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(nasm.info)Appendix B

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Appendix B: x86 Instruction Reference
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   This appendix provides a complete list of the machine instructions
which NASM will assemble, and a short description of the function of
each one.

   It is not intended to be exhaustive documentation on the fine
details of the instructions' function, such as which exceptions they
can trigger: for such documentation, you should go to Intel's Web site,
`http://developer.intel.com/design/Pentium4/manuals/'.

   Instead, this appendix is intended primarily to provide
documentation on the way the instructions may be used within NASM. For
example, looking up `LOOP' will tell you that NASM allows `CX' or `ECX'
to be specified as an optional second argument to the `LOOP'
instruction, to enforce which of the two possible counter registers
should be used if the default is not the one desired.

   The instructions are not quite listed in alphabetical order, since
groups of instructions with similar functions are lumped together in
the same entry. Most of them don't move very far from their alphabetic
position because of this.

Section B.1

Key to Operand Specifications

Section B.2

Key to Opcode Descriptions

Section B.3

Key to Instruction Flags

Section B.4

x86 Instruction Set