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\f0\froman Times New Roman;\f1\fmodern Courier New;
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#{\footnote Top}
${\footnote Contents}
+{\footnote browse:00000}
!{\footnote DisableButton("btn_up")}
\keepn\f2\b\fs30\sb0
NASM: The Netwide Assembler
\par\pard\plain\sb120
This file documents NASM, the Netwide Assembler: an assembler 
targetting the Intel x86 series of processors, with portable source.
\par\sb120
\li360\fi-360
{\uldb Chapter 1: Introduction}{\v chapter_1}\par\sb0
{\uldb Chapter 2: Running NASM}{\v chapter_2}\par\sb0
{\uldb Chapter 3: The NASM Language}{\v chapter_3}\par\sb0
{\uldb Chapter 4: The NASM Preprocessor}{\v chapter_4}\par\sb0
{\uldb Chapter 5: Assembler Directives}{\v chapter_5}\par\sb0
{\uldb Chapter 6: Output Formats}{\v chapter_6}\par\sb0
{\uldb Chapter 7: Writing 16-bit Code (DOS, Windows 3/3.1)}{\v chapter_7}\par\sb0
{\uldb Chapter 8: Writing 32-bit Code (Unix, Win32, DJGPP)}{\v chapter_8}\par\sb0
{\uldb Chapter 9: Mixing 16 and 32 Bit Code}{\v chapter_9}\par\sb0
{\uldb Chapter 10: Troubleshooting}{\v chapter_10}\par\sb0
{\uldb Appendix A: Ndisasm}{\v appendix_a}\par\sb0
{\uldb Appendix B: x86 Instruction Reference}{\v appendix_b}\par\sb0
\pard\sb120
\page
#{\footnote chapter_1}
${\footnote Chapter 1: Introduction}
+{\footnote browse:00001}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
Chapter 1: Introduction
\par\pard\plain\sb120
\li360\fi-360
{\uldb Section 1.1: What Is NASM?}{\v section_1_1}\par\sb0
{\uldb Section 1.2: Contact Information}{\v section_1_2}\par\sb0
{\uldb Section 1.3: Installation}{\v section_1_3}\par\sb0
\pard\sb120
\page
#{\footnote section_1_1}
${\footnote 1.1. What Is NASM?}
+{\footnote browse:00002}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_1')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
1.1. What Is NASM?
\par\pard\plain\sb120
The Netwide Assembler, NASM, is an 80x86 assembler designed for portability 
and modularity. It supports a range of object file formats, including Linux 
and {\f1 NetBSD/FreeBSD} {\f1 a.out}, {\f1 ELF}, {\f1 COFF}, Microsoft 
16-bit {\f1 OBJ} and {\f1 Win32}. It will also output plain binary files. 
Its syntax is designed to be simple and easy to understand, similar to 
Intel's but less complex. It supports {\f1 Pentium}, {\f1 P6}, {\f1 MMX}, 
{\f1 3DNow!}, {\f1 SSE} and {\f1 SSE2} opcodes, and has macro capability.
\par\sb120
\li360\fi-360
{\uldb Section 1.1.1: Why Yet Another Assembler?}{\v section_1_1_1}\par\sb0
{\uldb Section 1.1.2: Licence Conditions}{\v section_1_1_2}\par\sb0
\pard\sb120
\page
#{\footnote section_1_1_1}
${\footnote 1.1.1. Why Yet Another Assembler?}
+{\footnote browse:00003}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_1_1')");
EnableButton("btn_up")}
K{\footnote a86;
alt.lang.asm;
as86;
comp.lang.asm.x86;
gas;
gcc;
MASM;
TASM}
\keepn\f2\b\fs30\sb60\sa60
1.1.1. Why Yet Another Assembler?
\par\pard\plain\sb120
The Netwide Assembler grew out of an idea on {\f1 comp.lang.asm.x86} (or 
possibly {\f1 alt.lang.asm} \'96 I forget which), which was essentially 
that there didn't seem to be a good {\i free} x86-series assembler around, 
and that maybe someone ought to write one.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 a86} is good, but not free, and in particular you don't get any 32-bit 
capability until you pay. It's DOS only, too.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 gas} is free, and ports over DOS and Unix, but it's not very good, 
since it's designed to be a back end to {\f1 gcc}, which always feeds it 
correct code. So its error checking is minimal. Also, its syntax is 
horrible, from the point of view of anyone trying to actually {\i write} 
anything in it. Plus you can't write 16-bit code in it (properly).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 as86} is Minix- and Linux-specific, and (my version at least) doesn't 
seem to have much (or any) documentation.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 MASM} isn't very good, and it's (was) expensive, and it runs only 
under DOS.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 TASM} is better, but still strives for MASM compatibility, which means 
millions of directives and tons of red tape. And its syntax is essentially 
MASM's, with the contradictions and quirks that entails (although it sorts 
out some of those by means of Ideal mode). It's expensive too. And it's 
DOS-only.
\par\pard\sb120
So here, for your coding pleasure, is NASM. At present it's still in 
prototype stage \'96 we don't promise that it can outperform any of these 
assemblers. But please, {\i please} send us bug reports, fixes, helpful 
information, and anything else you can get your hands on (and thanks to the 
many people who've done this already! You all know who you are), and we'll 
improve it out of all recognition. Again.
\par\sb120
\page
#{\footnote section_1_1_2}
${\footnote 1.1.2. Licence Conditions}
+{\footnote browse:00004}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_1_1')");
EnableButton("btn_up")}
K{\footnote licence}
\keepn\f2\b\fs30\sb60\sa60
1.1.2. Licence Conditions
\par\pard\plain\sb120
Please see the file {\f1 COPYING}, supplied as part of any NASM 
distribution archive, for the licence conditions under which you may use 
NASM. NASM is now under the so-called GNU Lesser General Public License, 
LGPL.
\par\sb120
\page
#{\footnote section_1_2}
${\footnote 1.2. Contact Information}
+{\footnote browse:00005}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_1')");
EnableButton("btn_up")}
K{\footnote alt.lang.asm;
comp.lang.asm.x86;
comp.os.linux.announce;
e\'ADmail;
ftp.kernel.org;
ibiblio.org;
nasm\'ADdevel;
new releases;
WWW page}
\keepn\f2\b\fs30\sb60\sa60
1.2. Contact Information
\par\pard\plain\sb120
The current version of NASM (since about 0.98.08) are maintained by a team 
of developers, accessible through the {\f1 nasm\'ADdevel} mailing list (see 
below for the link). If you want to report a bug, please read 
{\uldb section 10.2}{\v section_10_2} first.
\par\sb120
NASM has a WWW page at {\f1 http://nasm.sourceforge.net}. If it's not 
there, google for us!
\par\sb120
The original authors are e\'ADmailable as {\f1 jules@dsf.org.uk} and 
{\f1 anakin@pobox.com}. The latter is no longer involved in the development 
team.
\par\sb120
New releases of NASM are uploaded to the official sites 
{\f1 http://nasm.sourceforge.net} and to {\f1 ftp.kernel.org} and 
{\f1 ibiblio.org}.
\par\sb120
Announcements are posted to {\f1 comp.lang.asm.x86}, {\f1 alt.lang.asm} and 
{\f1 comp.os.linux.announce}
\par\sb120
If you want information about NASM beta releases, and the current 
development status, please subscribe to the {\f1 nasm\'ADdevel} email list 
by registering at {\f1 http://sourceforge.net/projects/nasm}.
\par\sb120
\page
#{\footnote section_1_3}
${\footnote 1.3. Installation}
+{\footnote browse:00006}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_1')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
1.3. Installation
\par\pard\plain\sb120
\li360\fi-360
{\uldb Section 1.3.1: Installing NASM under MS-DOS or Windows}{\v section_1_3_1}\par\sb0
{\uldb Section 1.3.2: Installing NASM under Unix}{\v section_1_3_2}\par\sb0
\pard\sb120
\page
#{\footnote section_1_3_1}
${\footnote 1.3.1. Installing NASM under MS-DOS or Windows}
+{\footnote browse:00007}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_1_3')");
EnableButton("btn_up")}
K{\footnote autoexec.bat;
DOS;
DOS archive;
DOS source archive;
installing;
makefiles;
nasm.exe;
nasmw.exe;
nasmXXXs.zip;
nasmXXX.zip;
ndisasm.exe;
ndisasmw.exe;
PATH;
Perl;
source code;
Win32;
Windows 95;
Windows NT;
www.cpan.org}
\keepn\f2\b\fs30\sb60\sa60
1.3.1. Installing NASM under MS-DOS or Windows
\par\pard\plain\sb120
Once you've obtained the DOS archive for NASM, {\f1 nasmXXX.zip} (where 
{\f1 XXX} denotes the version number of NASM contained in the archive), 
unpack it into its own directory (for example {\f1 c:\\nasm}).
\par\sb120
The archive will contain four executable files: the NASM executable files 
{\f1 nasm.exe} and {\f1 nasmw.exe}, and the NDISASM executable files 
{\f1 ndisasm.exe} and {\f1 ndisasmw.exe}. In each case, the file whose name 
ends in {\f1 w} is a {\f1 Win32} executable, designed to run under 
{\f1 Windows\'A095} or  {\f1 Windows\'A0NT} Intel, and the other one is a 
16-bit {\f1 DOS} executable.
\par\sb120
The only file NASM needs to run is its own executable, so copy (at least) 
one of {\f1 nasm.exe} and {\f1 nasmw.exe} to a directory on your PATH, or 
alternatively edit {\f1 autoexec.bat} to add the {\f1 nasm} directory to 
your {\f1 PATH}. (If you're only installing the {\f1 Win32} version, you 
may wish to rename it to {\f1 nasm.exe}.)
\par\sb120
That's it \'96 NASM is installed. You don't need the nasm directory to be 
present to run NASM (unless you've added it to your {\f1 PATH}), so you can 
delete it if you need to save space; however, you may want to keep the 
documentation or test programs.
\par\sb120
If you've downloaded the DOS source archive, {\f1 nasmXXXs.zip}, the 
{\f1 nasm} directory will also contain the full NASM source code, and a 
selection of Makefiles you can (hopefully) use to rebuild your copy of NASM 
from scratch.
\par\sb120
Note that the source files {\f1 insnsa.c}, {\f1 insnsd.c}, {\f1 insnsi.h} 
and {\f1 insnsn.c} are automatically generated from the master instruction 
table {\f1 insns.dat} by a Perl script; the file {\f1 macros.c} is 
generated from {\f1 standard.mac} by another Perl script. Although the NASM 
source distribution includes these generated files, you will need to 
rebuild them (and hence, will need a Perl interpreter) if you change 
insns.dat, standard.mac or the documentation. It is possible future source 
distributions may not include these files at all. Ports of Perl for a 
variety of platforms, including DOS and Windows, are available from 
www.cpan.org.
\par\sb120
\page
#{\footnote section_1_3_2}
${\footnote 1.3.2. Installing NASM under Unix}
+{\footnote browse:00008}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_1_3')");
EnableButton("btn_up")}
K{\footnote Autoconf;
configure;
INSTALL;
make;
makefiles;
Makefile.unx;
man pages;
nasm.1;
nasm\'ADX.XX.tar.gz;
ndisasm.1;
rdoff subdirectory;
Unix;
Unix, source archive}
\keepn\f2\b\fs30\sb60\sa60
1.3.2. Installing NASM under Unix
\par\pard\plain\sb120
Once you've obtained the Unix source archive for NASM, 
{\f1 nasm\'ADX.XX.tar.gz} (where {\f1 X.XX} denotes the version number of 
NASM contained in the archive), unpack it into a directory such as 
{\f1 /usr/local/src}. The archive, when unpacked, will create its own 
subdirectory {\f1 nasm\'ADX.XX}.
\par\sb120
NASM is an auto-configuring package: once you've unpacked it, {\f1 cd} to 
the directory it's been unpacked into and type {\f1 ./configure}. This 
shell script will find the best C compiler to use for building NASM and set 
up Makefiles accordingly.
\par\sb120
Once NASM has auto-configured, you can type {\f1 make} to build the 
{\f1 nasm} and {\f1 ndisasm} binaries, and then {\f1 make\'A0install} to 
install them in {\f1 /usr/local/bin} and install the man pages {\f1 nasm.1} 
and {\f1 ndisasm.1} in {\f1 /usr/local/man/man1}. Alternatively, you can 
give options such as {\f1 \'AD\'ADprefix} to the configure script (see the 
file {\f1 INSTALL} for more details), or install the programs yourself.
\par\sb120
NASM also comes with a set of utilities for handling the {\f1 RDOFF} custom 
object-file format, which are in the {\f1 rdoff} subdirectory of the NASM 
archive. You can build these with {\f1 make\'A0rdf} and install them with 
{\f1 make\'A0rdf_install}, if you want them.
\par\sb120
If NASM fails to auto-configure, you may still be able to make it compile 
by using the fall-back Unix makefile {\f1 Makefile.unx}. Copy or rename 
that file to {\f1 Makefile} and try typing {\f1 make}. There is also a 
Makefile.unx file in the {\f1 rdoff} subdirectory.
\par\sb120
\page
#{\footnote chapter_2}
${\footnote Chapter 2: Running NASM}
+{\footnote browse:00009}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
Chapter 2: Running NASM
\par\pard\plain\sb120
\li360\fi-360
{\uldb Section 2.1: NASM Command\'ADLine Syntax}{\v section_2_1}\par\sb0
{\uldb Section 2.2: Quick Start for MASM Users}{\v section_2_2}\par\sb0
\pard\sb120
\page
#{\footnote section_2_1}
${\footnote 2.1. NASM Command\'ADLine Syntax}
+{\footnote browse:00010}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_2')");
EnableButton("btn_up")}
K{\footnote command\'ADline}
\keepn\f2\b\fs30\sb60\sa60
2.1. NASM Command\'ADLine Syntax
\par\pard\plain\sb120
To assemble a file, you issue a command of the form
\par\sb120
\keep\f1\sb120
nasm -f <format> <filename> [-o <output>]\par\sb0
\pard\f0\sb120
For example,
\par\sb120
\keep\f1\sb120
nasm -f elf myfile.asm\par\sb0
\pard\f0\sb120
will assemble {\f1 myfile.asm} into an {\f1 ELF} object file 
{\f1 myfile.o}. And
\par\sb120
\keep\f1\sb120
nasm -f bin myfile.asm -o myfile.com\par\sb0
\pard\f0\sb120
will assemble {\f1 myfile.asm} into a raw binary file {\f1 myfile.com}.
\par\sb120
To produce a listing file, with the hex codes output from NASM displayed on 
the left of the original sources, use the {\f1 \'ADl} option to give a 
listing file name, for example:
\par\sb120
\keep\f1\sb120
nasm -f coff myfile.asm -l myfile.lst\par\sb0
\pard\f0\sb120
To get further usage instructions from NASM, try typing
\par\sb120
\keep\f1\sb120
nasm -h\par\sb0
\pard\f0\sb120
As {\f1 \'ADhf}, this will also list the available output file formats, and 
what they are.
\par\sb120
If you use Linux but aren't sure whether your system is {\f1 a.out} or 
{\f1 ELF}, type
\par\sb120
\keep\f1\sb120
file nasm\par\sb0
\pard\f0\sb120
(in the directory in which you put the NASM binary when you installed it). 
If it says something like
\par\sb120
\keep\f1\sb120
nasm: ELF 32-bit LSB executable i386 (386 and up) Version 1\par\sb0
\pard\f0\sb120
then your system is {\f1 ELF}, and you should use the option 
{\f1 \'ADf\'A0elf} when you want NASM to produce Linux object files. If it 
says
\par\sb120
\keep\f1\sb120
nasm: Linux/i386 demand-paged executable (QMAGIC)\par\sb0
\pard\f0\sb120
or something similar, your system is {\f1 a.out}, and you should use 
{\f1 \'ADf\'A0aout} instead (Linux {\f1 a.out} systems have long been 
obsolete, and are rare these days.)
\par\sb120
Like Unix compilers and assemblers, NASM is silent unless it goes wrong: 
you won't see any output at all, unless it gives error messages.
\par\sb120
\li360\fi-360
{\uldb Section 2.1.1: The \'ADo Option: Specifying the Output File Name}{\v section_2_1_1}\par\sb0
{\uldb Section 2.1.2: The \'ADf Option: Specifying the Output File Format}{\v section_2_1_2}\par\sb0
{\uldb Section 2.1.3: The \'ADl Option: Generating a Listing File}{\v section_2_1_3}\par\sb0
{\uldb Section 2.1.4: The \'ADM Option: Generate Makefile Dependencies.}{\v section_2_1_4}\par\sb0
{\uldb Section 2.1.5: The \'ADF Option: Selecting a Debug Information Format}{\v section_2_1_5}\par\sb0
{\uldb Section 2.1.6: The \'ADg Option: Enabling Debug Information.}{\v section_2_1_6}\par\sb0
{\uldb Section 2.1.7: The \'ADX Option: Selecting an Error Reporting Format}{\v section_2_1_7}\par\sb0
{\uldb Section 2.1.8: The \'ADE Option: Send Errors to a File}{\v section_2_1_8}\par\sb0
{\uldb Section 2.1.9: The \'ADs Option: Send Errors to stdout}{\v section_2_1_9}\par\sb0
{\uldb Section 2.1.10: The \'ADi Option: Include File Search Directories}{\v section_2_1_10}\par\sb0
{\uldb Section 2.1.11: The \'ADp Option: Pre-Include a File}{\v section_2_1_11}\par\sb0
{\uldb Section 2.1.12: The \'ADd Option: Pre-Define a Macro}{\v section_2_1_12}\par\sb0
{\uldb Section 2.1.13: The \'ADu Option: Undefine a Macro}{\v section_2_1_13}\par\sb0
{\uldb Section 2.1.14: The \'ADe Option: Preprocess Only}{\v section_2_1_14}\par\sb0
{\uldb Section 2.1.15: The \'ADa Option: Don't Preprocess At All}{\v section_2_1_15}\par\sb0
{\uldb Section 2.1.16: The \'ADOn Option: Specifying Multipass Optimization.}{\v section_2_1_16}\par\sb0
{\uldb Section 2.1.17: The \'ADt option: Enable TASM Compatibility Mode}{\v section_2_1_17}\par\sb0
{\uldb Section 2.1.18: The \'ADw Option: Enable or Disable Assembly Warnings}{\v section_2_1_18}\par\sb0
{\uldb Section 2.1.19: The \'ADv Option: Display Version Info}{\v section_2_1_19}\par\sb0
{\uldb Section 2.1.20: The \'ADy Option: Display Available Debug Info Formats}{\v section_2_1_20}\par\sb0
{\uldb Section 2.1.21: The \'AD\'ADprefix and \'AD\'ADpostfix Options.}{\v section_2_1_21}\par\sb0
{\uldb Section 2.1.22: The NASMENV Environment Variable}{\v section_2_1_22}\par\sb0
\pard\sb120
\page
#{\footnote section_2_1_1}
${\footnote 2.1.1. The \'ADo Option: Specifying the Output File Name}
+{\footnote browse:00011}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote aout;
as86;
bin;
coff;
ELF;
extension;
nasm.out;
\'ADo option;
obj;
rdf;
Win32}
\keepn\f2\b\fs30\sb60\sa60
2.1.1. The {\f1 \'ADo} Option: Specifying the Output File Name
\par\pard\plain\sb120
NASM will normally choose the name of your output file for you; precisely 
how it does this is dependent on the object file format. For Microsoft 
object file formats ({\f1 obj} and {\f1 win32}), it will remove the 
{\f1 .asm} extension (or whatever extension you like to use \'96 NASM 
doesn't care) from your source file name and substitute {\f1 .obj}. For 
Unix object file formats ({\f1 aout}, {\f1 coff}, {\f1 elf} and {\f1 as86}) 
it will substitute {\f1 .o}. For {\f1 rdf}, it will use {\f1 .rdf}, and for 
the {\f1 bin} format it will simply remove the extension, so that 
{\f1 myfile.asm} produces the output file {\f1 myfile}.
\par\sb120
If the output file already exists, NASM will overwrite it, unless it has 
the same name as the input file, in which case it will give a warning and 
use {\f1 nasm.out} as the output file name instead.
\par\sb120
For situations in which this behaviour is unacceptable, NASM provides the 
{\f1 \'ADo} command-line option, which allows you to specify your desired 
output file name. You invoke {\f1 \'ADo} by following it with the name you 
wish for the output file, either with or without an intervening space. For 
example:
\par\sb120
\keep\f1\sb120
nasm -f bin program.asm -o program.com \par\sb0
nasm -f bin driver.asm -odriver.sys\par\sb0
\pard\f0\sb120
Note that this is a small o, and is different from a capital O , which is 
used to specify the number of optimisation passes required. See 
{\uldb section 2.1.16}{\v section_2_1_16}.
\par\sb120
\page
#{\footnote section_2_1_2}
${\footnote 2.1.2. The \'ADf Option: Specifying the Output File Format}
+{\footnote browse:00012}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote bin;
\'ADf option;
nasm\'A0\'ADhf;
OF_DEFAULT;
output file format}
\keepn\f2\b\fs30\sb60\sa60
2.1.2. The {\f1 \'ADf} Option: Specifying the Output File Format
\par\pard\plain\sb120
If you do not supply the {\f1 \'ADf} option to NASM, it will choose an 
output file format for you itself. In the distribution versions of NASM, 
the default is always {\f1 bin}; if you've compiled your own copy of NASM, 
you can redefine {\f1 OF_DEFAULT} at compile time and choose what you want 
the default to be.
\par\sb120
Like {\f1 \'ADo}, the intervening space between {\f1 \'ADf} and the output 
file format is optional; so {\f1 \'ADf\'A0elf} and {\f1 \'ADfelf} are both 
valid.
\par\sb120
A complete list of the available output file formats can be given by 
issuing the command {\f1 nasm\'A0\'ADhf}.
\par\sb120
\page
#{\footnote section_2_1_3}
${\footnote 2.1.3. The \'ADl Option: Generating a Listing File}
+{\footnote browse:00013}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADl option;
listing file;
source\'ADlisting file}
\keepn\f2\b\fs30\sb60\sa60
2.1.3. The {\f1 \'ADl} Option: Generating a Listing File
\par\pard\plain\sb120
If you supply the {\f1 \'ADl} option to NASM, followed (with the usual 
optional space) by a file name, NASM will generate a source\'ADlisting file 
for you, in which addresses and generated code are listed on the left, and 
the actual source code, with expansions of multi-line macros (except those 
which specifically request no expansion in source listings: see 
{\uldb section 4.3.9}{\v section_4_3_9}) on the right. For example:
\par\sb120
\keep\f1\sb120
nasm -f elf myfile.asm -l myfile.lst\par\sb0
\pard\f0\sb120
If a list file is selected, you may turn off listing for a section of your 
source with {\f1 [list\'A0\'AD]}, and turn it back on with 
{\f1 [list\'A0+]}, (the default, obviously). There is no "user form" 
(without the brackets). This can be used to list only sections of interest, 
avoiding excessively long listings.
\par\sb120
\page
#{\footnote section_2_1_4}
${\footnote 2.1.4. The \'ADM Option: Generate Makefile Dependencies.}
+{\footnote browse:00014}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADM option;
makefile dependencies}
\keepn\f2\b\fs30\sb60\sa60
2.1.4. The {\f1 \'ADM} Option: Generate Makefile Dependencies.
\par\pard\plain\sb120
This option can be used to generate makefile dependencies on stdout. This 
can be redirected to a file for further processing. For example:
\par\sb120
\keep\f1\sb120
NASM -M myfile.asm > myfile.dep\par\sb0
\pard\f0\sb120
\page
#{\footnote section_2_1_5}
${\footnote 2.1.5. The \'ADF Option: Selecting a Debug Information Format}
+{\footnote browse:00015}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote debug information format;
\'ADF option;
nasm\'A0\'ADf\'A0<format>\'A0\'ADy}
\keepn\f2\b\fs30\sb60\sa60
2.1.5. The {\f1 \'ADF} Option: Selecting a Debug Information Format
\par\pard\plain\sb120
This option is used to select the format of the debug information emitted 
into the output file, to be used by a debugger (or {\i will} be). Use of 
this switch does {\i not} enable output of the selected debug info format. 
Use {\f1 \'ADg}, see {\uldb section 2.1.6}{\v section_2_1_6}, to enable 
output.
\par\sb120
A complete list of the available debug file formats for an output format 
can be seen by issuing the command 
{\f1 nasm\'A0\'ADf\'A0<format>\'A0\'ADy}. (only "borland" in "-f obj", as 
of 0.98.35, but "watch this space") See: {\uldb section 
2.1.20}{\v section_2_1_20}.
\par\sb120
This should not be confused with the "-f dbg" output format option which is 
not built into NASM by default. For information on how to enable it when 
building from the sources, see {\uldb section 6.10}{\v section_6_10}
\par\sb120
\page
#{\footnote section_2_1_6}
${\footnote 2.1.6. The \'ADg Option: Enabling Debug Information.}
+{\footnote browse:00016}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote debug information;
\'ADg option}
\keepn\f2\b\fs30\sb60\sa60
2.1.6. The {\f1 \'ADg} Option: Enabling Debug Information.
\par\pard\plain\sb120
This option can be used to generate debugging information in the specified 
format. See: {\uldb section 2.1.5}{\v section_2_1_5}. Using {\f1 \'ADg} 
without {\f1 \'ADF} results in emitting debug info in the default format, 
if any, for the selected output format. If no debug information is 
currently implemented in the selected output format, {\f1 \'ADg} is 
{\i silently ignored}.
\par\sb120
\page
#{\footnote section_2_1_7}
${\footnote 2.1.7. The \'ADX Option: Selecting an Error Reporting Format}
+{\footnote browse:00017}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote error reporting format;
\'ADX option}
\keepn\f2\b\fs30\sb60\sa60
2.1.7. The {\f1 \'ADX} Option: Selecting an Error Reporting Format
\par\pard\plain\sb120
This option can be used to select an error reporting format for any error 
messages that might be produced by NASM.
\par\sb120
Currently, two error reporting formats may be selected. They are the 
{\f1 \'ADXvc} option and the {\f1 \'ADXgnu} option. The GNU format is the 
default and looks like this:
\par\sb120
\keep\f1\sb120
filename.asm:65: error: specific error message \par\sb0
\pard\f0\sb120
where {\f1 filename.asm} is the name of the source file in which the error 
was detected, {\f1 65} is the source file line number on which the error 
was detected, {\f1 error} is the severity of the error (this could be 
{\f1 warning}), and {\f1 specific\'A0error\'A0message} is a more detailed 
text message which should help pinpoint the exact problem.
\par\sb120
The other format, specified by {\f1 \'ADXvc} is the style used by Microsoft 
Visual C++ and some other programs. It looks like this:
\par\sb120
\keep\f1\sb120
filename.asm(65) : error: specific error message\par\sb0
\pard\f0\sb120
where the only difference is that the line number is in parentheses instead 
of being delimited by colons.
\par\sb120
See also the {\f1 Visual\'A0C++} output format, {\uldb section 
6.3}{\v section_6_3}.
\par\sb120
\page
#{\footnote section_2_1_8}
${\footnote 2.1.8. The \'ADE Option: Send Errors to a File}
+{\footnote browse:00018}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote DOS;
\'ADE option;
error messages;
redirecting errors;
stderr}
\keepn\f2\b\fs30\sb60\sa60
2.1.8. The {\f1 \'ADE} Option: Send Errors to a File
\par\pard\plain\sb120
Under {\f1 MS\'ADDOS} it can be difficult (though there are ways) to 
redirect the standard-error output of a program to a file. Since NASM 
usually produces its warning and error messages on {\f1 stderr}, this can 
make it hard to capture the errors if (for example) you want to load them 
into an editor.
\par\sb120
NASM therefore provides the {\f1 \'ADE} option, taking a filename argument 
which causes errors to be sent to the specified files rather than standard 
error. Therefore you can redirect the errors into a file by typing
\par\sb120
\keep\f1\sb120
nasm -E myfile.err -f obj myfile.asm\par\sb0
\pard\f0\sb120
\page
#{\footnote section_2_1_9}
${\footnote 2.1.9. The \'ADs Option: Send Errors to stdout}
+{\footnote browse:00019}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote DOS;
error messages;
\'ADs option;
stdout}
\keepn\f2\b\fs30\sb60\sa60
2.1.9. The {\f1 \'ADs} Option: Send Errors to {\f1 stdout}
\par\pard\plain\sb120
The {\f1 \'ADs} option redirects error messages to {\f1 stdout} rather than 
{\f1 stderr}, so it can be redirected under {\f1 MS\'ADDOS}. To assemble 
the file {\f1 myfile.asm} and pipe its output to the {\f1 more} program, 
you can type:
\par\sb120
\keep\f1\sb120
nasm -s -f obj myfile.asm | more\par\sb0
\pard\f0\sb120
See also the {\f1 \'ADE} option, {\uldb section 2.1.8}{\v section_2_1_8}.
\par\sb120
\page
#{\footnote section_2_1_10}
${\footnote 2.1.10. The \'ADi Option: Include File Search Directories}
+{\footnote browse:00020}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADI option;
\'ADi option;
incbin;
%include;
include search path;
macro library;
perverse}
\keepn\f2\b\fs30\sb60\sa60
2.1.10. The {\f1 \'ADi} Option: Include File Search Directories
\par\pard\plain\sb120
When NASM sees the {\f1 %include} or {\f1 incbin} directive in a source 
file (see {\uldb section 4.6}{\v section_4_6} or {\uldb section 
3.2.3}{\v section_3_2_3}), it will search for the given file not only in 
the current directory, but also in any directories specified on the command 
line by the use of the {\f1 \'ADi} option. Therefore you can include files 
from a macro library, for example, by typing
\par\sb120
\keep\f1\sb120
nasm -ic:\\macrolib\\ -f obj myfile.asm\par\sb0
\pard\f0\sb120
(As usual, a space between {\f1 \'ADi} and the path name is allowed, and 
optional).
\par\sb120
NASM, in the interests of complete source-code portability, does not 
understand the file naming conventions of the OS it is running on; the 
string you provide as an argument to the {\f1 \'ADi} option will be 
prepended exactly as written to the name of the include file. Therefore the 
trailing backslash in the above example is necessary. Under Unix, a 
trailing forward slash is similarly necessary.
\par\sb120
(You can use this to your advantage, if you're really perverse, by noting 
that the option {\f1 \'ADifoo} will cause {\f1 %include\'A0"bar.i"} to 
search for the file {\f1 foobar.i}...)
\par\sb120
If you want to define a {\i standard} include search path, similar to 
{\f1 /usr/include} on Unix systems, you should place one or more 
{\f1 \'ADi} directives in the {\f1 NASMENV} environment variable (see 
{\uldb section 2.1.22}{\v section_2_1_22}).
\par\sb120
For Makefile compatibility with many C compilers, this option can also be 
specified as {\f1 \'ADI}.
\par\sb120
\page
#{\footnote section_2_1_11}
${\footnote 2.1.11. The \'ADp Option: Pre-Include a File}
+{\footnote browse:00021}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote %include;
\'ADP option;
\'ADp option;
pre\'ADincluding files}
\keepn\f2\b\fs30\sb60\sa60
2.1.11. The {\f1 \'ADp} Option: Pre-Include a File
\par\pard\plain\sb120
NASM allows you to specify files to be {\i pre\'ADincluded} into your 
source file, by the use of the {\f1 \'ADp} option. So running
\par\sb120
\keep\f1\sb120
nasm myfile.asm -p myinc.inc\par\sb0
\pard\f0\sb120
is equivalent to running {\f1 nasm\'A0myfile.asm} and placing the directive 
{\f1 %include\'A0"myinc.inc"} at the start of the file.
\par\sb120
For consistency with the {\f1 \'ADI}, {\f1 \'ADD} and {\f1 \'ADU} options, 
this option can also be specified as {\f1 \'ADP}.
\par\sb120
\page
#{\footnote section_2_1_12}
${\footnote 2.1.12. The \'ADd Option: Pre-Define a Macro}
+{\footnote browse:00022}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote assembly\'ADtime options;
\'ADD option;
\'ADd option;
%define;
pre\'ADdefining macros}
\keepn\f2\b\fs30\sb60\sa60
2.1.12. The {\f1 \'ADd} Option: Pre-Define a Macro
\par\pard\plain\sb120
Just as the {\f1 \'ADp} option gives an alternative to placing 
{\f1 %include} directives at the start of a source file, the {\f1 \'ADd} 
option gives an alternative to placing a {\f1 %define} directive. You could 
code
\par\sb120
\keep\f1\sb120
nasm myfile.asm -dFOO=100\par\sb0
\pard\f0\sb120
as an alternative to placing the directive
\par\sb120
\keep\f1\sb120
%define FOO 100\par\sb0
\pard\f0\sb120
at the start of the file. You can miss off the macro value, as well: the 
option {\f1 \'ADdFOO} is equivalent to coding {\f1 %define\'A0FOO}. This 
form of the directive may be useful for selecting assembly\'ADtime options 
which are then tested using {\f1 %ifdef}, for example {\f1 \'ADdDEBUG}.
\par\sb120
For Makefile compatibility with many C compilers, this option can also be 
specified as {\f1 \'ADD}.
\par\sb120
\page
#{\footnote section_2_1_13}
${\footnote 2.1.13. The \'ADu Option: Undefine a Macro}
+{\footnote browse:00023}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADU option;
\'ADu option;
%undef;
undefining macros}
\keepn\f2\b\fs30\sb60\sa60
2.1.13. The {\f1 \'ADu} Option: Undefine a Macro
\par\pard\plain\sb120
The {\f1 \'ADu} option undefines a macro that would otherwise have been 
pre-defined, either automatically or by a {\f1 \'ADp} or {\f1 \'ADd} option 
specified earlier on the command lines.
\par\sb120
For example, the following command line:
\par\sb120
\keep\f1\sb120
nasm myfile.asm -dFOO=100 -uFOO\par\sb0
\pard\f0\sb120
would result in {\f1 FOO} {\i not} being a predefined macro in the program. 
This is useful to override options specified at a different point in a 
Makefile.
\par\sb120
For Makefile compatibility with many C compilers, this option can also be 
specified as {\f1 \'ADU}.
\par\sb120
\page
#{\footnote section_2_1_14}
${\footnote 2.1.14. The \'ADe Option: Preprocess Only}
+{\footnote browse:00024}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADe option;
expressions;
preprocess\'ADonly mode;
preprocessor;
preprocessor expressions}
\keepn\f2\b\fs30\sb60\sa60
2.1.14. The {\f1 \'ADe} Option: Preprocess Only
\par\pard\plain\sb120
NASM allows the preprocessor to be run on its own, up to a point. Using the 
{\f1 \'ADe} option (which requires no arguments) will cause NASM to 
preprocess its input file, expand all the macro references, remove all the 
comments and preprocessor directives, and print the resulting file on 
standard output (or save it to a file, if the {\f1 \'ADo} option is also 
used).
\par\sb120
This option cannot be applied to programs which require the preprocessor to 
evaluate expressions which depend on the values of symbols: so code such as
\par\sb120
\keep\f1\sb120
%assign tablesize ($-tablestart)\par\sb0
\pard\f0\sb120
will cause an error in preprocess\'ADonly mode.
\par\sb120
\page
#{\footnote section_2_1_15}
${\footnote 2.1.15. The \'ADa Option: Don't Preprocess At All}
+{\footnote browse:00025}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADa option;
preprocessor;
stub preprocessor;
suppressing preprocessing}
\keepn\f2\b\fs30\sb60\sa60
2.1.15. The {\f1 \'ADa} Option: Don't Preprocess At All
\par\pard\plain\sb120
If NASM is being used as the back end to a compiler, it might be desirable 
to suppress preprocessing completely and assume the compiler has already 
done it, to save time and increase compilation speeds. The {\f1 \'ADa} 
option, requiring no argument, instructs NASM to replace its powerful 
preprocessor with a stub preprocessor which does nothing.
\par\sb120
\page
#{\footnote section_2_1_16}
${\footnote 2.1.16. The \'ADOn Option: Specifying Multipass Optimization.}
+{\footnote browse:00026}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote multipass optimization;
\'ADOn option}
\keepn\f2\b\fs30\sb60\sa60
2.1.16. The {\f1 \'ADOn} Option: Specifying Multipass Optimization.
\par\pard\plain\sb120
NASM defaults to being a two pass assembler. This means that if you have a 
complex source file which needs more than 2 passes to assemble optimally, 
you have to enable extra passes.
\par\sb120
Using the {\f1 \'ADO} option, you can tell NASM to carry out multiple 
passes. The syntax is:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 \'ADO0} strict two-pass assembly, JMP and Jcc are handled more like 
v0.98, except that backward JMPs are short, if possible. Immediate operands 
take their long forms if a short form is not specified.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 \'ADO1} strict two-pass assembly, but forward branches are assembled 
with code guaranteed to reach; may produce larger code than \'96O0, but 
will produce successful assembly more often if branch offset sizes are not 
specified. Additionally, immediate operands which will fit in a signed byte 
are optimised, unless the long form is specified.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 \'ADOn} multi-pass optimization, minimize branch offsets; also will 
minimize signed immediate bytes, overriding size specification unless the 
{\f1 strict} keyword has been used (see {\uldb section 
3.7}{\v section_3_7}). The number specifies the maximum number of passes. 
The more passes, the better the code, but the slower is the assembly.
\par\pard\sb120
Note that this is a capital O, and is different from a small o, which is 
used to specify the output format. See {\uldb section 
2.1.1}{\v section_2_1_1}.
\par\sb120
\page
#{\footnote section_2_1_17}
${\footnote 2.1.17. The \'ADt option: Enable TASM Compatibility Mode}
+{\footnote browse:00027}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADt;
TASM}
\keepn\f2\b\fs30\sb60\sa60
2.1.17. The {\f1 \'ADt} option: Enable TASM Compatibility Mode
\par\pard\plain\sb120
NASM includes a limited form of compatibility with Borland's {\f1 TASM}. 
When NASM's {\f1 \'ADt} option is used, the following changes are made:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
local labels may be prefixed with {\f1 @@} instead of {\f1 .}
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
TASM-style response files beginning with {\f1 @} may be specified on the 
command line. This is different from the {\f1 \'AD@resp} style that NASM 
natively supports.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
size override is supported within brackets. In TASM compatible mode, a size 
override inside square brackets changes the size of the operand, and not 
the address type of the operand as it does in NASM syntax. E.g. 
{\f1 mov\'A0eax,[DWORD\'A0val]} is valid syntax in TASM compatibility mode. 
Note that you lose the ability to override the default address type for the 
instruction.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 %arg} preprocessor directive is supported which is similar to TASM's 
{\f1 ARG} directive.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 %local} preprocessor directive
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 %stacksize} preprocessor directive
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
unprefixed forms of some directives supported ({\f1 arg}, {\f1 elif}, 
{\f1 else}, {\f1 endif}, {\f1 if}, {\f1 ifdef}, {\f1 ifdifi}, {\f1 ifndef}, 
{\f1 include}, {\f1 local})
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
more...
\par\pard\sb120
For more information on the directives, see the section on TASM 
Compatiblity preprocessor directives in {\uldb section 
4.9}{\v section_4_9}.
\par\sb120
\page
#{\footnote section_2_1_18}
${\footnote 2.1.18. The \'ADw Option: Enable or Disable Assembly Warnings}
+{\footnote browse:00028}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote gnu\'ADelf\'ADextensions;
macro\'ADparams;
macro\'ADselfref;
multi\'ADline macros;
number\'ADoverflow;
orphan\'ADlabels;
suppressible warning;
\'ADw option;
warnings;
[warning\'A0+warning\'ADname];
[warning\'A0\'ADwarning\'ADname]}
\keepn\f2\b\fs30\sb60\sa60
2.1.18. The {\f1 \'ADw} Option: Enable or Disable Assembly Warnings
\par\pard\plain\sb120
NASM can observe many conditions during the course of assembly which are 
worth mentioning to the user, but not a sufficiently severe error to 
justify NASM refusing to generate an output file. These conditions are 
reported like errors, but come up with the word `warning' before the 
message. Warnings do not prevent NASM from generating an output file and 
returning a success status to the operating system.
\par\sb120
Some conditions are even less severe than that: they are only sometimes 
worth mentioning to the user. Therefore NASM supports the {\f1 \'ADw} 
command-line option, which enables or disables certain classes of assembly 
warning. Such warning classes are described by a name, for example 
{\f1 orphan\'ADlabels}; you can enable warnings of this class by the 
command-line option {\f1 \'ADw+orphan\'ADlabels} and disable it by 
{\f1 \'ADw\'ADorphan\'ADlabels}.
\par\sb120
The suppressible warning classes are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 macro\'ADparams} covers warnings about multi\'ADline macros being 
invoked with the wrong number of parameters. This warning class is enabled 
by default; see {\uldb section 4.3.1}{\v section_4_3_1} for an example of 
why you might want to disable it.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 macro\'ADselfref} warns if a macro references itself. This warning 
class is enabled by default.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 orphan\'ADlabels} covers warnings about source lines which contain no 
instruction but define a label without a trailing colon. NASM does not warn 
about this somewhat obscure condition by default; see {\uldb section 
3.1}{\v section_3_1} for an example of why you might want it to.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 number\'ADoverflow} covers warnings about numeric constants which 
don't fit in 32 bits (for example, it's easy to type one too many Fs and 
produce {\f1 0x7ffffffff} by mistake). This warning class is enabled by 
default.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 gnu\'ADelf\'ADextensions} warns if 8-bit or 16-bit relocations are 
used in {\f1 \'ADf\'A0elf} format. The GNU extensions allow this. This 
warning class is enabled by default.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
In addition, warning classes may be enabled or disabled across sections of 
source code with {\f1 [warning\'A0+warning\'ADname]} or 
{\f1 [warning\'A0\'ADwarning\'ADname]}. No "user form" (without the 
brackets) exists.
\par\pard\sb120
\page
#{\footnote section_2_1_19}
${\footnote 2.1.19. The \'ADv Option: Display Version Info}
+{\footnote browse:00029}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADv option;
version}
\keepn\f2\b\fs30\sb60\sa60
2.1.19. The {\f1 \'ADv} Option: Display Version Info
\par\pard\plain\sb120
Typing {\f1 NASM\'A0\'ADv} will display the version of NASM which you are 
using, and the date on which it was compiled. This replaces the deprecated 
{\f1 \'ADr}.
\par\sb120
You will need the version number if you report a bug.
\par\sb120
\page
#{\footnote section_2_1_20}
${\footnote 2.1.20. The \'ADy Option: Display Available Debug Info Formats}
+{\footnote browse:00030}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'ADy option}
\keepn\f2\b\fs30\sb60\sa60
2.1.20. The {\f1 \'ADy} Option: Display Available Debug Info Formats
\par\pard\plain\sb120
Typing {\f1 nasm\'A0\'ADf\'A0<option>\'A0\'ADy} will display a list of the 
available debug info formats for the given output format. The default 
format is indicated by an asterisk. E.g. 
{\f1 nasm\'A0\'ADf\'A0obj\'A0\'ADy} yields {\f1 *\'A0borland}. (as of 
0.98.35, the {\i only} debug info format implemented).
\par\sb120
\page
#{\footnote section_2_1_21}
${\footnote 2.1.21. The \'AD\'ADprefix and \'AD\'ADpostfix Options.}
+{\footnote browse:00031}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote \'AD\'ADpostfix;
\'AD\'ADprefix}
\keepn\f2\b\fs30\sb60\sa60
2.1.21. The {\f1 \'AD\'ADprefix} and {\f1 \'AD\'ADpostfix} Options.
\par\pard\plain\sb120
The {\f1 \'AD\'ADprefix} and {\f1 \'AD\'ADpostfix} options prepend or 
append (respectively) the given argument to all {\f1 global} or 
{\f1 extern} variables. E.g. {\f1 \'AD\'ADprefix_} will prepend the 
underscore to all global and external variables, as C sometimes (but not 
always) likes it.
\par\sb120
\page
#{\footnote section_2_1_22}
${\footnote 2.1.22. The NASMENV Environment Variable}
+{\footnote browse:00032}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_1')");
EnableButton("btn_up")}
K{\footnote environment;
separator character}
\keepn\f2\b\fs30\sb60\sa60
2.1.22. The {\f1 NASMENV} Environment Variable
\par\pard\plain\sb120
If you define an environment variable called {\f1 NASMENV}, the program 
will interpret it as a list of extra command-line options, which are 
processed before the real command line. You can use this to define standard 
search directories for include files, by putting {\f1 \'ADi} options in the 
{\f1 NASMENV} variable.
\par\sb120
The value of the variable is split up at white space, so that the value 
{\f1 \'ADs\'A0\'ADic:\\nasmlib} will be treated as two separate options. 
However, that means that the value {\f1 \'ADdNAME="my\'A0name"} won't do 
what you might want, because it will be split at the space and the NASM 
command-line processing will get confused by the two nonsensical words 
{\f1 \'ADdNAME="my} and {\f1 name"}.
\par\sb120
To get round this, NASM provides a feature whereby, if you begin the 
{\f1 NASMENV} environment variable with some character that isn't a minus 
sign, then NASM will treat this character as the separator character for 
options. So setting the {\f1 NASMENV} variable to the value 
{\f1 !\'ADs!\'ADic:\\nasmlib} is equivalent to setting it to 
{\f1 \'ADs\'A0\'ADic:\\nasmlib}, but {\f1 !\'ADdNAME="my\'A0name"} will 
work.
\par\sb120
This environment variable was previously called {\f1 NASM}. This was 
changed with version 0.98.31.
\par\sb120
\page
#{\footnote section_2_2}
${\footnote 2.2. Quick Start for MASM Users}
+{\footnote browse:00033}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_2')");
EnableButton("btn_up")}
K{\footnote a86;
MASM;
quick start;
tasm}
\keepn\f2\b\fs30\sb60\sa60
2.2. Quick Start for MASM Users
\par\pard\plain\sb120
If you're used to writing programs with MASM, or with TASM in 
MASM-compatible (non-Ideal) mode, or with {\f1 a86}, this section attempts 
to outline the major differences between MASM's syntax and NASM's. If 
you're not already used to MASM, it's probably worth skipping this section.
\par\sb120
\li360\fi-360
{\uldb Section 2.2.1: NASM Is Case-Sensitive}{\v section_2_2_1}\par\sb0
{\uldb Section 2.2.2: NASM Requires Square Brackets For Memory References}{\v section_2_2_2}\par\sb0
{\uldb Section 2.2.3: NASM Doesn't Store Variable Types}{\v section_2_2_3}\par\sb0
{\uldb Section 2.2.4: NASM Doesn't ASSUME}{\v section_2_2_4}\par\sb0
{\uldb Section 2.2.5: NASM Doesn't Support Memory Models}{\v section_2_2_5}\par\sb0
{\uldb Section 2.2.6: Floating\'ADPoint Differences}{\v section_2_2_6}\par\sb0
{\uldb Section 2.2.7: Other Differences}{\v section_2_2_7}\par\sb0
\pard\sb120
\page
#{\footnote section_2_2_1}
${\footnote 2.2.1. NASM Is Case-Sensitive}
+{\footnote browse:00034}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_2')");
EnableButton("btn_up")}
K{\footnote case sensitivity;
UPPERCASE}
\keepn\f2\b\fs30\sb60\sa60
2.2.1. NASM Is Case-Sensitive
\par\pard\plain\sb120
One simple difference is that NASM is case-sensitive. It makes a difference 
whether you call your label {\f1 foo}, {\f1 Foo} or {\f1 FOO}. If you're 
assembling to {\f1 DOS} or {\f1 OS/2} {\f1 .OBJ} files, you can invoke the 
{\f1 UPPERCASE} directive (documented in {\uldb section 
6.2}{\v section_6_2}) to ensure that all symbols exported to other code 
modules are forced to be upper case; but even then, {\i within} a single 
module, NASM will distinguish between labels differing only in case.
\par\sb120
\page
#{\footnote section_2_2_2}
${\footnote 2.2.2. NASM Requires Square Brackets For Memory References}
+{\footnote browse:00035}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_2')");
EnableButton("btn_up")}
K{\footnote a86;
design goals;
hybrid syntaxes;
memory references;
OFFSET;
square brackets}
\keepn\f2\b\fs30\sb60\sa60
2.2.2. NASM Requires Square Brackets For Memory References
\par\pard\plain\sb120
NASM was designed with simplicity of syntax in mind. One of the design 
goals of NASM is that it should be possible, as far as is practical, for 
the user to look at a single line of NASM code and tell what opcode is 
generated by it. You can't do this in MASM: if you declare, for example,
\par\sb120
\keep\f1\sb120
foo     equ     1 \par\sb0
bar     dw      2\par\sb0
\pard\f0\sb120
then the two lines of code
\par\sb120
\keep\f1\sb120
        mov     ax,foo \par\sb0
        mov     ax,bar\par\sb0
\pard\f0\sb120
generate completely different opcodes, despite having identical-looking 
syntaxes.
\par\sb120
NASM avoids this undesirable situation by having a much simpler syntax for 
memory references. The rule is simply that any access to the {\i contents} 
of a memory location requires square brackets around the address, and any 
access to the {\i address} of a variable doesn't. So an instruction of the 
form {\f1 mov\'A0ax,foo} will {\i always} refer to a compile-time constant, 
whether it's an {\f1 EQU} or the address of a variable; and to access the 
{\i contents} of the variable {\f1 bar}, you must code 
{\f1 mov\'A0ax,[bar]}.
\par\sb120
This also means that NASM has no need for MASM's {\f1 OFFSET} keyword, 
since the MASM code {\f1 mov\'A0ax,offset\'A0bar} means exactly the same 
thing as NASM's {\f1 mov\'A0ax,bar}. If you're trying to get large amounts 
of MASM code to assemble sensibly under NASM, you can always code 
{\f1 %idefine\'A0offset} to make the preprocessor treat the {\f1 OFFSET} 
keyword as a no-op.
\par\sb120
This issue is even more confusing in {\f1 a86}, where declaring a label 
with a trailing colon defines it to be a `label' as opposed to a `variable' 
and causes {\f1 a86} to adopt NASM-style semantics; so in {\f1 a86}, 
{\f1 mov\'A0ax,var} has different behaviour depending on whether {\f1 var} 
was declared as {\f1 var:\'A0dw\'A00} (a label) or {\f1 var\'A0dw\'A00} (a 
word-size variable). NASM is very simple by comparison: {\i everything} is 
a label.
\par\sb120
NASM, in the interests of simplicity, also does not support the hybrid 
syntaxes supported by MASM and its clones, such as 
{\f1 mov\'A0ax,table[bx]}, where a memory reference is denoted by one 
portion outside square brackets and another portion inside. The correct 
syntax for the above is {\f1 mov\'A0ax,[table+bx]}. Likewise, 
{\f1 mov\'A0ax,es:[di]} is wrong and {\f1 mov\'A0ax,[es:di]} is right.
\par\sb120
\page
#{\footnote section_2_2_3}
${\footnote 2.2.3. NASM Doesn't Store Variable Types}
+{\footnote browse:00036}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_2')");
EnableButton("btn_up")}
K{\footnote ambiguity;
variable types}
\keepn\f2\b\fs30\sb60\sa60
2.2.3. NASM Doesn't Store Variable Types
\par\pard\plain\sb120
NASM, by design, chooses not to remember the types of variables you 
declare. Whereas MASM will remember, on seeing {\f1 var\'A0dw\'A00}, that 
you declared {\f1 var} as a word-size variable, and will then be able to 
fill in the ambiguity in the size of the instruction {\f1 mov\'A0var,2}, 
NASM will deliberately remember nothing about the symbol {\f1 var} except 
where it begins, and so you must explicitly code 
{\f1 mov\'A0word\'A0[var],2}.
\par\sb120
For this reason, NASM doesn't support the {\f1 LODS}, {\f1 MOVS}, 
{\f1 STOS}, {\f1 SCAS}, {\f1 CMPS}, {\f1 INS}, or {\f1 OUTS} instructions, 
but only supports the forms such as {\f1 LODSB}, {\f1 MOVSW}, and 
{\f1 SCASD}, which explicitly specify the size of the components of the 
strings being manipulated.
\par\sb120
\page
#{\footnote section_2_2_4}
${\footnote 2.2.4. NASM Doesn't ASSUME}
+{\footnote browse:00037}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_2')");
EnableButton("btn_up")}
K{\footnote ASSUME;
segment override}
\keepn\f2\b\fs30\sb60\sa60
2.2.4. NASM Doesn't {\f1 ASSUME}
\par\pard\plain\sb120
As part of NASM's drive for simplicity, it also does not support the 
{\f1 ASSUME} directive. NASM will not keep track of what values you choose 
to put in your segment registers, and will never {\i automatically} 
generate a segment override prefix.
\par\sb120
\page
#{\footnote section_2_2_5}
${\footnote 2.2.5. NASM Doesn't Support Memory Models}
+{\footnote browse:00038}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_2')");
EnableButton("btn_up")}
K{\footnote far call;
memory models;
near call}
\keepn\f2\b\fs30\sb60\sa60
2.2.5. NASM Doesn't Support Memory Models
\par\pard\plain\sb120
NASM also does not have any directives to support different 16-bit memory 
models. The programmer has to keep track of which functions are supposed to 
be called with a far call and which with a near call, and is responsible 
for putting the correct form of {\f1 RET} instruction ({\f1 RETN} or 
{\f1 RETF}; NASM accepts {\f1 RET} itself as an alternate form for 
{\f1 RETN}); in addition, the programmer is responsible for coding CALL FAR 
instructions where necessary when calling {\i external} functions, and must 
also keep track of which external variable definitions are far and which 
are near.
\par\sb120
\page
#{\footnote section_2_2_6}
${\footnote 2.2.6. Floating\'ADPoint Differences}
+{\footnote browse:00039}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_2')");
EnableButton("btn_up")}
K{\footnote a86;
floating\'ADpoint;
`nowait'}
\keepn\f2\b\fs30\sb60\sa60
2.2.6. Floating\'ADPoint Differences
\par\pard\plain\sb120
NASM uses different names to refer to floating-point registers from MASM: 
where MASM would call them {\f1 ST(0)}, {\f1 ST(1)} and so on, and 
{\f1 a86} would call them simply {\f1 0}, {\f1 1} and so on, NASM chooses 
to call them {\f1 st0}, {\f1 st1} etc.
\par\sb120
As of version 0.96, NASM now treats the instructions with `nowait' forms in 
the same way as MASM-compatible assemblers. The idiosyncratic treatment 
employed by 0.95 and earlier was based on a misunderstanding by the 
authors.
\par\sb120
\page
#{\footnote section_2_2_7}
${\footnote 2.2.7. Other Differences}
+{\footnote browse:00040}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_2_2')");
EnableButton("btn_up")}
K{\footnote DUP;
RESB;
TBYTE;
TWORD;
uninitialised storage}
\keepn\f2\b\fs30\sb60\sa60
2.2.7. Other Differences
\par\pard\plain\sb120
For historical reasons, NASM uses the keyword {\f1 TWORD} where MASM and 
compatible assemblers use {\f1 TBYTE}.
\par\sb120
NASM does not declare uninitialised storage in the same way as MASM: where 
a MASM programmer might use {\f1 stack\'A0db\'A064\'A0dup\'A0(?)}, NASM 
requires {\f1 stack\'A0resb\'A064}, intended to be read as `reserve 64 
bytes'. For a limited amount of compatibility, since NASM treats {\f1 ?} as 
a valid character in symbol names, you can code {\f1 ?\'A0equ\'A00} and 
then writing {\f1 dw\'A0?} will at least do something vaguely useful. 
{\f1 DUP} is still not a supported syntax, however.
\par\sb120
In addition to all of this, macros and directives work completely 
differently to MASM. See {\uldb chapter 4}{\v chapter_4} and {\uldb chapter 
5}{\v chapter_5} for further details.
\par\sb120
\page
#{\footnote chapter_3}
${\footnote Chapter 3: The NASM Language}
+{\footnote browse:00041}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
Chapter 3: The NASM Language
\par\pard\plain\sb120
\li360\fi-360
{\uldb Section 3.1: Layout of a NASM Source Line}{\v section_3_1}\par\sb0
{\uldb Section 3.2: Pseudo\'ADInstructions}{\v section_3_2}\par\sb0
{\uldb Section 3.3: Effective Addresses}{\v section_3_3}\par\sb0
{\uldb Section 3.4: Constants}{\v section_3_4}\par\sb0
{\uldb Section 3.5: Expressions}{\v section_3_5}\par\sb0
{\uldb Section 3.6: SEG and WRT}{\v section_3_6}\par\sb0
{\uldb Section 3.7: STRICT: Inhibiting Optimization}{\v section_3_7}\par\sb0
{\uldb Section 3.8: Critical Expressions}{\v section_3_8}\par\sb0
{\uldb Section 3.9: Local Labels}{\v section_3_9}\par\sb0
\pard\sb120
\page
#{\footnote section_3_1}
${\footnote 3.1. Layout of a NASM Source Line}
+{\footnote browse:00042}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote $, prefix;
address\'ADsize prefixes;
colon;
DWORD;
effective addresses;
floating\'ADpoint;
memory operand;
operands;
operand\'ADsize prefixes;
orphan\'ADlabels;
QWORD;
segment override;
trailing colon;
TWORD;
valid characters}
\keepn\f2\b\fs30\sb60\sa60
3.1. Layout of a NASM Source Line
\par\pard\plain\sb120
Like most assemblers, each NASM source line contains (unless it is a macro, 
a preprocessor directive or an assembler directive: see {\uldb chapter 
4}{\v chapter_4} and {\uldb chapter 5}{\v chapter_5}) some combination of 
the four fields
\par\sb120
\keep\f1\sb120
label:    instruction operands        ; comment\par\sb0
\pard\f0\sb120
As usual, most of these fields are optional; the presence or absence of any 
combination of a label, an instruction and a comment is allowed. Of course, 
the operand field is either required or forbidden by the presence and 
nature of the instruction field.
\par\sb120
NASM uses backslash (\\) as the line continuation character; if a line ends 
with backslash, the next line is considered to be a part of the 
backslash-ended line.
\par\sb120
NASM places no restrictions on white space within a line: labels may have 
white space before them, or instructions may have no space before them, or 
anything. The colon after a label is also optional. (Note that this means 
that if you intend to code {\f1 lodsb} alone on a line, and type 
{\f1 lodab} by accident, then that's still a valid source line which does 
nothing but define a label. Running NASM with the command-line option 
{\f1 \'ADw+orphan\'ADlabels} will cause it to warn you if you define a 
label alone on a line without a trailing colon.)
\par\sb120
Valid characters in labels are letters, numbers, {\f1 _}, {\f1 $}, {\f1 #}, 
{\f1 @}, {\f1 ~}, {\f1 .}, and {\f1 ?}. The only characters which may be 
used as the {\i first} character of an identifier are letters, {\f1 .} 
(with special meaning: see {\uldb section 3.9}{\v section_3_9}), {\f1 _} 
and {\f1 ?}. An identifier may also be prefixed with a {\f1 $} to indicate 
that it is intended to be read as an identifier and not a reserved word; 
thus, if some other module you are linking with defines a symbol called 
{\f1 eax}, you can refer to {\f1 $eax} in NASM code to distinguish the 
symbol from the register.
\par\sb120
The instruction field may contain any machine instruction: Pentium and P6 
instructions, FPU instructions, MMX instructions and even undocumented 
instructions are all supported. The instruction may be prefixed by 
{\f1 LOCK}, {\f1 REP}, {\f1 REPE}/{\f1 REPZ} or {\f1 REPNE}/{\f1 REPNZ}, in 
the usual way. Explicit address-size and operand\'ADsize prefixes 
{\f1 A16}, {\f1 A32}, {\f1 O16} and {\f1 O32} are provided \'96 one example 
of their use is given in {\uldb chapter 9}{\v chapter_9}. You can also use 
the name of a segment register as an instruction prefix: coding 
{\f1 es\'A0mov\'A0[bx],ax} is equivalent to coding {\f1 mov\'A0[es:bx],ax}. 
We recommend the latter syntax, since it is consistent with other syntactic 
features of the language, but for instructions such as {\f1 LODSB}, which 
has no operands and yet can require a segment override, there is no clean 
syntactic way to proceed apart from {\f1 es\'A0lodsb}.
\par\sb120
An instruction is not required to use a prefix: prefixes such as {\f1 CS}, 
{\f1 A32}, {\f1 LOCK} or {\f1 REPE} can appear on a line by themselves, and 
NASM will just generate the prefix bytes.
\par\sb120
In addition to actual machine instructions, NASM also supports a number of 
pseudo-instructions, described in {\uldb section 3.2}{\v section_3_2}.
\par\sb120
Instruction operands may take a number of forms: they can be registers, 
described simply by the register name (e.g. {\f1 ax}, {\f1 bp}, {\f1 ebx}, 
{\f1 cr0}: NASM does not use the {\f1 gas}\'96style syntax in which 
register names must be prefixed by a {\f1 %} sign), or they can be 
effective addresses (see {\uldb section 3.3}{\v section_3_3}), constants 
({\uldb section 3.4}{\v section_3_4}) or expressions ({\uldb section 
3.5}{\v section_3_5}).
\par\sb120
For floating\'ADpoint instructions, NASM accepts a wide range of syntaxes: 
you can use two-operand forms like MASM supports, or you can use NASM's 
native single-operand forms in most cases. Details of all forms of each 
supported instruction are given in {\uldb appendix B}{\v appendix_b}. For 
example, you can code:
\par\sb120
\keep\f1\sb120
        fadd    st1             ; this sets st0 := st0 + st1 \par\sb0
        fadd    st0,st1         ; so does this \par\sb0
\par\sb0
        fadd    st1,st0         ; this sets st1 := st1 + st0 \par\sb0
        fadd    to st1          ; so does this\par\sb0
\pard\f0\sb120
Almost any floating-point instruction that references memory must use one 
of the prefixes {\f1 DWORD}, {\f1 QWORD} or {\f1 TWORD} to indicate what 
size of memory operand it refers to.
\par\sb120
\page
#{\footnote section_3_2}
${\footnote 3.2. Pseudo\'ADInstructions}
+{\footnote browse:00043}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote DB;
DD;
DQ;
DT;
DW;
EQU;
INCBIN;
pseudo\'ADinstructions;
RESB;
RESD;
RESQ;
REST;
RESW;
TIMES;
uninitialised}
\keepn\f2\b\fs30\sb60\sa60
3.2. Pseudo\'ADInstructions
\par\pard\plain\sb120
Pseudo-instructions are things which, though not real x86 machine 
instructions, are used in the instruction field anyway because that's the 
most convenient place to put them. The current pseudo-instructions are 
{\f1 DB}, {\f1 DW}, {\f1 DD}, {\f1 DQ} and {\f1 DT}, their uninitialised 
counterparts {\f1 RESB}, {\f1 RESW}, {\f1 RESD}, {\f1 RESQ} and {\f1 REST}, 
the {\f1 INCBIN} command, the {\f1 EQU} command, and the {\f1 TIMES} 
prefix.
\par\sb120
\li360\fi-360
{\uldb Section 3.2.1: DB and friends: Declaring Initialised Data}{\v section_3_2_1}\par\sb0
{\uldb Section 3.2.2: RESB and friends: Declaring Uninitialised Data}{\v section_3_2_2}\par\sb0
{\uldb Section 3.2.3: INCBIN: Including External Binary Files}{\v section_3_2_3}\par\sb0
{\uldb Section 3.2.4: EQU: Defining Constants}{\v section_3_2_4}\par\sb0
{\uldb Section 3.2.5: TIMES: Repeating Instructions or Data}{\v section_3_2_5}\par\sb0
\pard\sb120
\page
#{\footnote section_3_2_1}
${\footnote 3.2.1. DB and friends: Declaring Initialised Data}
+{\footnote browse:00044}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_2')");
EnableButton("btn_up")}
K{\footnote character constant;
DB;
DD;
DQ;
DT;
DW;
floating\'ADpoint;
numeric constants;
string constant}
\keepn\f2\b\fs30\sb60\sa60
3.2.1. {\f1 DB} and friends: Declaring Initialised Data
\par\pard\plain\sb120
{\f1 DB}, {\f1 DW}, {\f1 DD}, {\f1 DQ} and {\f1 DT} are used, much as in 
MASM, to declare initialised data in the output file. They can be invoked 
in a wide range of ways:
\par\sb120
\keep\f1\sb120
      db    0x55                ; just the byte 0x55 \par\sb0
      db    0x55,0x56,0x57      ; three bytes in succession \par\sb0
      db    'a',0x55            ; character constants are OK \par\sb0
      db    'hello',13,10,'$'   ; so are string constants \par\sb0
      dw    0x1234              ; 0x34 0x12 \par\sb0
      dw    'a'                 ; 0x61 0x00 (it's just a number) \par\sb0
      dw    'ab'                ; 0x61 0x62 (character constant) \par\sb0
      dw    'abc'               ; 0x61 0x62 0x63 0x00 (string) \par\sb0
      dd    0x12345678          ; 0x78 0x56 0x34 0x12 \par\sb0
      dd    1.234567e20         ; floating-point constant \par\sb0
      dq    1.234567e20         ; double-precision float \par\sb0
      dt    1.234567e20         ; extended-precision float\par\sb0
\pard\f0\sb120
{\f1 DQ} and {\f1 DT} do not accept numeric constants or string constants 
as operands.
\par\sb120
\page
#{\footnote section_3_2_2}
${\footnote 3.2.2. RESB and friends: Declaring Uninitialised Data}
+{\footnote browse:00045}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_2')");
EnableButton("btn_up")}
K{\footnote ? MASM syntax;
critical expression;
RESB;
RESD;
RESQ;
REST;
RESW;
uninitialised}
\keepn\f2\b\fs30\sb60\sa60
3.2.2. {\f1 RESB} and friends: Declaring Uninitialised Data
\par\pard\plain\sb120
{\f1 RESB}, {\f1 RESW}, {\f1 RESD}, {\f1 RESQ} and {\f1 REST} are designed 
to be used in the BSS section of a module: they declare {\i uninitialised} 
storage space. Each takes a single operand, which is the number of bytes, 
words, doublewords or whatever to reserve. As stated in {\uldb section 
2.2.7}{\v section_2_2_7}, NASM does not support the MASM/TASM syntax of 
reserving uninitialised space by writing {\f1 DW\'A0?} or similar things: 
this is what it does instead. The operand to a {\f1 RESB}\'96type 
pseudo-instruction is a {\i critical expression}: see {\uldb section 
3.8}{\v section_3_8}.
\par\sb120
For example:
\par\sb120
\keep\f1\sb120
buffer:         resb    64              ; reserve 64 bytes \par\sb0
wordvar:        resw    1               ; reserve a word \par\sb0
realarray       resq    10              ; array of ten reals\par\sb0
\pard\f0\sb120
\page
#{\footnote section_3_2_3}
${\footnote 3.2.3. INCBIN: Including External Binary Files}
+{\footnote browse:00046}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_2')");
EnableButton("btn_up")}
K{\footnote binary files;
DevPac;
graphics;
INCBIN;
sound}
\keepn\f2\b\fs30\sb60\sa60
3.2.3. {\f1 INCBIN}: Including External Binary Files
\par\pard\plain\sb120
{\f1 INCBIN} is borrowed from the old Amiga assembler DevPac: it includes a 
binary file verbatim into the output file. This can be handy for (for 
example) including graphics and sound data directly into a game executable 
file. It can be called in one of these three ways:
\par\sb120
\keep\f1\sb120
    incbin  "file.dat"             ; include the whole file \par\sb0
    incbin  "file.dat",1024        ; skip the first 1024 bytes \par\sb0
    incbin  "file.dat",1024,512    ; skip the first 1024, and \par\sb0
                                   ; actually include at most 512\par\sb0
\pard\f0\sb120
\page
#{\footnote section_3_2_4}
${\footnote 3.2.4. EQU: Defining Constants}
+{\footnote browse:00047}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_2')");
EnableButton("btn_up")}
K{\footnote critical expression;
EQU;
preprocessor}
\keepn\f2\b\fs30\sb60\sa60
3.2.4. {\f1 EQU}: Defining Constants
\par\pard\plain\sb120
{\f1 EQU} defines a symbol to a given constant value: when {\f1 EQU} is 
used, the source line must contain a label. The action of {\f1 EQU} is to 
define the given label name to the value of its (only) operand. This 
definition is absolute, and cannot change later. So, for example,
\par\sb120
\keep\f1\sb120
message         db      'hello, world' \par\sb0
msglen          equ     $-message\par\sb0
\pard\f0\sb120
defines {\f1 msglen} to be the constant 12. {\f1 msglen} may not then be 
redefined later. This is not a preprocessor definition either: the value of 
{\f1 msglen} is evaluated {\i once}, using the value of {\f1 $} (see 
{\uldb section 3.5}{\v section_3_5} for an explanation of {\f1 $}) at the 
point of definition, rather than being evaluated wherever it is referenced 
and using the value of {\f1 $} at the point of reference. Note that the 
operand to an {\f1 EQU} is also a critical expression ({\uldb section 
3.8}{\v section_3_8}).
\par\sb120
\page
#{\footnote section_3_2_5}
${\footnote 3.2.5. TIMES: Repeating Instructions or Data}
+{\footnote browse:00048}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_2')");
EnableButton("btn_up")}
K{\footnote DUP;
macros;
MASM;
%rep;
repeating;
TIMES;
unrolled loops}
\keepn\f2\b\fs30\sb60\sa60
3.2.5. {\f1 TIMES}: Repeating Instructions or Data
\par\pard\plain\sb120
The {\f1 TIMES} prefix causes the instruction to be assembled multiple 
times. This is partly present as NASM's equivalent of the {\f1 DUP} syntax 
supported by MASM\'96compatible assemblers, in that you can code
\par\sb120
\keep\f1\sb120
zerobuf:        times 64 db 0\par\sb0
\pard\f0\sb120
or similar things; but {\f1 TIMES} is more versatile than that. The 
argument to {\f1 TIMES} is not just a numeric constant, but a numeric 
{\i expression}, so you can do things like
\par\sb120
\keep\f1\sb120
buffer: db      'hello, world' \par\sb0
        times 64-$+buffer db ' '\par\sb0
\pard\f0\sb120
which will store exactly enough spaces to make the total length of 
{\f1 buffer} up to 64. Finally, {\f1 TIMES} can be applied to ordinary 
instructions, so you can code trivial unrolled loops in it:
\par\sb120
\keep\f1\sb120
        times 100 movsb\par\sb0
\pard\f0\sb120
Note that there is no effective difference between 
{\f1 times\'A0100\'A0resb\'A01} and {\f1 resb\'A0100}, except that the 
latter will be assembled about 100 times faster due to the internal 
structure of the assembler.
\par\sb120
The operand to {\f1 TIMES}, like that of {\f1 EQU} and those of {\f1 RESB} 
and friends, is a critical expression ({\uldb section 
3.8}{\v section_3_8}).
\par\sb120
Note also that {\f1 TIMES} can't be applied to macros: the reason for this 
is that {\f1 TIMES} is processed after the macro phase, which allows the 
argument to {\f1 TIMES} to contain expressions such as {\f1 64\'AD$+buffer} 
as above. To repeat more than one line of code, or a complex macro, use the 
preprocessor {\f1 %rep} directive.
\par\sb120
\page
#{\footnote section_3_3}
${\footnote 3.3. Effective Addresses}
+{\footnote browse:00049}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote algebra;
effective addresses;
memory references;
square brackets}
\keepn\f2\b\fs30\sb60\sa60
3.3. Effective Addresses
\par\pard\plain\sb120
An effective address is any operand to an instruction which references 
memory. Effective addresses, in NASM, have a very simple syntax: they 
consist of an expression evaluating to the desired address, enclosed in 
square brackets. For example:
\par\sb120
\keep\f1\sb120
wordvar dw      123 \par\sb0
        mov     ax,[wordvar] \par\sb0
        mov     ax,[wordvar+1] \par\sb0
        mov     ax,[es:wordvar+bx]\par\sb0
\pard\f0\sb120
Anything not conforming to this simple system is not a valid memory 
reference in NASM, for example {\f1 es:wordvar[bx]}.
\par\sb120
More complicated effective addresses, such as those involving more than one 
register, work in exactly the same way:
\par\sb120
\keep\f1\sb120
        mov     eax,[ebx*2+ecx+offset] \par\sb0
        mov     ax,[bp+di+8]\par\sb0
\pard\f0\sb120
NASM is capable of doing algebra on these effective addresses, so that 
things which don't necessarily {\i look} legal are perfectly all right:
\par\sb120
\keep\f1\sb120
    mov     eax,[ebx*5]             ; assembles as [ebx*4+ebx] \par\sb0
    mov     eax,[label1*2-label2]   ; ie [label1+(label1-label2)]\par\sb0
\pard\f0\sb120
Some forms of effective address have more than one assembled form; in most 
such cases NASM will generate the smallest form it can. For example, there 
are distinct assembled forms for the 32-bit effective addresses 
{\f1 [eax*2+0]} and {\f1 [eax+eax]}, and NASM will generally generate the 
latter on the grounds that the former requires four bytes to store a zero 
offset.
\par\sb120
NASM has a hinting mechanism which will cause {\f1 [eax+ebx]} and 
{\f1 [ebx+eax]} to generate different opcodes; this is occasionally useful 
because {\f1 [esi+ebp]} and {\f1 [ebp+esi]} have different default segment 
registers.
\par\sb120
However, you can force NASM to generate an effective address in a 
particular form by the use of the keywords {\f1 BYTE}, {\f1 WORD}, 
{\f1 DWORD} and {\f1 NOSPLIT}. If you need {\f1 [eax+3]} to be assembled 
using a double-word offset field instead of the one byte NASM will normally 
generate, you can code {\f1 [dword\'A0eax+3]}. Similarly, you can force 
NASM to use a byte offset for a small value which it hasn't seen on the 
first pass (see {\uldb section 3.8}{\v section_3_8} for an example of such 
a code fragment) by using {\f1 [byte\'A0eax+offset]}. As special cases, 
{\f1 [byte\'A0eax]} will code {\f1 [eax+0]} with a byte offset of zero, and 
{\f1 [dword\'A0eax]} will code it with a double-word offset of zero. The 
normal form, {\f1 [eax]}, will be coded with no offset field.
\par\sb120
The form described in the previous paragraph is also useful if you are 
trying to access data in a 32-bit segment from within 16 bit code. For more 
information on this see the section on mixed-size addressing 
({\uldb section 9.2}{\v section_9_2}). In particular, if you need to access 
data with a known offset that is larger than will fit in a 16-bit value, if 
you don't specify that it is a dword offset, nasm will cause the high word 
of the offset to be lost.
\par\sb120
Similarly, NASM will split {\f1 [eax*2]} into {\f1 [eax+eax]} because that 
allows the offset field to be absent and space to be saved; in fact, it 
will also split {\f1 [eax*2+offset]} into {\f1 [eax+eax+offset]}. You can 
combat this behaviour by the use of the {\f1 NOSPLIT} keyword: 
{\f1 [nosplit\'A0eax*2]} will force {\f1 [eax*2+0]} to be generated 
literally.
\par\sb120
\page
#{\footnote section_3_4}
${\footnote 3.4. Constants}
+{\footnote browse:00050}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote constants}
\keepn\f2\b\fs30\sb60\sa60
3.4. Constants
\par\pard\plain\sb120
NASM understands four different types of constant: numeric, character, 
string and floating-point.
\par\sb120
\li360\fi-360
{\uldb Section 3.4.1: Numeric Constants}{\v section_3_4_1}\par\sb0
{\uldb Section 3.4.2: Character Constants}{\v section_3_4_2}\par\sb0
{\uldb Section 3.4.3: String Constants}{\v section_3_4_3}\par\sb0
{\uldb Section 3.4.4: Floating-Point Constants}{\v section_3_4_4}\par\sb0
\pard\sb120
\page
#{\footnote section_3_4_1}
${\footnote 3.4.1. Numeric Constants}
+{\footnote browse:00051}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_4')");
EnableButton("btn_up")}
K{\footnote $, prefix;
binary;
hex;
numeric constants;
octal}
\keepn\f2\b\fs30\sb60\sa60
3.4.1. Numeric Constants
\par\pard\plain\sb120
A numeric constant is simply a number. NASM allows you to specify numbers 
in a variety of number bases, in a variety of ways: you can suffix {\f1 H}, 
{\f1 Q} or {\f1 O}, and {\f1 B} for hex, octal and binary, or you can 
prefix {\f1 0x} for hex in the style of C, or you can prefix {\f1 $} for 
hex in the style of Borland Pascal. Note, though, that the {\f1 $} prefix 
does double duty as a prefix on identifiers (see {\uldb section 
3.1}{\v section_3_1}), so a hex number prefixed with a {\f1 $} sign must 
have a digit after the {\f1 $} rather than a letter.
\par\sb120
Some examples:
\par\sb120
\keep\f1\sb120
        mov     ax,100          ; decimal \par\sb0
        mov     ax,0a2h         ; hex \par\sb0
        mov     ax,$0a2         ; hex again: the 0 is required \par\sb0
        mov     ax,0xa2         ; hex yet again \par\sb0
        mov     ax,777q         ; octal \par\sb0
        mov     ax,777o         ; octal again \par\sb0
        mov     ax,10010011b    ; binary\par\sb0
\pard\f0\sb120
\page
#{\footnote section_3_4_2}
${\footnote 3.4.2. Character Constants}
+{\footnote browse:00052}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_4')");
EnableButton("btn_up")}
K{\footnote character constant;
CPUID;
little\'ADendian}
\keepn\f2\b\fs30\sb60\sa60
3.4.2. Character Constants
\par\pard\plain\sb120
A character constant consists of up to four characters enclosed in either 
single or double quotes. The type of quote makes no difference to NASM, 
except of course that surrounding the constant with single quotes allows 
double quotes to appear within it and vice versa.
\par\sb120
A character constant with more than one character will be arranged with 
little\'ADendian order in mind: if you code
\par\sb120
\keep\f1\sb120
          mov eax,'abcd'\par\sb0
\pard\f0\sb120
then the constant generated is not {\f1 0x61626364}, but {\f1 0x64636261}, 
so that if you were then to store the value into memory, it would read 
{\f1 abcd} rather than {\f1 dcba}. This is also the sense of character 
constants understood by the Pentium's {\f1 CPUID} instruction (see 
{\uldb section B.4.34}{\v section_b_4_34}).
\par\sb120
\page
#{\footnote section_3_4_3}
${\footnote 3.4.3. String Constants}
+{\footnote browse:00053}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_4')");
EnableButton("btn_up")}
K{\footnote DB;
DD;
DQ;
DT;
DW;
INCBIN}
\keepn\f2\b\fs30\sb60\sa60
3.4.3. String Constants
\par\pard\plain\sb120
String constants are only acceptable to some pseudo-instructions, namely 
the {\f1 DB} family and {\f1 INCBIN}.
\par\sb120
A string constant looks like a character constant, only longer. It is 
treated as a concatenation of maximum-size character constants for the 
conditions. So the following are equivalent:
\par\sb120
\keep\f1\sb120
      db    'hello'               ; string constant \par\sb0
      db    'h','e','l','l','o'   ; equivalent character constants\par\sb0
\pard\f0\sb120
And the following are also equivalent:
\par\sb120
\keep\f1\sb120
      dd    'ninechars'           ; doubleword string constant \par\sb0
      dd    'nine','char','s'     ; becomes three doublewords \par\sb0
      db    'ninechars',0,0,0     ; and really looks like this\par\sb0
\pard\f0\sb120
Note that when used as an operand to {\f1 db}, a constant like {\f1 'ab'} 
is treated as a string constant despite being short enough to be a 
character constant, because otherwise {\f1 db\'A0'ab'} would have the same 
effect as {\f1 db\'A0'a'}, which would be silly. Similarly, three-character 
or four-character constants are treated as strings when they are operands 
to {\f1 dw}.
\par\sb120
\page
#{\footnote section_3_4_4}
${\footnote 3.4.4. Floating-Point Constants}
+{\footnote browse:00054}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_4')");
EnableButton("btn_up")}
K{\footnote DD;
DQ;
DT;
floating\'ADpoint;
floating\'ADpoint, constants;
Intel number formats}
\keepn\f2\b\fs30\sb60\sa60
3.4.4. Floating-Point Constants
\par\pard\plain\sb120
Floating\'ADpoint constants are acceptable only as arguments to {\f1 DD}, 
{\f1 DQ} and {\f1 DT}. They are expressed in the traditional form: digits, 
then a period, then optionally more digits, then optionally an {\f1 E} 
followed by an exponent. The period is mandatory, so that NASM can 
distinguish between {\f1 dd\'A01}, which declares an integer constant, and 
{\f1 dd\'A01.0} which declares a floating-point constant.
\par\sb120
Some examples:
\par\sb120
\keep\f1\sb120
      dd    1.2                     ; an easy one \par\sb0
      dq    1.e10                   ; 10,000,000,000 \par\sb0
      dq    1.e+10                  ; synonymous with 1.e10 \par\sb0
      dq    1.e-10                  ; 0.000 000 000 1 \par\sb0
      dt    3.141592653589793238462 ; pi\par\sb0
\pard\f0\sb120
NASM cannot do compile-time arithmetic on floating-point constants. This is 
because NASM is designed to be portable \'96 although it always generates 
code to run on x86 processors, the assembler itself can run on any system 
with an ANSI C compiler. Therefore, the assembler cannot guarantee the 
presence of a floating-point unit capable of handling the Intel number 
formats, and so for NASM to be able to do floating arithmetic it would have 
to include its own complete set of floating-point routines, which would 
significantly increase the size of the assembler for very little benefit.
\par\sb120
\page
#{\footnote section_3_5}
${\footnote 3.5. Expressions}
+{\footnote browse:00055}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote $$ token;
$, Here token;
expressions;
infinite loop;
integer overflow;
operators;
precedence}
\keepn\f2\b\fs30\sb60\sa60
3.5. Expressions
\par\pard\plain\sb120
Expressions in NASM are similar in syntax to those in C.
\par\sb120
NASM does not guarantee the size of the integers used to evaluate 
expressions at compile time: since NASM can compile and run on 64-bit 
systems quite happily, don't assume that expressions are evaluated in 
32-bit registers and so try to make deliberate use of integer overflow. It 
might not always work. The only thing NASM will guarantee is what's 
guaranteed by ANSI C: you always have {\i at least} 32 bits to work in.
\par\sb120
NASM supports two special tokens in expressions, allowing calculations to 
involve the current assembly position: the {\f1 $} and {\f1 $$} tokens. 
{\f1 $} evaluates to the assembly position at the beginning of the line 
containing the expression; so you can code an infinite loop using 
{\f1 JMP\'A0$}. {\f1 $$} evaluates to the beginning of the current section; 
so you can tell how far into the section you are by using {\f1 ($\'AD$$)}.
\par\sb120
The arithmetic operators provided by NASM are listed here, in increasing 
order of precedence.
\par\sb120
\li360\fi-360
{\uldb Section 3.5.1: |: Bitwise OR Operator}{\v section_3_5_1}\par\sb0
{\uldb Section 3.5.2: ^: Bitwise XOR Operator}{\v section_3_5_2}\par\sb0
{\uldb Section 3.5.3: &: Bitwise AND Operator}{\v section_3_5_3}\par\sb0
{\uldb Section 3.5.4: << and >>: Bit Shift Operators}{\v section_3_5_4}\par\sb0
{\uldb Section 3.5.5: + and -: Addition and Subtraction Operators}{\v section_3_5_5}\par\sb0
{\uldb Section 3.5.6: *, /, //, % and %%: Multiplication and Division}{\v section_3_5_6}\par\sb0
{\uldb Section 3.5.7: Unary Operators: +, -, ~ and SEG}{\v section_3_5_7}\par\sb0
\pard\sb120
\page
#{\footnote section_3_5_1}
${\footnote 3.5.1. |: Bitwise OR Operator}
+{\footnote browse:00056}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_5')");
EnableButton("btn_up")}
K{\footnote | operator;
bitwise OR}
\keepn\f2\b\fs30\sb60\sa60
3.5.1. {\f1 |}: Bitwise OR Operator
\par\pard\plain\sb120
The {\f1 |} operator gives a bitwise OR, exactly as performed by the 
{\f1 OR} machine instruction. Bitwise OR is the lowest-priority arithmetic 
operator supported by NASM.
\par\sb120
\page
#{\footnote section_3_5_2}
${\footnote 3.5.2. ^: Bitwise XOR Operator}
+{\footnote browse:00057}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_5')");
EnableButton("btn_up")}
K{\footnote ^ operator;
bitwise XOR}
\keepn\f2\b\fs30\sb60\sa60
3.5.2. {\f1 ^}: Bitwise XOR Operator
\par\pard\plain\sb120
{\f1 ^} provides the bitwise XOR operation.
\par\sb120
\page
#{\footnote section_3_5_3}
${\footnote 3.5.3. &: Bitwise AND Operator}
+{\footnote browse:00058}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_5')");
EnableButton("btn_up")}
K{\footnote & operator;
bitwise AND}
\keepn\f2\b\fs30\sb60\sa60
3.5.3. {\f1 &}: Bitwise AND Operator
\par\pard\plain\sb120
{\f1 &} provides the bitwise AND operation.
\par\sb120
\page
#{\footnote section_3_5_4}
${\footnote 3.5.4. << and >>: Bit Shift Operators}
+{\footnote browse:00059}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_5')");
EnableButton("btn_up")}
K{\footnote << operator;
>> operator;
bit shift}
\keepn\f2\b\fs30\sb60\sa60
3.5.4. {\f1 <<} and {\f1 >>}: Bit Shift Operators
\par\pard\plain\sb120
{\f1 <<} gives a bit-shift to the left, just as it does in C. So {\f1 5<<3} 
evaluates to 5 times 8, or 40. {\f1 >>} gives a bit-shift to the right; in 
NASM, such a shift is {\i always} unsigned, so that the bits shifted in 
from the left-hand end are filled with zero rather than a sign-extension of 
the previous highest bit.
\par\sb120
\page
#{\footnote section_3_5_5}
${\footnote 3.5.5. + and -: Addition and Subtraction Operators}
+{\footnote browse:00060}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_5')");
EnableButton("btn_up")}
K{\footnote + operator, binary;
- operator, binary;
addition;
subtraction}
\keepn\f2\b\fs30\sb60\sa60
3.5.5. {\f1 +} and {\f1 -}: Addition and Subtraction Operators
\par\pard\plain\sb120
The {\f1 +} and {\f1 -} operators do perfectly ordinary addition and 
subtraction.
\par\sb120
\page
#{\footnote section_3_5_6}
${\footnote 3.5.6. *, /, //, % and %%: Multiplication and Division}
+{\footnote browse:00061}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_5')");
EnableButton("btn_up")}
K{\footnote % operator;
%% operator;
* operator;
/ operator;
// operator;
division;
modulo operators;
multiplication;
preprocessor;
signed division;
signed modulo;
unsigned division;
unsigned modulo}
\keepn\f2\b\fs30\sb60\sa60
3.5.6. {\f1 *}, {\f1 /}, {\f1 //}, {\f1 %} and {\f1 %%}: Multiplication and Division
\par\pard\plain\sb120
{\f1 *} is the multiplication operator. {\f1 /} and {\f1 //} are both 
division operators: {\f1 /} is unsigned division and {\f1 //} is signed 
division. Similarly, {\f1 %} and {\f1 %%} provide unsigned and signed 
modulo operators respectively.
\par\sb120
NASM, like ANSI C, provides no guarantees about the sensible operation of 
the signed modulo operator.
\par\sb120
Since the {\f1 %} character is used extensively by the macro preprocessor, 
you should ensure that both the signed and unsigned modulo operators are 
followed by white space wherever they appear.
\par\sb120
\page
#{\footnote section_3_5_7}
${\footnote 3.5.7. Unary Operators: +, -, ~ and SEG}
+{\footnote browse:00062}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_3_5')");
EnableButton("btn_up")}
K{\footnote + operator, unary;
- operator, unary;
~ operator;
one's complement;
SEG;
segment address;
unary operators}
\keepn\f2\b\fs30\sb60\sa60
3.5.7. Unary Operators: {\f1 +}, {\f1 -}, {\f1 ~} and {\f1 SEG}
\par\pard\plain\sb120
The highest-priority operators in NASM's expression grammar are those which 
only apply to one argument. {\f1 -} negates its operand, {\f1 +} does 
nothing (it's provided for symmetry with {\f1 -}), {\f1 ~} computes the 
one's complement of its operand, and {\f1 SEG} provides the segment address 
of its operand (explained in more detail in {\uldb section 
3.6}{\v section_3_6}).
\par\sb120
\page
#{\footnote section_3_6}
${\footnote 3.6. SEG and WRT}
+{\footnote browse:00063}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote CALL\'A0FAR;
far pointer;
groups;
overlapping segments;
preferred;
SEG;
segment address;
segments;
WRT}
\keepn\f2\b\fs30\sb60\sa60
3.6. {\f1 SEG} and {\f1 WRT}
\par\pard\plain\sb120
When writing large 16-bit programs, which must be split into multiple 
segments, it is often necessary to be able to refer to the segment part of 
the address of a symbol. NASM supports the {\f1 SEG} operator to perform 
this function.
\par\sb120
The {\f1 SEG} operator returns the {\i preferred} segment base of a symbol, 
defined as the segment base relative to which the offset of the symbol 
makes sense. So the code
\par\sb120
\keep\f1\sb120
        mov     ax,seg symbol \par\sb0
        mov     es,ax \par\sb0
        mov     bx,symbol\par\sb0
\pard\f0\sb120
will load {\f1 ES:BX} with a valid pointer to the symbol {\f1 symbol}.
\par\sb120
Things can be more complex than this: since 16-bit segments and groups may 
overlap, you might occasionally want to refer to some symbol using a 
different segment base from the preferred one. NASM lets you do this, by 
the use of the {\f1 WRT} (With Reference To) keyword. So you can do things 
like
\par\sb120
\keep\f1\sb120
        mov     ax,weird_seg        ; weird_seg is a segment base \par\sb0
        mov     es,ax \par\sb0
        mov     bx,symbol wrt weird_seg\par\sb0
\pard\f0\sb120
to load {\f1 ES:BX} with a different, but functionally equivalent, pointer 
to the symbol {\f1 symbol}.
\par\sb120
NASM supports far (inter-segment) calls and jumps by means of the syntax 
{\f1 call\'A0segment:offset}, where {\f1 segment} and {\f1 offset} both 
represent immediate values. So to call a far procedure, you could code 
either of
\par\sb120
\keep\f1\sb120
        call    (seg procedure):procedure \par\sb0
        call    weird_seg:(procedure wrt weird_seg)\par\sb0
\pard\f0\sb120
(The parentheses are included for clarity, to show the intended parsing of 
the above instructions. They are not necessary in practice.)
\par\sb120
NASM supports the syntax {\f1 call\'A0far\'A0procedure} as a synonym for 
the first of the above usages. {\f1 JMP} works identically to {\f1 CALL} in 
these examples.
\par\sb120
To declare a far pointer to a data item in a data segment, you must code
\par\sb120
\keep\f1\sb120
        dw      symbol, seg symbol\par\sb0
\pard\f0\sb120
NASM supports no convenient synonym for this, though you can always invent 
one using the macro processor.
\par\sb120
\page
#{\footnote section_3_7}
${\footnote 3.7. STRICT: Inhibiting Optimization}
+{\footnote browse:00064}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote STRICT}
\keepn\f2\b\fs30\sb60\sa60
3.7. {\f1 STRICT}: Inhibiting Optimization
\par\pard\plain\sb120
When assembling with the optimizer set to level 2 or higher (see 
{\uldb section 2.1.16}{\v section_2_1_16}), NASM will use size specifiers 
({\f1 BYTE}, {\f1 WORD}, {\f1 DWORD}, {\f1 QWORD}, or {\f1 TWORD}), but 
will give them the smallest possible size. The keyword {\f1 STRICT} can be 
used to inhibit optimization and force a particular operand to be emitted 
in the specified size. For example, with the optimizer on, and in 
{\f1 BITS\'A016} mode,
\par\sb120
\keep\f1\sb120
        push dword 33\par\sb0
\pard\f0\sb120
is encoded in three bytes {\f1 66\'A06A\'A021}, whereas
\par\sb120
\keep\f1\sb120
        push strict dword 33\par\sb0
\pard\f0\sb120
is encoded in six bytes, with a full dword immediate operand 
{\f1 66\'A068\'A021\'A000\'A000\'A000}.
\par\sb120
With the optimizer off, the same code (six bytes) is generated whether the 
{\f1 STRICT} keyword was used or not.
\par\sb120
\page
#{\footnote section_3_8}
${\footnote 3.8. Critical Expressions}
+{\footnote browse:00065}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote assembly passes;
critical expression;
effective addresses;
EQU;
forward references;
paradox;
passes, assembly;
RESB;
TIMES;
two\'ADpass assembler}
\keepn\f2\b\fs30\sb60\sa60
3.8. Critical Expressions
\par\pard\plain\sb120
A limitation of NASM is that it is a two\'ADpass assembler; unlike TASM and 
others, it will always do exactly two assembly passes. Therefore it is 
unable to cope with source files that are complex enough to require three 
or more passes.
\par\sb120
The first pass is used to determine the size of all the assembled code and 
data, so that the second pass, when generating all the code, knows all the 
symbol addresses the code refers to. So one thing NASM can't handle is code 
whose size depends on the value of a symbol declared after the code in 
question. For example,
\par\sb120
\keep\f1\sb120
        times (label-$) db 0 \par\sb0
label:  db      'Where am I?'\par\sb0
\pard\f0\sb120
The argument to {\f1 TIMES} in this case could equally legally evaluate to 
anything at all; NASM will reject this example because it cannot tell the 
size of the {\f1 TIMES} line when it first sees it. It will just as firmly 
reject the slightly paradoxical code
\par\sb120
\keep\f1\sb120
        times (label-$+1) db 0 \par\sb0
label:  db      'NOW where am I?'\par\sb0
\pard\f0\sb120
in which {\i any} value for the {\f1 TIMES} argument is by definition 
wrong!
\par\sb120
NASM rejects these examples by means of a concept called a {\i critical 
expression}, which is defined to be an expression whose value is required 
to be computable in the first pass, and which must therefore depend only on 
symbols defined before it. The argument to the {\f1 TIMES} prefix is a 
critical expression; for the same reason, the arguments to the {\f1 RESB} 
family of pseudo-instructions are also critical expressions.
\par\sb120
Critical expressions can crop up in other contexts as well: consider the 
following code.
\par\sb120
\keep\f1\sb120
                mov     ax,symbol1 \par\sb0
symbol1         equ     symbol2 \par\sb0
symbol2:\par\sb0
\pard\f0\sb120
On the first pass, NASM cannot determine the value of {\f1 symbol1}, 
because {\f1 symbol1} is defined to be equal to {\f1 symbol2} which NASM 
hasn't seen yet. On the second pass, therefore, when it encounters the line 
{\f1 mov\'A0ax,symbol1}, it is unable to generate the code for it because 
it still doesn't know the value of {\f1 symbol1}. On the next line, it 
would see the {\f1 EQU} again and be able to determine the value of 
{\f1 symbol1}, but by then it would be too late.
\par\sb120
NASM avoids this problem by defining the right-hand side of an {\f1 EQU} 
statement to be a critical expression, so the definition of {\f1 symbol1} 
would be rejected in the first pass.
\par\sb120
There is a related issue involving forward references: consider this code 
fragment.
\par\sb120
\keep\f1\sb120
        mov     eax,[ebx+offset] \par\sb0
offset  equ     10\par\sb0
\pard\f0\sb120
NASM, on pass one, must calculate the size of the instruction 
{\f1 mov\'A0eax,[ebx+offset]} without knowing the value of {\f1 offset}. It 
has no way of knowing that {\f1 offset} is small enough to fit into a 
one-byte offset field and that it could therefore get away with generating 
a shorter form of the effective\'ADaddress encoding; for all it knows, in 
pass one, {\f1 offset} could be a symbol in the code segment, and it might 
need the full four-byte form. So it is forced to compute the size of the 
instruction to accommodate a four-byte address part. In pass two, having 
made this decision, it is now forced to honour it and keep the instruction 
large, so the code generated in this case is not as small as it could have 
been. This problem can be solved by defining {\f1 offset} before using it, 
or by forcing byte size in the effective address by coding 
{\f1 [byte\'A0ebx+offset]}.
\par\sb120
Note that use of the {\f1 \'ADOn} switch (with n>=2) makes some of the 
above no longer true (see {\uldb section 2.1.16}{\v section_2_1_16}).
\par\sb120
\page
#{\footnote section_3_9}
${\footnote 3.9. Local Labels}
+{\footnote browse:00066}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_3')");
EnableButton("btn_up")}
K{\footnote ..@ symbol prefix;
DevPac;
label prefix;
local labels;
period}
\keepn\f2\b\fs30\sb60\sa60
3.9. Local Labels
\par\pard\plain\sb120
NASM gives special treatment to symbols beginning with a period. A label 
beginning with a single period is treated as a {\i local} label, which 
means that it is associated with the previous non-local label. So, for 
example:
\par\sb120
\keep\f1\sb120
label1  ; some code \par\sb0
\par\sb0
.loop \par\sb0
        ; some more code \par\sb0
\par\sb0
        jne     .loop \par\sb0
        ret \par\sb0
\par\sb0
label2  ; some code \par\sb0
\par\sb0
.loop \par\sb0
        ; some more code \par\sb0
\par\sb0
        jne     .loop \par\sb0
        ret\par\sb0
\pard\f0\sb120
In the above code fragment, each {\f1 JNE} instruction jumps to the line 
immediately before it, because the two definitions of {\f1 .loop} are kept 
separate by virtue of each being associated with the previous non-local 
label.
\par\sb120
This form of local label handling is borrowed from the old Amiga assembler 
DevPac; however, NASM goes one step further, in allowing access to local 
labels from other parts of the code. This is achieved by means of 
{\i defining} a local label in terms of the previous non-local label: the 
first definition of {\f1 .loop} above is really defining a symbol called 
{\f1 label1.loop}, and the second defines a symbol called 
{\f1 label2.loop}. So, if you really needed to, you could write
\par\sb120
\keep\f1\sb120
label3  ; some more code \par\sb0
        ; and some more \par\sb0
\par\sb0
        jmp label1.loop\par\sb0
\pard\f0\sb120
Sometimes it is useful \'96 in a macro, for instance \'96 to be able to 
define a label which can be referenced from anywhere but which doesn't 
interfere with the normal local-label mechanism. Such a label can't be 
non-local because it would interfere with subsequent definitions of, and 
references to, local labels; and it can't be local because the macro that 
defined it wouldn't know the label's full name. NASM therefore introduces a 
third type of label, which is probably only useful in macro definitions: if 
a label begins with the special prefix {\f1 ..@}, then it does nothing to 
the local label mechanism. So you could code
\par\sb120
\keep\f1\sb120
label1:                         ; a non-local label \par\sb0
.local:                         ; this is really label1.local \par\sb0
..@@foo:                         ; this is a special symbol \par\sb0
label2:                         ; another non-local label \par\sb0
.local:                         ; this is really label2.local \par\sb0
\par\sb0
        jmp     ..@@foo          ; this will jump three lines up\par\sb0
\pard\f0\sb120
NASM has the capacity to define other special symbols beginning with a 
double period: for example, {\f1 ..start} is used to specify the entry 
point in the {\f1 obj} output format (see {\uldb section 
6.2.6}{\v section_6_2_6}).
\par\sb120
\page
#{\footnote chapter_4}
${\footnote Chapter 4: The NASM Preprocessor}
+{\footnote browse:00067}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
K{\footnote macro processor;
preprocessor}
\keepn\f2\b\fs30\sb60\sa60
Chapter 4: The NASM Preprocessor
\par\pard\plain\sb120
NASM contains a powerful macro processor, which supports conditional 
assembly, multi-level file inclusion, two forms of macro (single-line and 
multi-line), and a `context stack' mechanism for extra macro power. 
Preprocessor directives all begin with a {\f1 %} sign.
\par\sb120
The preprocessor collapses all lines which end with a backslash (\\) 
character into a single line. Thus:
\par\sb120
\keep\f1\sb120
%define THIS_VERY_LONG_MACRO_NAME_IS_DEFINED_TO \\ \par\sb0
        THIS_VALUE\par\sb0
\pard\f0\sb120
will work like a single-line macro without the backslash-newline sequence.
\par\sb120
\li360\fi-360
{\uldb Section 4.1: Single\'ADLine Macros}{\v section_4_1}\par\sb0
{\uldb Section 4.2: String Handling in Macros: %strlen and %substr}{\v section_4_2}\par\sb0
{\uldb Section 4.3: Multi\'ADLine Macros: %macro}{\v section_4_3}\par\sb0
{\uldb Section 4.4: Conditional Assembly}{\v section_4_4}\par\sb0
{\uldb Section 4.5: Preprocessor Loops: %rep}{\v section_4_5}\par\sb0
{\uldb Section 4.6: Including Other Files}{\v section_4_6}\par\sb0
{\uldb Section 4.7: The Context Stack}{\v section_4_7}\par\sb0
{\uldb Section 4.8: Standard Macros}{\v section_4_8}\par\sb0
{\uldb Section 4.9: TASM Compatible Preprocessor Directives}{\v section_4_9}\par\sb0
{\uldb Section 4.10: Other Preprocessor Directives}{\v section_4_10}\par\sb0
\pard\sb120
\page
#{\footnote section_4_1}
${\footnote 4.1. Single\'ADLine Macros}
+{\footnote browse:00068}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote single\'ADline macros}
\keepn\f2\b\fs30\sb60\sa60
4.1. Single\'ADLine Macros
\par\pard\plain\sb120
\li360\fi-360
{\uldb Section 4.1.1: The Normal Way: %define}{\v section_4_1_1}\par\sb0
{\uldb Section 4.1.2: Enhancing %define: %xdefine}{\v section_4_1_2}\par\sb0
{\uldb Section 4.1.3: Concatenating Single Line Macro Tokens: %+}{\v section_4_1_3}\par\sb0
{\uldb Section 4.1.4: Undefining macros: %undef}{\v section_4_1_4}\par\sb0
{\uldb Section 4.1.5: Preprocessor Variables: %assign}{\v section_4_1_5}\par\sb0
\pard\sb120
\page
#{\footnote section_4_1_1}
${\footnote 4.1.1. The Normal Way: %define}
+{\footnote browse:00069}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_1')");
EnableButton("btn_up")}
K{\footnote case sensitivity;
circular references;
%define;
%idefine;
overloading, single\'ADline macros;
pre\'ADdefining macros}
\keepn\f2\b\fs30\sb60\sa60
4.1.1. The Normal Way: {\f1 %define}
\par\pard\plain\sb120
Single-line macros are defined using the {\f1 %define} preprocessor 
directive. The definitions work in a similar way to C; so you can do things 
like
\par\sb120
\keep\f1\sb120
%define ctrl    0x1F & \par\sb0
%define param(a,b) ((a)+(a)*(b)) \par\sb0
\par\sb0
        mov     byte [param(2,ebx)], ctrl 'D'\par\sb0
\pard\f0\sb120
which will expand to
\par\sb120
\keep\f1\sb120
        mov     byte [(2)+(2)*(ebx)], 0x1F & 'D'\par\sb0
\pard\f0\sb120
When the expansion of a single-line macro contains tokens which invoke 
another macro, the expansion is performed at invocation time, not at 
definition time. Thus the code
\par\sb120
\keep\f1\sb120
%define a(x)    1+b(x) \par\sb0
%define b(x)    2*x \par\sb0
\par\sb0
        mov     ax,a(8)\par\sb0
\pard\f0\sb120
will evaluate in the expected way to {\f1 mov\'A0ax,1+2*8}, even though the 
macro {\f1 b} wasn't defined at the time of definition of {\f1 a}.
\par\sb120
Macros defined with {\f1 %define} are case sensitive: after 
{\f1 %define\'A0foo\'A0bar}, only {\f1 foo} will expand to {\f1 bar}: 
{\f1 Foo} or {\f1 FOO} will not. By using {\f1 %idefine} instead of 
{\f1 %define} (the `i' stands for `insensitive') you can define all the 
case variants of a macro at once, so that {\f1 %idefine\'A0foo\'A0bar} 
would cause {\f1 foo}, {\f1 Foo}, {\f1 FOO}, {\f1 fOO} and so on all to 
expand to {\f1 bar}.
\par\sb120
There is a mechanism which detects when a macro call has occurred as a 
result of a previous expansion of the same macro, to guard against circular 
references and infinite loops. If this happens, the preprocessor will only 
expand the first occurrence of the macro. Hence, if you code
\par\sb120
\keep\f1\sb120
%define a(x)    1+a(x) \par\sb0
\par\sb0
        mov     ax,a(3)\par\sb0
\pard\f0\sb120
the macro {\f1 a(3)} will expand once, becoming {\f1 1+a(3)}, and will then 
expand no further. This behaviour can be useful: see {\uldb section 
8.1}{\v section_8_1} for an example of its use.
\par\sb120
You can overload single-line macros: if you write
\par\sb120
\keep\f1\sb120
%define foo(x)   1+x \par\sb0
%define foo(x,y) 1+x*y\par\sb0
\pard\f0\sb120
the preprocessor will be able to handle both types of macro call, by 
counting the parameters you pass; so {\f1 foo(3)} will become {\f1 1+3} 
whereas {\f1 foo(ebx,2)} will become {\f1 1+ebx*2}. However, if you define
\par\sb120
\keep\f1\sb120
%define foo bar\par\sb0
\pard\f0\sb120
then no other definition of {\f1 foo} will be accepted: a macro with no 
parameters prohibits the definition of the same name as a macro {\i with} 
parameters, and vice versa.
\par\sb120
This doesn't prevent single-line macros being {\i redefined}: you can 
perfectly well define a macro with
\par\sb120
\keep\f1\sb120
%define foo bar\par\sb0
\pard\f0\sb120
and then re-define it later in the same source file with
\par\sb120
\keep\f1\sb120
%define foo baz\par\sb0
\pard\f0\sb120
Then everywhere the macro {\f1 foo} is invoked, it will be expanded 
according to the most recent definition. This is particularly useful when 
defining single-line macros with {\f1 %assign} (see {\uldb section 
4.1.5}{\v section_4_1_5}).
\par\sb120
You can pre\'ADdefine single-line macros using the `-d' option on the NASM 
command line: see {\uldb section 2.1.12}{\v section_2_1_12}.
\par\sb120
\page
#{\footnote section_4_1_2}
${\footnote 4.1.2. Enhancing %define: %xdefine}
+{\footnote browse:00070}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_1')");
EnableButton("btn_up")}
K{\footnote case sensitivity;
%xdefine;
%xidefine}
\keepn\f2\b\fs30\sb60\sa60
4.1.2. Enhancing %define: {\f1 %xdefine}
\par\pard\plain\sb120
To have a reference to an embedded single-line macro resolved at the time 
that it is embedded, as opposed to when the calling macro is expanded, you 
need a different mechanism to the one offered by {\f1 %define}. The 
solution is to use {\f1 %xdefine}, or it's case-insensitive counterpart 
{\f1 %xidefine}.
\par\sb120
Suppose you have the following code:
\par\sb120
\keep\f1\sb120
%define  isTrue  1 \par\sb0
%define  isFalse isTrue \par\sb0
%define  isTrue  0 \par\sb0
\par\sb0
val1:    db      isFalse \par\sb0
\par\sb0
%define  isTrue  1 \par\sb0
\par\sb0
val2:    db      isFalse\par\sb0
\pard\f0\sb120
In this case, {\f1 val1} is equal to 0, and {\f1 val2} is equal to 1. This 
is because, when a single-line macro is defined using {\f1 %define}, it is 
expanded only when it is called. As {\f1 isFalse} expands to {\f1 isTrue}, 
the expansion will be the current value of {\f1 isTrue}. The first time it 
is called that is 0, and the second time it is 1.
\par\sb120
If you wanted {\f1 isFalse} to expand to the value assigned to the embedded 
macro {\f1 isTrue} at the time that {\f1 isFalse} was defined, you need to 
change the above code to use {\f1 %xdefine}.
\par\sb120
\keep\f1\sb120
%xdefine isTrue  1 \par\sb0
%xdefine isFalse isTrue \par\sb0
%xdefine isTrue  0 \par\sb0
\par\sb0
val1:    db      isFalse \par\sb0
\par\sb0
%xdefine isTrue  1 \par\sb0
\par\sb0
val2:    db      isFalse\par\sb0
\pard\f0\sb120
Now, each time that {\f1 isFalse} is called, it expands to 1, as that is 
what the embedded macro {\f1 isTrue} expanded to at the time that 
{\f1 isFalse} was defined.
\par\sb120
\page
#{\footnote section_4_1_3}
${\footnote 4.1.3. Concatenating Single Line Macro Tokens: %+}
+{\footnote browse:00071}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_1')");
EnableButton("btn_up")}
K{\footnote %+}
\keepn\f2\b\fs30\sb60\sa60
4.1.3. Concatenating Single Line Macro Tokens: {\f1 %+}
\par\pard\plain\sb120
Individual tokens in single line macros can be concatenated, to produce 
longer tokens for later processing. This can be useful if there are several 
similar macros that perform similar functions.
\par\sb120
As an example, consider the following:
\par\sb120
\keep\f1\sb120
%define BDASTART 400h                ; Start of BIOS data area\par\sb0
\pard\f0\sb120
\keep\f1\sb120
struc   tBIOSDA                      ; its structure \par\sb0
        .COM1addr       RESW    1 \par\sb0
        .COM2addr       RESW    1 \par\sb0
        ; ..and so on \par\sb0
endstruc\par\sb0
\pard\f0\sb120
Now, if we need to access the elements of tBIOSDA in different places, we 
can end up with:
\par\sb120
\keep\f1\sb120
        mov     ax,BDASTART + tBIOSDA.COM1addr \par\sb0
        mov     bx,BDASTART + tBIOSDA.COM2addr\par\sb0
\pard\f0\sb120
This will become pretty ugly (and tedious) if used in many places, and can 
be reduced in size significantly by using the following macro:
\par\sb120
\keep\f1\sb120
; Macro to access BIOS variables by their names (from tBDA):\par\sb0
\pard\f0\sb120
\keep\f1\sb120
%define BDA(x)  BDASTART + tBIOSDA. %+ x\par\sb0
\pard\f0\sb120
Now the above code can be written as:
\par\sb120
\keep\f1\sb120
        mov     ax,BDA(COM1addr) \par\sb0
        mov     bx,BDA(COM2addr)\par\sb0
\pard\f0\sb120
Using this feature, we can simplify references to a lot of macros (and, in 
turn, reduce typing errors).
\par\sb120
\page
#{\footnote section_4_1_4}
${\footnote 4.1.4. Undefining macros: %undef}
+{\footnote browse:00072}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_1')");
EnableButton("btn_up")}
K{\footnote %undef}
\keepn\f2\b\fs30\sb60\sa60
4.1.4. Undefining macros: {\f1 %undef}
\par\pard\plain\sb120
Single-line macros can be removed with the {\f1 %undef} command. For 
example, the following sequence:
\par\sb120
\keep\f1\sb120
%define foo bar \par\sb0
%undef  foo \par\sb0
\par\sb0
        mov     eax, foo\par\sb0
\pard\f0\sb120
will expand to the instruction {\f1 mov\'A0eax,\'A0foo}, since after 
{\f1 %undef} the macro {\f1 foo} is no longer defined.
\par\sb120
Macros that would otherwise be pre-defined can be undefined on the 
command-line using the `-u' option on the NASM command line: see 
{\uldb section 2.1.13}{\v section_2_1_13}.
\par\sb120
\page
#{\footnote section_4_1_5}
${\footnote 4.1.5. Preprocessor Variables: %assign}
+{\footnote browse:00073}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_1')");
EnableButton("btn_up")}
K{\footnote %assign;
case sensitivity;
critical expression;
%iassign;
preprocessor variables}
\keepn\f2\b\fs30\sb60\sa60
4.1.5. Preprocessor Variables: {\f1 %assign}
\par\pard\plain\sb120
An alternative way to define single-line macros is by means of the 
{\f1 %assign} command (and its case-insensitive counterpart {\f1 %iassign}, 
which differs from {\f1 %assign} in exactly the same way that 
{\f1 %idefine} differs from {\f1 %define}).
\par\sb120
{\f1 %assign} is used to define single-line macros which take no parameters 
and have a numeric value. This value can be specified in the form of an 
expression, and it will be evaluated once, when the {\f1 %assign} directive 
is processed.
\par\sb120
Like {\f1 %define}, macros defined using {\f1 %assign} can be re-defined 
later, so you can do things like
\par\sb120
\keep\f1\sb120
%assign i i+1\par\sb0
\pard\f0\sb120
to increment the numeric value of a macro.
\par\sb120
{\f1 %assign} is useful for controlling the termination of {\f1 %rep} 
preprocessor loops: see {\uldb section 4.5}{\v section_4_5} for an example 
of this. Another use for {\f1 %assign} is given in {\uldb section 
7.4}{\v section_7_4} and {\uldb section 8.1}{\v section_8_1}.
\par\sb120
The expression passed to {\f1 %assign} is a critical expression (see 
{\uldb section 3.8}{\v section_3_8}), and must also evaluate to a pure 
number (rather than a relocatable reference such as a code or data address, 
or anything involving a register).
\par\sb120
\page
#{\footnote section_4_2}
${\footnote 4.2. String Handling in Macros: %strlen and %substr}
+{\footnote browse:00074}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote string handling in macros;
%strlen;
%substr}
\keepn\f2\b\fs30\sb60\sa60
4.2. String Handling in Macros: {\f1 %strlen} and {\f1 %substr}
\par\pard\plain\sb120
It's often useful to be able to handle strings in macros. NASM supports two 
simple string handling macro operators from which more complex operations 
can be constructed.
\par\sb120
\li360\fi-360
{\uldb Section 4.2.1: String Length: %strlen}{\v section_4_2_1}\par\sb0
{\uldb Section 4.2.2: Sub\'ADstrings: %substr}{\v section_4_2_2}\par\sb0
\pard\sb120
\page
#{\footnote section_4_2_1}
${\footnote 4.2.1. String Length: %strlen}
+{\footnote browse:00075}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_2')");
EnableButton("btn_up")}
K{\footnote string length;
%strlen}
\keepn\f2\b\fs30\sb60\sa60
4.2.1. String Length: {\f1 %strlen}
\par\pard\plain\sb120
The {\f1 %strlen} macro is like {\f1 %assign} macro in that it creates (or 
redefines) a numeric value to a macro. The difference is that with 
{\f1 %strlen}, the numeric value is the length of a string. An example of 
the use of this would be:
\par\sb120
\keep\f1\sb120
%strlen charcnt 'my string'\par\sb0
\pard\f0\sb120
In this example, {\f1 charcnt} would receive the value 8, just as if an 
{\f1 %assign} had been used. In this example, {\f1 'my\'A0string'} was a 
literal string but it could also have been a single-line macro that expands 
to a string, as in the following example:
\par\sb120
\keep\f1\sb120
%define sometext 'my string' \par\sb0
%strlen charcnt sometext\par\sb0
\pard\f0\sb120
As in the first case, this would result in {\f1 charcnt} being assigned the 
value of 8.
\par\sb120
\page
#{\footnote section_4_2_2}
${\footnote 4.2.2. Sub\'ADstrings: %substr}
+{\footnote browse:00076}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_2')");
EnableButton("btn_up")}
K{\footnote %substr;
sub\'ADstrings}
\keepn\f2\b\fs30\sb60\sa60
4.2.2. Sub\'ADstrings: {\f1 %substr}
\par\pard\plain\sb120
Individual letters in strings can be extracted using {\f1 %substr}. An 
example of its use is probably more useful than the description:
\par\sb120
\keep\f1\sb120
%substr mychar  'xyz' 1         ; equivalent to %define mychar 'x' \par\sb0
%substr mychar  'xyz' 2         ; equivalent to %define mychar 'y' \par\sb0
%substr mychar  'xyz' 3         ; equivalent to %define mychar 'z'\par\sb0
\pard\f0\sb120
In this example, mychar gets the value of 'y'. As with {\f1 %strlen} (see 
{\uldb section 4.2.1}{\v section_4_2_1}), the first parameter is the 
single-line macro to be created and the second is the string. The third 
parameter specifies which character is to be selected. Note that the first 
index is 1, not 0 and the last index is equal to the value that 
{\f1 %strlen} would assign given the same string. Index values out of range 
result in an empty string.
\par\sb120
\page
#{\footnote section_4_3}
${\footnote 4.3. Multi\'ADLine Macros: %macro}
+{\footnote browse:00077}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote braces, around macro parameters;
case sensitivity;
%imacro;
%macro;
multi\'ADline macros}
\keepn\f2\b\fs30\sb60\sa60
4.3. Multi\'ADLine Macros: {\f1 %macro}
\par\pard\plain\sb120
Multi-line macros are much more like the type of macro seen in MASM and 
TASM: a multi-line macro definition in NASM looks something like this.
\par\sb120
\keep\f1\sb120
%macro  prologue 1 \par\sb0
\par\sb0
        push    ebp \par\sb0
        mov     ebp,esp \par\sb0
        sub     esp,%1 \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
This defines a C-like function prologue as a macro: so you would invoke the 
macro with a call such as
\par\sb120
\keep\f1\sb120
myfunc:   prologue 12\par\sb0
\pard\f0\sb120
which would expand to the three lines of code
\par\sb120
\keep\f1\sb120
myfunc: push    ebp \par\sb0
        mov     ebp,esp \par\sb0
        sub     esp,12\par\sb0
\pard\f0\sb120
The number {\f1 1} after the macro name in the {\f1 %macro} line defines 
the number of parameters the macro {\f1 prologue} expects to receive. The 
use of {\f1 %1} inside the macro definition refers to the first parameter 
to the macro call. With a macro taking more than one parameter, subsequent 
parameters would be referred to as {\f1 %2}, {\f1 %3} and so on.
\par\sb120
Multi-line macros, like single-line macros, are case\'ADsensitive, unless 
you define them using the alternative directive {\f1 %imacro}.
\par\sb120
If you need to pass a comma as {\i part} of a parameter to a multi-line 
macro, you can do that by enclosing the entire parameter in braces. So you 
could code things like
\par\sb120
\keep\f1\sb120
%macro  silly 2 \par\sb0
\par\sb0
    %2: db      %1 \par\sb0
\par\sb0
%endmacro \par\sb0
\par\sb0
        silly 'a', letter_a             ; letter_a:  db 'a' \par\sb0
        silly 'ab', string_ab           ; string_ab: db 'ab' \par\sb0
        silly @\{13,10@\}, crlf             ; crlf:      db 13,10\par\sb0
\pard\f0\sb120
\li360\fi-360
{\uldb Section 4.3.1: Overloading Multi-Line Macros}{\v section_4_3_1}\par\sb0
{\uldb Section 4.3.2: Macro\'ADLocal Labels}{\v section_4_3_2}\par\sb0
{\uldb Section 4.3.3: Greedy Macro Parameters}{\v section_4_3_3}\par\sb0
{\uldb Section 4.3.4: Default Macro Parameters}{\v section_4_3_4}\par\sb0
{\uldb Section 4.3.5: %0: Macro Parameter Counter}{\v section_4_3_5}\par\sb0
{\uldb Section 4.3.6: %rotate: Rotating Macro Parameters}{\v section_4_3_6}\par\sb0
{\uldb Section 4.3.7: Concatenating Macro Parameters}{\v section_4_3_7}\par\sb0
{\uldb Section 4.3.8: Condition Codes as Macro Parameters}{\v section_4_3_8}\par\sb0
{\uldb Section 4.3.9: Disabling Listing Expansion}{\v section_4_3_9}\par\sb0
\pard\sb120
\page
#{\footnote section_4_3_1}
${\footnote 4.3.1. Overloading Multi-Line Macros}
+{\footnote browse:00078}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote overloading, multi\'ADline macros}
\keepn\f2\b\fs30\sb60\sa60
4.3.1. Overloading Multi-Line Macros
\par\pard\plain\sb120
As with single-line macros, multi-line macros can be overloaded by defining 
the same macro name several times with different numbers of parameters. 
This time, no exception is made for macros with no parameters at all. So 
you could define
\par\sb120
\keep\f1\sb120
%macro  prologue 0 \par\sb0
\par\sb0
        push    ebp \par\sb0
        mov     ebp,esp \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
to define an alternative form of the function prologue which allocates no 
local stack space.
\par\sb120
Sometimes, however, you might want to `overload' a machine instruction; for 
example, you might want to define
\par\sb120
\keep\f1\sb120
%macro  push 2 \par\sb0
\par\sb0
        push    %1 \par\sb0
        push    %2 \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
so that you could code
\par\sb120
\keep\f1\sb120
        push    ebx             ; this line is not a macro call \par\sb0
        push    eax,ecx         ; but this one is\par\sb0
\pard\f0\sb120
Ordinarily, NASM will give a warning for the first of the above two lines, 
since {\f1 push} is now defined to be a macro, and is being invoked with a 
number of parameters for which no definition has been given. The correct 
code will still be generated, but the assembler will give a warning. This 
warning can be disabled by the use of the {\f1 \'ADw\'ADmacro\'ADparams} 
command-line option (see {\uldb section 2.1.18}{\v section_2_1_18}).
\par\sb120
\page
#{\footnote section_4_3_2}
${\footnote 4.3.2. Macro\'ADLocal Labels}
+{\footnote browse:00079}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote %% operator;
..@ symbol prefix;
macro\'ADlocal labels}
\keepn\f2\b\fs30\sb60\sa60
4.3.2. Macro\'ADLocal Labels
\par\pard\plain\sb120
NASM allows you to define labels within a multi-line macro definition in 
such a way as to make them local to the macro call: so calling the same 
macro multiple times will use a different label each time. You do this by 
prefixing {\f1 %%} to the label name. So you can invent an instruction 
which executes a {\f1 RET} if the {\f1 Z} flag is set by doing this:
\par\sb120
\keep\f1\sb120
%macro  retz 0 \par\sb0
\par\sb0
        jnz     %%skip \par\sb0
        ret \par\sb0
    %%skip: \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
You can call this macro as many times as you want, and every time you call 
it NASM will make up a different `real' name to substitute for the label 
{\f1 %%skip}. The names NASM invents are of the form {\f1 ..@2345.skip}, 
where the number 2345 changes with every macro call. The {\f1 ..@} prefix 
prevents macro-local labels from interfering with the local label 
mechanism, as described in {\uldb section 3.9}{\v section_3_9}. You should 
avoid defining your own labels in this form (the {\f1 ..@} prefix, then a 
number, then another period) in case they interfere with macro-local 
labels.
\par\sb120
\page
#{\footnote section_4_3_3}
${\footnote 4.3.3. Greedy Macro Parameters}
+{\footnote browse:00080}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote + modifier;
commas in macro parameters;
greedy macro parameters}
\keepn\f2\b\fs30\sb60\sa60
4.3.3. Greedy Macro Parameters
\par\pard\plain\sb120
Occasionally it is useful to define a macro which lumps its entire command 
line into one parameter definition, possibly after extracting one or two 
smaller parameters from the front. An example might be a macro to write a 
text string to a file in MS-DOS, where you might want to be able to write
\par\sb120
\keep\f1\sb120
        writefile [filehandle],"hello, world",13,10\par\sb0
\pard\f0\sb120
NASM allows you to define the last parameter of a macro to be {\i greedy}, 
meaning that if you invoke the macro with more parameters than it expects, 
all the spare parameters get lumped into the last defined one along with 
the separating commas. So if you code:
\par\sb120
\keep\f1\sb120
%macro  writefile 2+ \par\sb0
\par\sb0
        jmp     %%endstr \par\sb0
  %%str:        db      %2 \par\sb0
  %%endstr: \par\sb0
        mov     dx,%%str \par\sb0
        mov     cx,%%endstr-%%str \par\sb0
        mov     bx,%1 \par\sb0
        mov     ah,0x40 \par\sb0
        int     0x21 \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
then the example call to {\f1 writefile} above will work as expected: the 
text before the first comma, {\f1 [filehandle]}, is used as the first macro 
parameter and expanded when {\f1 %1} is referred to, and all the subsequent 
text is lumped into {\f1 %2} and placed after the {\f1 db}.
\par\sb120
The greedy nature of the macro is indicated to NASM by the use of the 
{\f1 +} sign after the parameter count on the {\f1 %macro} line.
\par\sb120
If you define a greedy macro, you are effectively telling NASM how it 
should expand the macro given {\i any} number of parameters from the actual 
number specified up to infinity; in this case, for example, NASM now knows 
what to do when it sees a call to {\f1 writefile} with 2, 3, 4 or more 
parameters. NASM will take this into account when overloading macros, and 
will not allow you to define another form of {\f1 writefile} taking 4 
parameters (for example).
\par\sb120
Of course, the above macro could have been implemented as a non-greedy 
macro, in which case the call to it would have had to look like
\par\sb120
\keep\f1\sb120
          writefile [filehandle], @\{"hello, world",13,10@\}\par\sb0
\pard\f0\sb120
NASM provides both mechanisms for putting commas in macro parameters, and 
you choose which one you prefer for each macro definition.
\par\sb120
See {\uldb section 5.2.1}{\v section_5_2_1} for a better way to write the 
above macro.
\par\sb120
\page
#{\footnote section_4_3_4}
${\footnote 4.3.4. Default Macro Parameters}
+{\footnote browse:00081}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote %0 parameter count;
default macro parameters;
omitted parameters}
\keepn\f2\b\fs30\sb60\sa60
4.3.4. Default Macro Parameters
\par\pard\plain\sb120
NASM also allows you to define a multi-line macro with a {\i range} of 
allowable parameter counts. If you do this, you can specify defaults for 
omitted parameters. So, for example:
\par\sb120
\keep\f1\sb120
%macro  die 0-1 "Painful program death has occurred." \par\sb0
\par\sb0
        writefile 2,%1 \par\sb0
        mov     ax,0x4c01 \par\sb0
        int     0x21 \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
This macro (which makes use of the {\f1 writefile} macro defined in 
{\uldb section 4.3.3}{\v section_4_3_3}) can be called with an explicit 
error message, which it will display on the error output stream before 
exiting, or it can be called with no parameters, in which case it will use 
the default error message supplied in the macro definition.
\par\sb120
In general, you supply a minimum and maximum number of parameters for a 
macro of this type; the minimum number of parameters are then required in 
the macro call, and then you provide defaults for the optional ones. So if 
a macro definition began with the line
\par\sb120
\keep\f1\sb120
%macro foobar 1-3 eax,[ebx+2]\par\sb0
\pard\f0\sb120
then it could be called with between one and three parameters, and {\f1 %1} 
would always be taken from the macro call. {\f1 %2}, if not specified by 
the macro call, would default to {\f1 eax}, and {\f1 %3} if not specified 
would default to {\f1 [ebx+2]}.
\par\sb120
You may omit parameter defaults from the macro definition, in which case 
the parameter default is taken to be blank. This can be useful for macros 
which can take a variable number of parameters, since the {\f1 %0} token 
(see {\uldb section 4.3.5}{\v section_4_3_5}) allows you to determine how 
many parameters were really passed to the macro call.
\par\sb120
This defaulting mechanism can be combined with the greedy-parameter 
mechanism; so the {\f1 die} macro above could be made more powerful, and 
more useful, by changing the first line of the definition to
\par\sb120
\keep\f1\sb120
%macro die 0-1+ "Painful program death has occurred.",13,10\par\sb0
\pard\f0\sb120
The maximum parameter count can be infinite, denoted by {\f1 *}. In this 
case, of course, it is impossible to provide a {\i full} set of default 
parameters. Examples of this usage are shown in {\uldb section 
4.3.6}{\v section_4_3_6}.
\par\sb120
\page
#{\footnote section_4_3_5}
${\footnote 4.3.5. %0: Macro Parameter Counter}
+{\footnote browse:00082}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote %0 parameter count;
counting macro parameters}
\keepn\f2\b\fs30\sb60\sa60
4.3.5. {\f1 %0}: Macro Parameter Counter
\par\pard\plain\sb120
For a macro which can take a variable number of parameters, the parameter 
reference {\f1 %0} will return a numeric constant giving the number of 
parameters passed to the macro. This can be used as an argument to 
{\f1 %rep} (see {\uldb section 4.5}{\v section_4_5}) in order to iterate 
through all the parameters of a macro. Examples are given in {\uldb section 
4.3.6}{\v section_4_3_6}.
\par\sb120
\page
#{\footnote section_4_3_6}
${\footnote 4.3.6. %rotate: Rotating Macro Parameters}
+{\footnote browse:00083}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote iterating over macro parameters;
multipush macro;
%rotate;
rotating macro parameters;
shift command}
\keepn\f2\b\fs30\sb60\sa60
4.3.6. {\f1 %rotate}: Rotating Macro Parameters
\par\pard\plain\sb120
Unix shell programmers will be familiar with the {\f1 shift} shell command, 
which allows the arguments passed to a shell script (referenced as 
{\f1 $1}, {\f1 $2} and so on) to be moved left by one place, so that the 
argument previously referenced as {\f1 $2} becomes available as {\f1 $1}, 
and the argument previously referenced as {\f1 $1} is no longer available 
at all.
\par\sb120
NASM provides a similar mechanism, in the form of {\f1 %rotate}. As its 
name suggests, it differs from the Unix {\f1 shift} in that no parameters 
are lost: parameters rotated off the left end of the argument list reappear 
on the right, and vice versa.
\par\sb120
{\f1 %rotate} is invoked with a single numeric argument (which may be an 
expression). The macro parameters are rotated to the left by that many 
places. If the argument to {\f1 %rotate} is negative, the macro parameters 
are rotated to the right.
\par\sb120
So a pair of macros to save and restore a set of registers might work as 
follows:
\par\sb120
\keep\f1\sb120
%macro  multipush 1-* \par\sb0
\par\sb0
  %rep  %0 \par\sb0
        push    %1 \par\sb0
  %rotate 1 \par\sb0
  %endrep \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
This macro invokes the {\f1 PUSH} instruction on each of its arguments in 
turn, from left to right. It begins by pushing its first argument, 
{\f1 %1}, then invokes {\f1 %rotate} to move all the arguments one place to 
the left, so that the original second argument is now available as 
{\f1 %1}. Repeating this procedure as many times as there were arguments 
(achieved by supplying {\f1 %0} as the argument to {\f1 %rep}) causes each 
argument in turn to be pushed.
\par\sb120
Note also the use of {\f1 *} as the maximum parameter count, indicating 
that there is no upper limit on the number of parameters you may supply to 
the {\f1 multipush} macro.
\par\sb120
It would be convenient, when using this macro, to have a {\f1 POP} 
equivalent, which {\i didn't} require the arguments to be given in reverse 
order. Ideally, you would write the {\f1 multipush} macro call, then 
cut-and-paste the line to where the pop needed to be done, and change the 
name of the called macro to {\f1 multipop}, and the macro would take care 
of popping the registers in the opposite order from the one in which they 
were pushed.
\par\sb120
This can be done by the following definition:
\par\sb120
\keep\f1\sb120
%macro  multipop 1-* \par\sb0
\par\sb0
  %rep %0 \par\sb0
  %rotate -1 \par\sb0
        pop     %1 \par\sb0
  %endrep \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
This macro begins by rotating its arguments one place to the {\i right}, so 
that the original {\i last} argument appears as {\f1 %1}. This is then 
popped, and the arguments are rotated right again, so the second-to-last 
argument becomes {\f1 %1}. Thus the arguments are iterated through in 
reverse order.
\par\sb120
\page
#{\footnote section_4_3_7}
${\footnote 4.3.7. Concatenating Macro Parameters}
+{\footnote browse:00084}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote braces, after % sign;
concatenating macro parameters}
\keepn\f2\b\fs30\sb60\sa60
4.3.7. Concatenating Macro Parameters
\par\pard\plain\sb120
NASM can concatenate macro parameters on to other text surrounding them. 
This allows you to declare a family of symbols, for example, in a macro 
definition. If, for example, you wanted to generate a table of key codes 
along with offsets into the table, you could code something like
\par\sb120
\keep\f1\sb120
%macro keytab_entry 2 \par\sb0
\par\sb0
    keypos%1    equ     $-keytab \par\sb0
                db      %2 \par\sb0
\par\sb0
%endmacro \par\sb0
\par\sb0
keytab: \par\sb0
          keytab_entry F1,128+1 \par\sb0
          keytab_entry F2,128+2 \par\sb0
          keytab_entry Return,13\par\sb0
\pard\f0\sb120
which would expand to
\par\sb120
\keep\f1\sb120
keytab: \par\sb0
keyposF1        equ     $-keytab \par\sb0
                db     128+1 \par\sb0
keyposF2        equ     $-keytab \par\sb0
                db      128+2 \par\sb0
keyposReturn    equ     $-keytab \par\sb0
                db      13\par\sb0
\pard\f0\sb120
You can just as easily concatenate text on to the other end of a macro 
parameter, by writing {\f1 %1foo}.
\par\sb120
If you need to append a {\i digit} to a macro parameter, for example 
defining labels {\f1 foo1} and {\f1 foo2} when passed the parameter 
{\f1 foo}, you can't code {\f1 %11} because that would be taken as the 
eleventh macro parameter. Instead, you must code {\f1 %\{1\}1}, which will 
separate the first {\f1 1} (giving the number of the macro parameter) from 
the second (literal text to be concatenated to the parameter).
\par\sb120
This concatenation can also be applied to other preprocessor in-line 
objects, such as macro-local labels ({\uldb section 
4.3.2}{\v section_4_3_2}) and context-local labels ({\uldb section 
4.7.2}{\v section_4_7_2}). In all cases, ambiguities in syntax can be 
resolved by enclosing everything after the {\f1 %} sign and before the 
literal text in braces: so {\f1 %\{%foo\}bar} concatenates the text 
{\f1 bar} to the end of the real name of the macro-local label {\f1 %%foo}. 
(This is unnecessary, since the form NASM uses for the real names of 
macro-local labels means that the two usages {\f1 %\{%foo\}bar} and 
{\f1 %%foobar} would both expand to the same thing anyway; nevertheless, 
the capability is there.)
\par\sb120
\page
#{\footnote section_4_3_8}
${\footnote 4.3.8. Condition Codes as Macro Parameters}
+{\footnote browse:00085}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote %+1 and %\'AD1 syntax;
condition codes as macro parameters;
conditional\'ADreturn macro}
\keepn\f2\b\fs30\sb60\sa60
4.3.8. Condition Codes as Macro Parameters
\par\pard\plain\sb120
NASM can give special treatment to a macro parameter which contains a 
condition code. For a start, you can refer to the macro parameter {\f1 %1} 
by means of the alternative syntax {\f1 %+1}, which informs NASM that this 
macro parameter is supposed to contain a condition code, and will cause the 
preprocessor to report an error message if the macro is called with a 
parameter which is {\i not} a valid condition code.
\par\sb120
Far more usefully, though, you can refer to the macro parameter by means of 
{\f1 %\'AD1}, which NASM will expand as the {\i inverse} condition code. So 
the {\f1 retz} macro defined in {\uldb section 4.3.2}{\v section_4_3_2} can 
be replaced by a general conditional\'ADreturn macro like this:
\par\sb120
\keep\f1\sb120
%macro  retc 1 \par\sb0
\par\sb0
        j%-1    %%skip \par\sb0
        ret \par\sb0
  %%skip: \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
This macro can now be invoked using calls like {\f1 retc\'A0ne}, which will 
cause the conditional-jump instruction in the macro expansion to come out 
as {\f1 JE}, or {\f1 retc\'A0po} which will make the jump a {\f1 JPE}.
\par\sb120
The {\f1 %+1} macro-parameter reference is quite happy to interpret the 
arguments {\f1 CXZ} and {\f1 ECXZ} as valid condition codes; however, 
{\f1 %\'AD1} will report an error if passed either of these, because no 
inverse condition code exists.
\par\sb120
\page
#{\footnote section_4_3_9}
${\footnote 4.3.9. Disabling Listing Expansion}
+{\footnote browse:00086}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_3')");
EnableButton("btn_up")}
K{\footnote disabling listing expansion;
.nolist}
\keepn\f2\b\fs30\sb60\sa60
4.3.9. Disabling Listing Expansion
\par\pard\plain\sb120
When NASM is generating a listing file from your program, it will generally 
expand multi-line macros by means of writing the macro call and then 
listing each line of the expansion. This allows you to see which 
instructions in the macro expansion are generating what code; however, for 
some macros this clutters the listing up unnecessarily.
\par\sb120
NASM therefore provides the {\f1 .nolist} qualifier, which you can include 
in a macro definition to inhibit the expansion of the macro in the listing 
file. The {\f1 .nolist} qualifier comes directly after the number of 
parameters, like this:
\par\sb120
\keep\f1\sb120
%macro foo 1.nolist\par\sb0
\pard\f0\sb120
Or like this:
\par\sb120
\keep\f1\sb120
%macro bar 1-5+.nolist a,b,c,d,e,f,g,h\par\sb0
\pard\f0\sb120
\page
#{\footnote section_4_4}
${\footnote 4.4. Conditional Assembly}
+{\footnote browse:00087}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote conditional assembly;
%elif;
%else;
%if}
\keepn\f2\b\fs30\sb60\sa60
4.4. Conditional Assembly
\par\pard\plain\sb120
Similarly to the C preprocessor, NASM allows sections of a source file to 
be assembled only if certain conditions are met. The general syntax of this 
feature looks like this:
\par\sb120
\keep\f1\sb120
%if<condition> \par\sb0
    ; some code which only appears if <condition> is met \par\sb0
%elif<condition2> \par\sb0
    ; only appears if <condition> is not met but <condition2> is \par\sb0
%else \par\sb0
    ; this appears if neither <condition> nor <condition2> was met \par\sb0
%endif\par\sb0
\pard\f0\sb120
The {\f1 %else} clause is optional, as is the {\f1 %elif} clause. You can 
have more than one {\f1 %elif} clause as well.
\par\sb120
\li360\fi-360
{\uldb Section 4.4.1: %ifdef: Testing Single-Line Macro Existence}{\v section_4_4_1}\par\sb0
{\uldb Section 4.4.2: ifmacro: Testing Multi-Line Macro Existence}{\v section_4_4_2}\par\sb0
{\uldb Section 4.4.3: %ifctx: Testing the Context Stack}{\v section_4_4_3}\par\sb0
{\uldb Section 4.4.4: %if: Testing Arbitrary Numeric Expressions}{\v section_4_4_4}\par\sb0
{\uldb Section 4.4.5: %ifidn and %ifidni: Testing Exact Text Identity}{\v section_4_4_5}\par\sb0
{\uldb Section 4.4.6: %ifid, %ifnum, %ifstr: Testing Token Types}{\v section_4_4_6}\par\sb0
{\uldb Section 4.4.7: %error: Reporting User\'ADDefined Errors}{\v section_4_4_7}\par\sb0
\pard\sb120
\page
#{\footnote section_4_4_1}
${\footnote 4.4.1. %ifdef: Testing Single-Line Macro Existence}
+{\footnote browse:00088}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_4')");
EnableButton("btn_up")}
K{\footnote %elifdef;
%elifndef;
%ifdef;
%ifndef;
testing, single\'ADline macro existence}
\keepn\f2\b\fs30\sb60\sa60
4.4.1. {\f1 %ifdef}: Testing Single-Line Macro Existence
\par\pard\plain\sb120
Beginning a conditional-assembly block with the line {\f1 %ifdef\'A0MACRO} 
will assemble the subsequent code if, and only if, a single-line macro 
called {\f1 MACRO} is defined. If not, then the {\f1 %elif} and {\f1 %else} 
blocks (if any) will be processed instead.
\par\sb120
For example, when debugging a program, you might want to write code such as
\par\sb120
\keep\f1\sb120
          ; perform some function \par\sb0
%ifdef DEBUG \par\sb0
          writefile 2,"Function performed successfully",13,10 \par\sb0
%endif \par\sb0
          ; go and do something else\par\sb0
\pard\f0\sb120
Then you could use the command-line option {\f1 \'ADdDEBUG} to create a 
version of the program which produced debugging messages, and remove the 
option to generate the final release version of the program.
\par\sb120
You can test for a macro {\i not} being defined by using {\f1 %ifndef} 
instead of {\f1 %ifdef}. You can also test for macro definitions in 
{\f1 %elif} blocks by using {\f1 %elifdef} and {\f1 %elifndef}.
\par\sb120
\page
#{\footnote section_4_4_2}
${\footnote 4.4.2. ifmacro: Testing Multi-Line Macro Existence}
+{\footnote browse:00089}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_4')");
EnableButton("btn_up")}
K{\footnote %elifmacro;
%elifnmacro;
ifmacro;
%ifnmacro;
testing, multi\'ADline macro existence}
\keepn\f2\b\fs30\sb60\sa60
4.4.2. {\f1 ifmacro}: Testing Multi-Line Macro Existence
\par\pard\plain\sb120
The {\f1 %ifmacro} directive operates in the same way as the {\f1 %ifdef} 
directive, except that it checks for the existence of a multi-line macro.
\par\sb120
For example, you may be working with a large project and not have control 
over the macros in a library. You may want to create a macro with one name 
if it doesn't already exist, and another name if one with that name does 
exist.
\par\sb120
The {\f1 %ifmacro} is considered true if defining a macro with the given 
name and number of arguments would cause a definitions conflict. For 
example:
\par\sb120
\keep\f1\sb120
%ifmacro MyMacro 1-3 \par\sb0
\par\sb0
     %error "MyMacro 1-3" causes a conflict with an existing macro. \par\sb0
\par\sb0
%else \par\sb0
\par\sb0
     %macro MyMacro 1-3 \par\sb0
\par\sb0
             ; insert code to define the macro \par\sb0
\par\sb0
     %endmacro \par\sb0
\par\sb0
%endif\par\sb0
\pard\f0\sb120
This will create the macro "MyMacro 1-3" if no macro already exists which 
would conflict with it, and emits a warning if there would be a definition 
conflict.
\par\sb120
You can test for the macro not existing by using the {\f1 %ifnmacro} 
instead of {\f1 %ifmacro}. Additional tests can be performed in {\f1 %elif} 
blocks by using {\f1 %elifmacro} and {\f1 %elifnmacro}.
\par\sb120
\page
#{\footnote section_4_4_3}
${\footnote 4.4.3. %ifctx: Testing the Context Stack}
+{\footnote browse:00090}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_4')");
EnableButton("btn_up")}
K{\footnote %elifctx;
%elifnctx;
%ifctx;
%ifnctx;
testing, context stack}
\keepn\f2\b\fs30\sb60\sa60
4.4.3. {\f1 %ifctx}: Testing the Context Stack
\par\pard\plain\sb120
The conditional-assembly construct {\f1 %ifctx\'A0ctxname} will cause the 
subsequent code to be assembled if and only if the top context on the 
preprocessor's context stack has the name {\f1 ctxname}. As with 
{\f1 %ifdef}, the inverse and {\f1 %elif} forms {\f1 %ifnctx}, 
{\f1 %elifctx} and {\f1 %elifnctx} are also supported.
\par\sb120
For more details of the context stack, see {\uldb section 
4.7}{\v section_4_7}. For a sample use of {\f1 %ifctx}, see {\uldb section 
4.7.5}{\v section_4_7_5}.
\par\sb120
\page
#{\footnote section_4_4_4}
${\footnote 4.4.4. %if: Testing Arbitrary Numeric Expressions}
+{\footnote browse:00091}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_4')");
EnableButton("btn_up")}
K{\footnote != operator;
&& operator;
< operator;
<= operator;
<> operator;
= operator;
== operator;
> operator;
>= operator;
^^ operator;
|| operator;
%elif;
%if;
logical AND;
logical OR;
logical XOR;
relational operators;
testing, arbitrary numeric expressions}
\keepn\f2\b\fs30\sb60\sa60
4.4.4. {\f1 %if}: Testing Arbitrary Numeric Expressions
\par\pard\plain\sb120
The conditional-assembly construct {\f1 %if\'A0expr} will cause the 
subsequent code to be assembled if and only if the value of the numeric 
expression {\f1 expr} is non-zero. An example of the use of this feature is 
in deciding when to break out of a {\f1 %rep} preprocessor loop: see 
{\uldb section 4.5}{\v section_4_5} for a detailed example.
\par\sb120
The expression given to {\f1 %if}, and its counterpart {\f1 %elif}, is a 
critical expression (see {\uldb section 3.8}{\v section_3_8}).
\par\sb120
{\f1 %if} extends the normal NASM expression syntax, by providing a set of 
relational operators which are not normally available in expressions. The 
operators {\f1 =}, {\f1 <}, {\f1 >}, {\f1 <=}, {\f1 >=} and {\f1 <>} test 
equality, less-than, greater-than, less-or-equal, greater-or-equal and 
not-equal respectively. The C-like forms {\f1 ==} and {\f1 !=} are 
supported as alternative forms of {\f1 =} and {\f1 <>}. In addition, 
low-priority logical operators {\f1 &&}, {\f1 ^^} and {\f1 ||} are 
provided, supplying logical AND, logical XOR and logical OR. These work 
like the C logical operators (although C has no logical XOR), in that they 
always return either 0 or 1, and treat any non-zero input as 1 (so that 
{\f1 ^^}, for example, returns 1 if exactly one of its inputs is zero, and 
0 otherwise). The relational operators also return 1 for true and 0 for 
false.
\par\sb120
\page
#{\footnote section_4_4_5}
${\footnote 4.4.5. %ifidn and %ifidni: Testing Exact Text Identity}
+{\footnote browse:00092}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_4')");
EnableButton("btn_up")}
K{\footnote case sensitivity;
%elifidn;
%elifidni;
%elifnidn;
%elifnidni;
%ifidn;
%ifidni;
%ifnidn;
%ifnidni;
testing, exact text identity}
\keepn\f2\b\fs30\sb60\sa60
4.4.5. {\f1 %ifidn} and {\f1 %ifidni}: Testing Exact Text Identity
\par\pard\plain\sb120
The construct {\f1 %ifidn\'A0text1,text2} will cause the subsequent code to 
be assembled if and only if {\f1 text1} and {\f1 text2}, after expanding 
single-line macros, are identical pieces of text. Differences in white 
space are not counted.
\par\sb120
{\f1 %ifidni} is similar to {\f1 %ifidn}, but is case\'ADinsensitive.
\par\sb120
For example, the following macro pushes a register or number on the stack, 
and allows you to treat {\f1 IP} as a real register:
\par\sb120
\keep\f1\sb120
%macro  pushparam 1 \par\sb0
\par\sb0
  %ifidni %1,ip \par\sb0
        call    %%label \par\sb0
  %%label: \par\sb0
  %else \par\sb0
        push    %1 \par\sb0
  %endif \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
Like most other {\f1 %if} constructs, {\f1 %ifidn} has a counterpart 
{\f1 %elifidn}, and negative forms {\f1 %ifnidn} and {\f1 %elifnidn}. 
Similarly, {\f1 %ifidni} has counterparts {\f1 %elifidni}, {\f1 %ifnidni} 
and {\f1 %elifnidni}.
\par\sb120
\page
#{\footnote section_4_4_6}
${\footnote 4.4.6. %ifid, %ifnum, %ifstr: Testing Token Types}
+{\footnote browse:00093}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_4')");
EnableButton("btn_up")}
K{\footnote %elifid;
%elifnid;
%elifnnum;
%elifnstr;
%elifnum;
%elifstr;
%ifid;
%ifnid;
%ifnnum;
%ifnstr;
%ifnum;
%ifstr;
testing, token types}
\keepn\f2\b\fs30\sb60\sa60
4.4.6. {\f1 %ifid}, {\f1 %ifnum}, {\f1 %ifstr}: Testing Token Types
\par\pard\plain\sb120
Some macros will want to perform different tasks depending on whether they 
are passed a number, a string, or an identifier. For example, a string 
output macro might want to be able to cope with being passed either a 
string constant or a pointer to an existing string.
\par\sb120
The conditional assembly construct {\f1 %ifid}, taking one parameter (which 
may be blank), assembles the subsequent code if and only if the first token 
in the parameter exists and is an identifier. {\f1 %ifnum} works similarly, 
but tests for the token being a numeric constant; {\f1 %ifstr} tests for it 
being a string.
\par\sb120
For example, the {\f1 writefile} macro defined in {\uldb section 
4.3.3}{\v section_4_3_3} can be extended to take advantage of {\f1 %ifstr} 
in the following fashion:
\par\sb120
\keep\f1\sb120
%macro writefile 2-3+ \par\sb0
\par\sb0
  %ifstr %2 \par\sb0
        jmp     %%endstr \par\sb0
    %if %0 = 3 \par\sb0
      %%str:    db      %2,%3 \par\sb0
    %else \par\sb0
      %%str:    db      %2 \par\sb0
    %endif \par\sb0
      %%endstr: mov     dx,%%str \par\sb0
                mov     cx,%%endstr-%%str \par\sb0
  %else \par\sb0
                mov     dx,%2 \par\sb0
                mov     cx,%3 \par\sb0
  %endif \par\sb0
                mov     bx,%1 \par\sb0
                mov     ah,0x40 \par\sb0
                int     0x21 \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
Then the {\f1 writefile} macro can cope with being called in either of the 
following two ways:
\par\sb120
\keep\f1\sb120
        writefile [file], strpointer, length \par\sb0
        writefile [file], "hello", 13, 10\par\sb0
\pard\f0\sb120
In the first, {\f1 strpointer} is used as the address of an 
already-declared string, and {\f1 length} is used as its length; in the 
second, a string is given to the macro, which therefore declares it itself 
and works out the address and length for itself.
\par\sb120
Note the use of {\f1 %if} inside the {\f1 %ifstr}: this is to detect 
whether the macro was passed two arguments (so the string would be a single 
string constant, and {\f1 db\'A0%2} would be adequate) or more (in which 
case, all but the first two would be lumped together into {\f1 %3}, and 
{\f1 db\'A0%2,%3} would be required).
\par\sb120
  The usual {\f1 %elifXXX}, {\f1 %ifnXXX} and {\f1 %elifnXXX} versions 
exist for each of {\f1 %ifid}, {\f1 %ifnum} and {\f1 %ifstr}.
\par\sb120
\page
#{\footnote section_4_4_7}
${\footnote 4.4.7. %error: Reporting User\'ADDefined Errors}
+{\footnote browse:00094}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_4')");
EnableButton("btn_up")}
K{\footnote %error;
user\'ADdefined errors}
\keepn\f2\b\fs30\sb60\sa60
4.4.7. {\f1 %error}: Reporting User\'ADDefined Errors
\par\pard\plain\sb120
The preprocessor directive {\f1 %error} will cause NASM to report an error 
if it occurs in assembled code. So if other users are going to try to 
assemble your source files, you can ensure that they define the right 
macros by means of code like this:
\par\sb120
\keep\f1\sb120
%ifdef SOME_MACRO \par\sb0
    ; do some setup \par\sb0
%elifdef SOME_OTHER_MACRO \par\sb0
    ; do some different setup \par\sb0
%else \par\sb0
    %error Neither SOME_MACRO nor SOME_OTHER_MACRO was defined. \par\sb0
%endif\par\sb0
\pard\f0\sb120
Then any user who fails to understand the way your code is supposed to be 
assembled will be quickly warned of their mistake, rather than having to 
wait until the program crashes on being run and then not knowing what went 
wrong.
\par\sb120
\page
#{\footnote section_4_5}
${\footnote 4.5. Preprocessor Loops: %rep}
+{\footnote browse:00095}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote %endrep;
%exitrep;
preprocessor loops;
%rep;
repeating}
\keepn\f2\b\fs30\sb60\sa60
4.5. Preprocessor Loops: {\f1 %rep}
\par\pard\plain\sb120
NASM's {\f1 TIMES} prefix, though useful, cannot be used to invoke a 
multi-line macro multiple times, because it is processed by NASM after 
macros have already been expanded. Therefore NASM provides another form of 
loop, this time at the preprocessor level: {\f1 %rep}.
\par\sb120
The directives {\f1 %rep} and {\f1 %endrep} ({\f1 %rep} takes a numeric 
argument, which can be an expression; {\f1 %endrep} takes no arguments) can 
be used to enclose a chunk of code, which is then replicated as many times 
as specified by the preprocessor:
\par\sb120
\keep\f1\sb120
%assign i 0 \par\sb0
%rep    64 \par\sb0
        inc     word [table+2*i] \par\sb0
%assign i i+1 \par\sb0
%endrep\par\sb0
\pard\f0\sb120
This will generate a sequence of 64 {\f1 INC} instructions, incrementing 
every word of memory from {\f1 [table]} to {\f1 [table+126]}.
\par\sb120
For more complex termination conditions, or to break out of a repeat loop 
part way along, you can use the {\f1 %exitrep} directive to terminate the 
loop, like this:
\par\sb120
\keep\f1\sb120
fibonacci: \par\sb0
%assign i 0 \par\sb0
%assign j 1 \par\sb0
%rep 100 \par\sb0
%if j > 65535 \par\sb0
    %exitrep \par\sb0
%endif \par\sb0
        dw j \par\sb0
%assign k j+i \par\sb0
%assign i j \par\sb0
%assign j k \par\sb0
%endrep \par\sb0
\par\sb0
fib_number equ ($-fibonacci)/2\par\sb0
\pard\f0\sb120
This produces a list of all the Fibonacci numbers that will fit in 16 bits. 
Note that a maximum repeat count must still be given to {\f1 %rep}. This is 
to prevent the possibility of NASM getting into an infinite loop in the 
preprocessor, which (on multitasking or multi-user systems) would typically 
cause all the system memory to be gradually used up and other applications 
to start crashing.
\par\sb120
\page
#{\footnote section_4_6}
${\footnote 4.6. Including Other Files}
+{\footnote browse:00096}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote %include;
including other files;
\'ADp option;
searching for include files}
\keepn\f2\b\fs30\sb60\sa60
4.6. Including Other Files
\par\pard\plain\sb120
Using, once again, a very similar syntax to the C preprocessor, NASM's 
preprocessor lets you include other source files into your code. This is 
done by the use of the {\f1 %include} directive:
\par\sb120
\keep\f1\sb120
%include "macros.mac"\par\sb0
\pard\f0\sb120
will include the contents of the file {\f1 macros.mac} into the source file 
containing the {\f1 %include} directive.
\par\sb120
Include files are searched for in the current directory (the directory 
you're in when you run NASM, as opposed to the location of the NASM 
executable or the location of the source file), plus any directories 
specified on the NASM command line using the {\f1 \'ADi} option.
\par\sb120
The standard C idiom for preventing a file being included more than once is 
just as applicable in NASM: if the file {\f1 macros.mac} has the form
\par\sb120
\keep\f1\sb120
%ifndef MACROS_MAC \par\sb0
    %define MACROS_MAC \par\sb0
    ; now define some macros \par\sb0
%endif\par\sb0
\pard\f0\sb120
then including the file more than once will not cause errors, because the 
second time the file is included nothing will happen because the macro 
{\f1 MACROS_MAC} will already be defined.
\par\sb120
You can force a file to be included even if there is no {\f1 %include} 
directive that explicitly includes it, by using the {\f1 \'ADp} option on 
the NASM command line (see {\uldb section 2.1.11}{\v section_2_1_11}).
\par\sb120
\page
#{\footnote section_4_7}
${\footnote 4.7. The Context Stack}
+{\footnote browse:00097}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote context stack;
%pop;
%push}
\keepn\f2\b\fs30\sb60\sa60
4.7. The Context Stack
\par\pard\plain\sb120
Having labels that are local to a macro definition is sometimes not quite 
powerful enough: sometimes you want to be able to share labels between 
several macro calls. An example might be a {\f1 REPEAT} ... {\f1 UNTIL} 
loop, in which the expansion of the {\f1 REPEAT} macro would need to be 
able to refer to a label which the {\f1 UNTIL} macro had defined. However, 
for such a macro you would also want to be able to nest these loops.
\par\sb120
NASM provides this level of power by means of a {\i context stack}. The 
preprocessor maintains a stack of {\i contexts}, each of which is 
characterised by a name. You add a new context to the stack using the 
{\f1 %push} directive, and remove one using {\f1 %pop}. You can define 
labels that are local to a particular context on the stack.
\par\sb120
\li360\fi-360
{\uldb Section 4.7.1: %push and %pop: Creating and Removing Contexts}{\v section_4_7_1}\par\sb0
{\uldb Section 4.7.2: Context\'ADLocal Labels}{\v section_4_7_2}\par\sb0
{\uldb Section 4.7.3: Context\'ADLocal Single\'ADLine Macros}{\v section_4_7_3}\par\sb0
{\uldb Section 4.7.4: %repl: Renaming a Context}{\v section_4_7_4}\par\sb0
{\uldb Section 4.7.5: Example Use of the Context Stack: Block IFs}{\v section_4_7_5}\par\sb0
\pard\sb120
\page
#{\footnote section_4_7_1}
${\footnote 4.7.1. %push and %pop: Creating and Removing Contexts}
+{\footnote browse:00098}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_7')");
EnableButton("btn_up")}
K{\footnote creating contexts;
%pop;
%push;
removing contexts}
\keepn\f2\b\fs30\sb60\sa60
4.7.1. {\f1 %push} and {\f1 %pop}: Creating and Removing Contexts
\par\pard\plain\sb120
The {\f1 %push} directive is used to create a new context and place it on 
the top of the context stack. {\f1 %push} requires one argument, which is 
the name of the context. For example:
\par\sb120
\keep\f1\sb120
%push    foobar\par\sb0
\pard\f0\sb120
This pushes a new context called {\f1 foobar} on the stack. You can have 
several contexts on the stack with the same name: they can still be 
distinguished.
\par\sb120
The directive {\f1 %pop}, requiring no arguments, removes the top context 
from the context stack and destroys it, along with any labels associated 
with it.
\par\sb120
\page
#{\footnote section_4_7_2}
${\footnote 4.7.2. Context\'ADLocal Labels}
+{\footnote browse:00099}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_7')");
EnableButton("btn_up")}
K{\footnote %$ and %$$ prefixes;
context\'ADlocal labels}
\keepn\f2\b\fs30\sb60\sa60
4.7.2. Context\'ADLocal Labels
\par\pard\plain\sb120
Just as the usage {\f1 %%foo} defines a label which is local to the 
particular macro call in which it is used, the usage {\f1 %$foo} is used to 
define a label which is local to the context on the top of the context 
stack. So the {\f1 REPEAT} and {\f1 UNTIL} example given above could be 
implemented by means of:
\par\sb120
\keep\f1\sb120
%macro repeat 0 \par\sb0
\par\sb0
    %push   repeat \par\sb0
    %$begin: \par\sb0
\par\sb0
%endmacro \par\sb0
\par\sb0
%macro until 1 \par\sb0
\par\sb0
        j%-1    %$begin \par\sb0
    %pop \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
and invoked by means of, for example,
\par\sb120
\keep\f1\sb120
        mov     cx,string \par\sb0
        repeat \par\sb0
        add     cx,3 \par\sb0
        scasb \par\sb0
        until   e\par\sb0
\pard\f0\sb120
which would scan every fourth byte of a string in search of the byte in 
{\f1 AL}.
\par\sb120
If you need to define, or access, labels local to the context {\i below} 
the top one on the stack, you can use {\f1 %$$foo}, or {\f1 %$$$foo} for 
the context below that, and so on.
\par\sb120
\page
#{\footnote section_4_7_3}
${\footnote 4.7.3. Context\'ADLocal Single\'ADLine Macros}
+{\footnote browse:00100}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_7')");
EnableButton("btn_up")}
K{\footnote context\'ADlocal single\'ADline macros}
\keepn\f2\b\fs30\sb60\sa60
4.7.3. Context\'ADLocal Single\'ADLine Macros
\par\pard\plain\sb120
NASM also allows you to define single-line macros which are local to a 
particular context, in just the same way:
\par\sb120
\keep\f1\sb120
%define %$localmac 3\par\sb0
\pard\f0\sb120
will define the single-line macro {\f1 %$localmac} to be local to the top 
context on the stack. Of course, after a subsequent {\f1 %push}, it can 
then still be accessed by the name {\f1 %$$localmac}.
\par\sb120
\page
#{\footnote section_4_7_4}
${\footnote 4.7.4. %repl: Renaming a Context}
+{\footnote browse:00101}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_7')");
EnableButton("btn_up")}
K{\footnote renaming contexts;
%repl}
\keepn\f2\b\fs30\sb60\sa60
4.7.4. {\f1 %repl}: Renaming a Context
\par\pard\plain\sb120
If you need to change the name of the top context on the stack (in order, 
for example, to have it respond differently to {\f1 %ifctx}), you can 
execute a {\f1 %pop} followed by a {\f1 %push}; but this will have the side 
effect of destroying all context-local labels and macros associated with 
the context that was just popped.
\par\sb120
NASM provides the directive {\f1 %repl}, which {\i replaces} a context with 
a different name, without touching the associated macros and labels. So you 
could replace the destructive code
\par\sb120
\keep\f1\sb120
%pop \par\sb0
%push   newname\par\sb0
\pard\f0\sb120
with the non-destructive version {\f1 %repl\'A0newname}.
\par\sb120
\page
#{\footnote section_4_7_5}
${\footnote 4.7.5. Example Use of the Context Stack: Block IFs}
+{\footnote browse:00102}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_7')");
EnableButton("btn_up")}
K{\footnote block IFs;
context stack;
%ifctx}
\keepn\f2\b\fs30\sb60\sa60
4.7.5. Example Use of the Context Stack: Block IFs
\par\pard\plain\sb120
This example makes use of almost all the context-stack features, including 
the conditional-assembly construct {\f1 %ifctx}, to implement a block IF 
statement as a set of macros.
\par\sb120
\keep\f1\sb120
%macro if 1 \par\sb0
\par\sb0
    %push if \par\sb0
    j%-1  %$ifnot \par\sb0
\par\sb0
%endmacro \par\sb0
\par\sb0
%macro else 0 \par\sb0
\par\sb0
  %ifctx if \par\sb0
        %repl   else \par\sb0
        jmp     %$ifend \par\sb0
        %$ifnot: \par\sb0
  %else \par\sb0
        %error  "expected `if' before `else'" \par\sb0
  %endif \par\sb0
\par\sb0
%endmacro \par\sb0
\par\sb0
%macro endif 0 \par\sb0
\par\sb0
  %ifctx if \par\sb0
        %$ifnot: \par\sb0
        %pop \par\sb0
  %elifctx      else \par\sb0
        %$ifend: \par\sb0
        %pop \par\sb0
  %else \par\sb0
        %error  "expected `if' or `else' before `endif'" \par\sb0
  %endif \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
This code is more robust than the {\f1 REPEAT} and {\f1 UNTIL} macros given 
in {\uldb section 4.7.2}{\v section_4_7_2}, because it uses conditional 
assembly to check that the macros are issued in the right order (for 
example, not calling {\f1 endif} before {\f1 if}) and issues a {\f1 %error} 
if they're not.
\par\sb120
In addition, the {\f1 endif} macro has to be able to cope with the two 
distinct cases of either directly following an {\f1 if}, or following an 
{\f1 else}. It achieves this, again, by using conditional assembly to do 
different things depending on whether the context on top of the stack is 
{\f1 if} or {\f1 else}.
\par\sb120
The {\f1 else} macro has to preserve the context on the stack, in order to 
have the {\f1 %$ifnot} referred to by the {\f1 if} macro be the same as the 
one defined by the {\f1 endif} macro, but has to change the context's name 
so that {\f1 endif} will know there was an intervening {\f1 else}. It does 
this by the use of {\f1 %repl}.
\par\sb120
A sample usage of these macros might look like:
\par\sb120
\keep\f1\sb120
        cmp     ax,bx \par\sb0
\par\sb0
        if ae \par\sb0
               cmp     bx,cx \par\sb0
\par\sb0
               if ae \par\sb0
                       mov     ax,cx \par\sb0
               else \par\sb0
                       mov     ax,bx \par\sb0
               endif \par\sb0
\par\sb0
        else \par\sb0
               cmp     ax,cx \par\sb0
\par\sb0
               if ae \par\sb0
                       mov     ax,cx \par\sb0
               endif \par\sb0
\par\sb0
        endif\par\sb0
\pard\f0\sb120
The block-{\f1 IF} macros handle nesting quite happily, by means of pushing 
another context, describing the inner {\f1 if}, on top of the one 
describing the outer {\f1 if}; thus {\f1 else} and {\f1 endif} always refer 
to the last unmatched {\f1 if} or {\f1 else}.
\par\sb120
\page
#{\footnote section_4_8}
${\footnote 4.8. Standard Macros}
+{\footnote browse:00103}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote %clear;
standard macros;
user\'ADlevel assembler directives}
\keepn\f2\b\fs30\sb60\sa60
4.8. Standard Macros
\par\pard\plain\sb120
NASM defines a set of standard macros, which are already defined when it 
starts to process any source file. If you really need a program to be 
assembled with no pre-defined macros, you can use the {\f1 %clear} 
directive to empty the preprocessor of everything.
\par\sb120
Most user\'ADlevel assembler directives (see {\uldb chapter 
5}{\v chapter_5}) are implemented as macros which invoke primitive 
directives; these are described in {\uldb chapter 5}{\v chapter_5}. The 
rest of the standard macro set is described here.
\par\sb120
\li360\fi-360
{\uldb Section 4.8.1: __NASM_MAJOR__, __NASM_MINOR__, __NASM_SUBMINOR__ and ___NASM_PATCHLEVEL__: NASM Version}{\v section_4_8_1}\par\sb0
{\uldb Section 4.8.2: __NASM_VERSION_ID__: NASM Version ID}{\v section_4_8_2}\par\sb0
{\uldb Section 4.8.3: __NASM_VER__: NASM Version string}{\v section_4_8_3}\par\sb0
{\uldb Section 4.8.4: __FILE__ and __LINE__: File Name and Line Number}{\v section_4_8_4}\par\sb0
{\uldb Section 4.8.5: STRUC and ENDSTRUC: Declaring Structure Data Types}{\v section_4_8_5}\par\sb0
{\uldb Section 4.8.6: ISTRUC, AT and IEND: Declaring Instances of Structures}{\v section_4_8_6}\par\sb0
{\uldb Section 4.8.7: ALIGN and ALIGNB: Data Alignment}{\v section_4_8_7}\par\sb0
\pard\sb120
\page
#{\footnote section_4_8_1}
${\footnote 4.8.1. __NASM_MAJOR__, __NASM_MINOR__, __NASM_SUBMINOR__ and ___NASM_PATCHLEVEL__: NASM Version}
+{\footnote browse:00104}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_8')");
EnableButton("btn_up")}
K{\footnote NASM version;
__NASM_MAJOR__;
__NASM_MINOR__;
___NASM_PATCHLEVEL__;
__NASM_SUBMINOR__;
version number of NASM}
\keepn\f2\b\fs30\sb60\sa60
4.8.1. {\f1 __NASM_MAJOR__}, {\f1 __NASM_MINOR__}, {\f1 __NASM_SUBMINOR__} and {\f1 ___NASM_PATCHLEVEL__}: NASM Version
\par\pard\plain\sb120
The single-line macros {\f1 __NASM_MAJOR__}, {\f1 __NASM_MINOR__}, 
{\f1 __NASM_SUBMINOR__} and {\f1 ___NASM_PATCHLEVEL__} expand to the major, 
minor, subminor and patch level parts of the version number of NASM being 
used. So, under NASM 0.98.32p1 for example, {\f1 __NASM_MAJOR__} would be 
defined to be 0, {\f1 __NASM_MINOR__} would be defined as 98, 
{\f1 __NASM_SUBMINOR__} would be defined to 32, and 
{\f1 ___NASM_PATCHLEVEL__} would be defined as 1.
\par\sb120
\page
#{\footnote section_4_8_2}
${\footnote 4.8.2. __NASM_VERSION_ID__: NASM Version ID}
+{\footnote browse:00105}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_8')");
EnableButton("btn_up")}
K{\footnote nasm version id;
__NASM_VERSION_ID__}
\keepn\f2\b\fs30\sb60\sa60
4.8.2. {\f1 __NASM_VERSION_ID__}: NASM Version ID
\par\pard\plain\sb120
The single-line macro {\f1 __NASM_VERSION_ID__} expands to a dword integer 
representing the full version number of the version of nasm being used. The 
value is the equivalent to {\f1 __NASM_MAJOR__}, {\f1 __NASM_MINOR__}, 
{\f1 __NASM_SUBMINOR__} and {\f1 ___NASM_PATCHLEVEL__} concatenated to 
produce a single doubleword. Hence, for 0.98.32p1, the returned number 
would be equivalent to:
\par\sb120
\keep\f1\sb120
        dd      0x00622001\par\sb0
\pard\f0\sb120
or
\par\sb120
\keep\f1\sb120
        db      1,32,98,0\par\sb0
\pard\f0\sb120
Note that the above lines are generate exactly the same code, the second 
line is used just to give an indication of the order that the separate 
values will be present in memory.
\par\sb120
\page
#{\footnote section_4_8_3}
${\footnote 4.8.3. __NASM_VER__: NASM Version string}
+{\footnote browse:00106}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_8')");
EnableButton("btn_up")}
K{\footnote nasm version string;
__NASM_VER__}
\keepn\f2\b\fs30\sb60\sa60
4.8.3. {\f1 __NASM_VER__}: NASM Version string
\par\pard\plain\sb120
The single-line macro {\f1 __NASM_VER__} expands to a string which defines 
the version number of nasm being used. So, under NASM 0.98.32 for example,
\par\sb120
\keep\f1\sb120
        db      __NASM_VER__\par\sb0
\pard\f0\sb120
would expand to
\par\sb120
\keep\f1\sb120
        db      "0.98.32"\par\sb0
\pard\f0\sb120
\page
#{\footnote section_4_8_4}
${\footnote 4.8.4. __FILE__ and __LINE__: File Name and Line Number}
+{\footnote browse:00107}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_8')");
EnableButton("btn_up")}
K{\footnote __FILE__;
__LINE__}
\keepn\f2\b\fs30\sb60\sa60
4.8.4. {\f1 __FILE__} and {\f1 __LINE__}: File Name and Line Number
\par\pard\plain\sb120
Like the C preprocessor, NASM allows the user to find out the file name and 
line number containing the current instruction. The macro {\f1 __FILE__} 
expands to a string constant giving the name of the current input file 
(which may change through the course of assembly if {\f1 %include} 
directives are used), and {\f1 __LINE__} expands to a numeric constant 
giving the current line number in the input file.
\par\sb120
These macros could be used, for example, to communicate debugging 
information to a macro, since invoking {\f1 __LINE__} inside a macro 
definition (either single-line or multi-line) will return the line number 
of the macro {\i call}, rather than {\i definition}. So to determine where 
in a piece of code a crash is occurring, for example, one could write a 
routine {\f1 stillhere}, which is passed a line number in {\f1 EAX} and 
outputs something like `line 155: still here'. You could then write a macro
\par\sb120
\keep\f1\sb120
%macro  notdeadyet 0 \par\sb0
\par\sb0
        push    eax \par\sb0
        mov     eax,__LINE__ \par\sb0
        call    stillhere \par\sb0
        pop     eax \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
and then pepper your code with calls to {\f1 notdeadyet} until you find the 
crash point.
\par\sb120
\page
#{\footnote section_4_8_5}
${\footnote 4.8.5. STRUC and ENDSTRUC: Declaring Structure Data Types}
+{\footnote browse:00108}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_8')");
EnableButton("btn_up")}
K{\footnote declaring structures;
ENDSTRUC;
STRUC}
\keepn\f2\b\fs30\sb60\sa60
4.8.5. {\f1 STRUC} and {\f1 ENDSTRUC}: Declaring Structure Data Types
\par\pard\plain\sb120
The core of NASM contains no intrinsic means of defining data structures; 
instead, the preprocessor is sufficiently powerful that data structures can 
be implemented as a set of macros. The macros {\f1 STRUC} and 
{\f1 ENDSTRUC} are used to define a structure data type.
\par\sb120
{\f1 STRUC} takes one parameter, which is the name of the data type. This 
name is defined as a symbol with the value zero, and also has the suffix 
{\f1 _size} appended to it and is then defined as an {\f1 EQU} giving the 
size of the structure. Once {\f1 STRUC} has been issued, you are defining 
the structure, and should define fields using the {\f1 RESB} family of 
pseudo-instructions, and then invoke {\f1 ENDSTRUC} to finish the 
definition.
\par\sb120
For example, to define a structure called {\f1 mytype} containing a 
longword, a word, a byte and a string of bytes, you might code
\par\sb120
\keep\f1\sb120
struc   mytype \par\sb0
\par\sb0
  mt_long:      resd    1 \par\sb0
  mt_word:      resw    1 \par\sb0
  mt_byte:      resb    1 \par\sb0
  mt_str:       resb    32 \par\sb0
\par\sb0
endstruc\par\sb0
\pard\f0\sb120
The above code defines six symbols: {\f1 mt_long} as 0 (the offset from the 
beginning of a {\f1 mytype} structure to the longword field), {\f1 mt_word} 
as 4, {\f1 mt_byte} as 6, {\f1 mt_str} as 7, {\f1 mytype_size} as 39, and 
{\f1 mytype} itself as zero.
\par\sb120
The reason why the structure type name is defined at zero is a side effect 
of allowing structures to work with the local label mechanism: if your 
structure members tend to have the same names in more than one structure, 
you can define the above structure like this:
\par\sb120
\keep\f1\sb120
struc mytype \par\sb0
\par\sb0
  .long:        resd    1 \par\sb0
  .word:        resw    1 \par\sb0
  .byte:        resb    1 \par\sb0
  .str:         resb    32 \par\sb0
\par\sb0
endstruc\par\sb0
\pard\f0\sb120
This defines the offsets to the structure fields as {\f1 mytype.long}, 
{\f1 mytype.word}, {\f1 mytype.byte} and {\f1 mytype.str}.
\par\sb120
NASM, since it has no {\i intrinsic} structure support, does not support 
any form of period notation to refer to the elements of a structure once 
you have one (except the above local-label notation), so code such as 
{\f1 mov\'A0ax,[mystruc.mt_word]} is not valid. {\f1 mt_word} is a constant 
just like any other constant, so the correct syntax is 
{\f1 mov\'A0ax,[mystruc+mt_word]} or {\f1 mov\'A0ax,[mystruc+mytype.word]}.
\par\sb120
\page
#{\footnote section_4_8_6}
${\footnote 4.8.6. ISTRUC, AT and IEND: Declaring Instances of Structures}
+{\footnote browse:00109}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_8')");
EnableButton("btn_up")}
K{\footnote AT;
IEND;
instances of structures;
ISTRUC}
\keepn\f2\b\fs30\sb60\sa60
4.8.6. {\f1 ISTRUC}, {\f1 AT} and {\f1 IEND}: Declaring Instances of Structures
\par\pard\plain\sb120
Having defined a structure type, the next thing you typically want to do is 
to declare instances of that structure in your data segment. NASM provides 
an easy way to do this in the {\f1 ISTRUC} mechanism. To declare a 
structure of type {\f1 mytype} in a program, you code something like this:
\par\sb120
\keep\f1\sb120
mystruc: \par\sb0
    istruc mytype \par\sb0
\par\sb0
        at mt_long, dd      123456 \par\sb0
        at mt_word, dw      1024 \par\sb0
        at mt_byte, db      'x' \par\sb0
        at mt_str,  db      'hello, world', 13, 10, 0 \par\sb0
\par\sb0
    iend\par\sb0
\pard\f0\sb120
The function of the {\f1 AT} macro is to make use of the {\f1 TIMES} prefix 
to advance the assembly position to the correct point for the specified 
structure field, and then to declare the specified data. Therefore the 
structure fields must be declared in the same order as they were specified 
in the structure definition.
\par\sb120
If the data to go in a structure field requires more than one source line 
to specify, the remaining source lines can easily come after the {\f1 AT} 
line. For example:
\par\sb120
\keep\f1\sb120
        at mt_str,  db      123,134,145,156,167,178,189 \par\sb0
                    db      190,100,0\par\sb0
\pard\f0\sb120
Depending on personal taste, you can also omit the code part of the 
{\f1 AT} line completely, and start the structure field on the next line:
\par\sb120
\keep\f1\sb120
        at mt_str \par\sb0
                db      'hello, world' \par\sb0
                db      13,10,0\par\sb0
\pard\f0\sb120
\page
#{\footnote section_4_8_7}
${\footnote 4.8.7. ALIGN and ALIGNB: Data Alignment}
+{\footnote browse:00110}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_8')");
EnableButton("btn_up")}
K{\footnote ALIGN;
ALIGNB;
EVEN}
\keepn\f2\b\fs30\sb60\sa60
4.8.7. {\f1 ALIGN} and {\f1 ALIGNB}: Data Alignment
\par\pard\plain\sb120
The {\f1 ALIGN} and {\f1 ALIGNB} macros provides a convenient way to align 
code or data on a word, longword, paragraph or other boundary. (Some 
assemblers call this directive {\f1 EVEN}.) The syntax of the {\f1 ALIGN} 
and {\f1 ALIGNB} macros is
\par\sb120
\keep\f1\sb120
        align   4               ; align on 4-byte boundary \par\sb0
        align   16              ; align on 16-byte boundary \par\sb0
        align   8,db 0          ; pad with 0s rather than NOPs \par\sb0
        align   4,resb 1        ; align to 4 in the BSS \par\sb0
        alignb  4               ; equivalent to previous line\par\sb0
\pard\f0\sb120
Both macros require their first argument to be a power of two; they both 
compute the number of additional bytes required to bring the length of the 
current section up to a multiple of that power of two, and then apply the 
{\f1 TIMES} prefix to their second argument to perform the alignment.
\par\sb120
If the second argument is not specified, the default for {\f1 ALIGN} is 
{\f1 NOP}, and the default for {\f1 ALIGNB} is {\f1 RESB\'A01}. So if the 
second argument is specified, the two macros are equivalent. Normally, you 
can just use {\f1 ALIGN} in code and data sections and {\f1 ALIGNB} in BSS 
sections, and never need the second argument except for special purposes.
\par\sb120
{\f1 ALIGN} and {\f1 ALIGNB}, being simple macros, perform no error 
checking: they cannot warn you if their first argument fails to be a power 
of two, or if their second argument generates more than one byte of code. 
In each of these cases they will silently do the wrong thing.
\par\sb120
{\f1 ALIGNB} (or {\f1 ALIGN} with a second argument of {\f1 RESB\'A01}) can 
be used within structure definitions:
\par\sb120
\keep\f1\sb120
struc mytype2 \par\sb0
\par\sb0
  mt_byte: \par\sb0
        resb 1 \par\sb0
        alignb 2 \par\sb0
  mt_word: \par\sb0
        resw 1 \par\sb0
        alignb 4 \par\sb0
  mt_long: \par\sb0
        resd 1 \par\sb0
  mt_str: \par\sb0
        resb 32 \par\sb0
\par\sb0
endstruc\par\sb0
\pard\f0\sb120
This will ensure that the structure members are sensibly aligned relative 
to the base of the structure.
\par\sb120
A final caveat: {\f1 ALIGN} and {\f1 ALIGNB} work relative to the beginning 
of the {\i section}, not the beginning of the address space in the final 
executable. Aligning to a 16-byte boundary when the section you're in is 
only guaranteed to be aligned to a 4-byte boundary, for example, is a waste 
of effort. Again, NASM does not check that the section's alignment 
characteristics are sensible for the use of {\f1 ALIGN} or {\f1 ALIGNB}.
\par\sb120
\page
#{\footnote section_4_9}
${\footnote 4.9. TASM Compatible Preprocessor Directives}
+{\footnote browse:00111}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote tasm compatible preprocessor directives}
\keepn\f2\b\fs30\sb60\sa60
4.9. TASM Compatible Preprocessor Directives
\par\pard\plain\sb120
The following preprocessor directives may only be used when TASM 
compatibility is turned on using the {\f1 \'ADt} command line switch (This 
switch is described in {\uldb section 2.1.17}{\v section_2_1_17}.)
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 %arg} (see {\uldb section 4.9.1}{\v section_4_9_1})
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 %stacksize} (see {\uldb section 4.9.2}{\v section_4_9_2})
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 %local} (see {\uldb section 4.9.3}{\v section_4_9_3})
\par\pard\sb120
\li360\fi-360
{\uldb Section 4.9.1: %arg Directive}{\v section_4_9_1}\par\sb0
{\uldb Section 4.9.2: %stacksize Directive}{\v section_4_9_2}\par\sb0
{\uldb Section 4.9.3: %local Directive}{\v section_4_9_3}\par\sb0
\pard\sb120
\page
#{\footnote section_4_9_1}
${\footnote 4.9.1. %arg Directive}
+{\footnote browse:00112}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_9')");
EnableButton("btn_up")}
K{\footnote %arg}
\keepn\f2\b\fs30\sb60\sa60
4.9.1. {\f1 %arg} Directive
\par\pard\plain\sb120
The {\f1 %arg} directive is used to simplify the handling of parameters 
passed on the stack. Stack based parameter passing is used by many high 
level languages, including C, C++ and Pascal.
\par\sb120
While NASM comes with macros which attempt to duplicate this functionality 
(see {\uldb section 7.4.5}{\v section_7_4_5}), the syntax is not 
particularly convenient to use and is not TASM compatible. Here is an 
example which shows the use of {\f1 %arg} without any external macros:
\par\sb120
\keep\f1\sb120
some_function: \par\sb0
\par\sb0
    %push     mycontext        ; save the current context \par\sb0
    %stacksize large           ; tell NASM to use bp \par\sb0
    %arg      i:word, j_ptr:word \par\sb0
\par\sb0
        mov     ax,[i] \par\sb0
        mov     bx,[j_ptr] \par\sb0
        add     ax,[bx] \par\sb0
        ret \par\sb0
\par\sb0
    %pop                       ; restore original context\par\sb0
\pard\f0\sb120
This is similar to the procedure defined in {\uldb section 
7.4.5}{\v section_7_4_5} and adds the value in i to the value pointed to by 
j_ptr and returns the sum in the ax register. See {\uldb section 
4.7.1}{\v section_4_7_1} for an explanation of {\f1 push} and {\f1 pop} and 
the use of context stacks.
\par\sb120
\page
#{\footnote section_4_9_2}
${\footnote 4.9.2. %stacksize Directive}
+{\footnote browse:00113}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_9')");
EnableButton("btn_up")}
K{\footnote %stacksize}
\keepn\f2\b\fs30\sb60\sa60
4.9.2. {\f1 %stacksize} Directive
\par\pard\plain\sb120
The {\f1 %stacksize} directive is used in conjunction with the {\f1 %arg} 
(see {\uldb section 4.9.1}{\v section_4_9_1}) and the {\f1 %local} (see 
{\uldb section 4.9.3}{\v section_4_9_3}) directives. It tells NASM the 
default size to use for subsequent {\f1 %arg} and {\f1 %local} directives. 
The {\f1 %stacksize} directive takes one required argument which is one of 
{\f1 flat}, {\f1 large} or {\f1 small}.
\par\sb120
\keep\f1\sb120
%stacksize flat\par\sb0
\pard\f0\sb120
This form causes NASM to use stack-based parameter addressing relative to 
{\f1 ebp} and it assumes that a near form of call was used to get to this 
label (i.e. that {\f1 eip} is on the stack).
\par\sb120
\keep\f1\sb120
%stacksize large\par\sb0
\pard\f0\sb120
This form uses {\f1 bp} to do stack-based parameter addressing and assumes 
that a far form of call was used to get to this address (i.e. that {\f1 ip} 
and {\f1 cs} are on the stack).
\par\sb120
\keep\f1\sb120
%stacksize small\par\sb0
\pard\f0\sb120
This form also uses {\f1 bp} to address stack parameters, but it is 
different from {\f1 large} because it also assumes that the old value of bp 
is pushed onto the stack (i.e. it expects an {\f1 ENTER} instruction). In 
other words, it expects that {\f1 bp}, {\f1 ip} and {\f1 cs} are on the top 
of the stack, underneath any local space which may have been allocated by 
{\f1 ENTER}. This form is probably most useful when used in combination 
with the {\f1 %local} directive (see {\uldb section 
4.9.3}{\v section_4_9_3}).
\par\sb120
\page
#{\footnote section_4_9_3}
${\footnote 4.9.3. %local Directive}
+{\footnote browse:00114}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_9')");
EnableButton("btn_up")}
K{\footnote %local}
\keepn\f2\b\fs30\sb60\sa60
4.9.3. {\f1 %local} Directive
\par\pard\plain\sb120
The {\f1 %local} directive is used to simplify the use of local temporary 
stack variables allocated in a stack frame. Automatic local variables in C 
are an example of this kind of variable. The {\f1 %local} directive is most 
useful when used with the {\f1 %stacksize} (see {\uldb section 
4.9.2}{\v section_4_9_2} and is also compatible with the {\f1 %arg} 
directive (see {\uldb section 4.9.1}{\v section_4_9_1}). It allows 
simplified reference to variables on the stack which have been allocated 
typically by using the {\f1 ENTER} instruction (see {\uldb section 
B.4.65}{\v section_b_4_65} for a description of that instruction). An 
example of its use is the following:
\par\sb120
\keep\f1\sb120
silly_swap: \par\sb0
\par\sb0
    %push mycontext             ; save the current context \par\sb0
    %stacksize small            ; tell NASM to use bp \par\sb0
    %assign %$localsize 0       ; see text for explanation \par\sb0
    %local old_ax:word, old_dx:word \par\sb0
\par\sb0
        enter   %$localsize,0   ; see text for explanation \par\sb0
        mov     [old_ax],ax     ; swap ax & bx \par\sb0
        mov     [old_dx],dx     ; and swap dx & cx \par\sb0
        mov     ax,bx \par\sb0
        mov     dx,cx \par\sb0
        mov     bx,[old_ax] \par\sb0
        mov     cx,[old_dx] \par\sb0
        leave                   ; restore old bp \par\sb0
        ret                     ; \par\sb0
\par\sb0
    %pop                        ; restore original context\par\sb0
\pard\f0\sb120
The {\f1 %$localsize} variable is used internally by the {\f1 %local} 
directive and {\i must} be defined within the current context before the 
{\f1 %local} directive may be used. Failure to do so will result in one 
expression syntax error for each {\f1 %local} variable declared. It then 
may be used in the construction of an appropriately sized ENTER instruction 
as shown in the example.
\par\sb120
\page
#{\footnote section_4_10}
${\footnote 4.10. Other Preprocessor Directives}
+{\footnote browse:00115}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_4')");
EnableButton("btn_up")}
K{\footnote other preprocessor directives}
\keepn\f2\b\fs30\sb60\sa60
4.10. Other Preprocessor Directives
\par\pard\plain\sb120
NASM also has preprocessor directives which allow access to information 
from external sources. Currently they include:
\par\sb120
The following preprocessor directive is supported to allow NASM to 
correctly handle output of the cpp C language preprocessor.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 %line} enables NAsM to correctly handle the output of the cpp C 
language preprocessor (see {\uldb section 4.10.1}{\v section_4_10_1}).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 %!} enables NASM to read in the value of an environment variable, 
which can then be used in your program (see {\uldb section 
4.10.2}{\v section_4_10_2}).
\par\pard\sb120
\li360\fi-360
{\uldb Section 4.10.1: %line Directive}{\v section_4_10_1}\par\sb0
{\uldb Section 4.10.2: %!<env>: Read an environment variable.}{\v section_4_10_2}\par\sb0
\pard\sb120
\page
#{\footnote section_4_10_1}
${\footnote 4.10.1. %line Directive}
+{\footnote browse:00116}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_10')");
EnableButton("btn_up")}
K{\footnote %line}
\keepn\f2\b\fs30\sb60\sa60
4.10.1. {\f1 %line} Directive
\par\pard\plain\sb120
The {\f1 %line} directive is used to notify NASM that the input line 
corresponds to a specific line number in another file. Typically this other 
file would be an original source file, with the current NASM input being 
the output of a pre-processor. The {\f1 %line} directive allows NASM to 
output messages which indicate the line number of the original source file, 
instead of the file that is being read by NASM.
\par\sb120
This preprocessor directive is not generally of use to programmers, by may 
be of interest to preprocessor authors. The usage of the {\f1 %line} 
preprocessor directive is as follows:
\par\sb120
\keep\f1\sb120
%line nnn[+mmm] [filename]\par\sb0
\pard\f0\sb120
In this directive, {\f1 nnn} indentifies the line of the original source 
file which this line corresponds to. {\f1 mmm} is an optional parameter 
which specifies a line increment value; each line of the input file read in 
is considered to correspond to {\f1 mmm} lines of the original source file. 
Finally, {\f1 filename} is an optional parameter which specifies the file 
name of the original source file.
\par\sb120
After reading a {\f1 %line} preprocessor directive, NASM will report all 
file name and line numbers relative to the values specified therein.
\par\sb120
\page
#{\footnote section_4_10_2}
${\footnote 4.10.2. %!<env>: Read an environment variable.}
+{\footnote browse:00117}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_4_10')");
EnableButton("btn_up")}
K{\footnote %!}
\keepn\f2\b\fs30\sb60\sa60
4.10.2. {\f1 %!}{\f1 <env>}: Read an environment variable.
\par\pard\plain\sb120
The {\f1 %!<env>} directive makes it possible to read the value of an 
environment variable at assembly time. This could, for example, be used to 
store the contents of an environment variable into a string, which could be 
used at some other point in your code.
\par\sb120
For example, suppose that you have an environment variable {\f1 FOO}, and 
you want the contents of {\f1 FOO} to be embedded in your program. You 
could do that as follows:
\par\sb120
\keep\f1\sb120
%define FOO    %!FOO \par\sb0
%define quote   ' \par\sb0
\par\sb0
tmpstr  db      quote FOO quote\par\sb0
\pard\f0\sb120
At the time of writing, this will generate an "unterminated string" warning 
at the time of defining "quote", and it will add a space before and after 
the string that is read in. I was unable to find a simple workaround 
(although a workaround can be created using a multi-line macro), so I 
believe that you will need to either learn how to create more complex 
macros, or allow for the extra spaces if you make use of this feature in 
that way.
\par\sb120
\page
#{\footnote chapter_5}
${\footnote Chapter 5: Assembler Directives}
+{\footnote browse:00118}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
K{\footnote assembler directives;
format\'ADspecific directives;
primitive directives;
user\'ADlevel directives}
\keepn\f2\b\fs30\sb60\sa60
Chapter 5: Assembler Directives
\par\pard\plain\sb120
NASM, though it attempts to avoid the bureaucracy of assemblers like MASM 
and TASM, is nevertheless forced to support a {\i few} directives. These 
are described in this chapter.
\par\sb120
NASM's directives come in two types: {\i user\'ADlevel} directives and 
{\i primitive} directives. Typically, each directive has a user-level form 
and a primitive form. In almost all cases, we recommend that users use the 
user-level forms of the directives, which are implemented as macros which 
call the primitive forms.
\par\sb120
Primitive directives are enclosed in square brackets; user-level directives 
are not.
\par\sb120
In addition to the universal directives described in this chapter, each 
object file format can optionally supply extra directives in order to 
control particular features of that file format. These 
{\i format\'ADspecific} directives are documented along with the formats 
that implement them, in {\uldb chapter 6}{\v chapter_6}.
\par\sb120
\li360\fi-360
{\uldb Section 5.1: BITS: Specifying Target Processor Mode}{\v section_5_1}\par\sb0
{\uldb Section 5.2: SECTION or SEGMENT: Changing and Defining Sections}{\v section_5_2}\par\sb0
{\uldb Section 5.3: ABSOLUTE: Defining Absolute Labels}{\v section_5_3}\par\sb0
{\uldb Section 5.4: EXTERN: Importing Symbols from Other Modules}{\v section_5_4}\par\sb0
{\uldb Section 5.5: GLOBAL: Exporting Symbols to Other Modules}{\v section_5_5}\par\sb0
{\uldb Section 5.6: COMMON: Defining Common Data Areas}{\v section_5_6}\par\sb0
{\uldb Section 5.7: CPU: Defining CPU Dependencies}{\v section_5_7}\par\sb0
\pard\sb120
\page
#{\footnote section_5_1}
${\footnote 5.1. BITS: Specifying Target Processor Mode}
+{\footnote browse:00119}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_5')");
EnableButton("btn_up")}
K{\footnote 16\'ADbit mode, versus 32\'ADbit mode;
BITS;
processor mode}
\keepn\f2\b\fs30\sb60\sa60
5.1. {\f1 BITS}: Specifying Target Processor Mode
\par\pard\plain\sb120
The {\f1 BITS} directive specifies whether NASM should generate code 
designed to run on a processor operating in 16-bit mode, or code designed 
to run on a processor operating in 32-bit mode. The syntax is 
{\f1 BITS\'A016} or {\f1 BITS\'A032}.
\par\sb120
In most cases, you should not need to use {\f1 BITS} explicitly. The 
{\f1 aout}, {\f1 coff}, {\f1 elf} and {\f1 win32} object formats, which are 
designed for use in 32-bit operating systems, all cause NASM to select 
32-bit mode by default. The {\f1 obj} object format allows you to specify 
each segment you define as either {\f1 USE16} or {\f1 USE32}, and NASM will 
set its operating mode accordingly, so the use of the {\f1 BITS} directive 
is once again unnecessary.
\par\sb120
The most likely reason for using the {\f1 BITS} directive is to write 
32-bit code in a flat binary file; this is because the {\f1 bin} output 
format defaults to 16-bit mode in anticipation of it being used most 
frequently to write DOS {\f1 .COM} programs, DOS {\f1 .SYS} device drivers 
and boot loader software.
\par\sb120
You do {\i not} need to specify {\f1 BITS\'A032} merely in order to use 
32-bit instructions in a 16-bit DOS program; if you do, the assembler will 
generate incorrect code because it will be writing code targeted at a 
32-bit platform, to be run on a 16-bit one.
\par\sb120
When NASM is in {\f1 BITS\'A016} state, instructions which use 32-bit data 
are prefixed with an 0x66 byte, and those referring to 32-bit addresses 
have an 0x67 prefix. In {\f1 BITS\'A032} state, the reverse is true: 32-bit 
instructions require no prefixes, whereas instructions using 16-bit data 
need an 0x66 and those working on 16-bit addresses need an 0x67.
\par\sb120
The {\f1 BITS} directive has an exactly equivalent primitive form, 
{\f1 [BITS\'A016]} and {\f1 [BITS\'A032]}. The user-level form is a macro 
which has no function other than to call the primitive form.
\par\sb120
Note that the space is neccessary, {\f1 BITS32} will {\i not} work!
\par\sb120
\li360\fi-360
{\uldb Section 5.1.1: USE16 & USE32: Aliases for BITS}{\v section_5_1_1}\par\sb0
\pard\sb120
\page
#{\footnote section_5_1_1}
${\footnote 5.1.1. USE16 & USE32: Aliases for BITS}
+{\footnote browse:00120}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_5_1')");
EnableButton("btn_up")}
K{\footnote USE16;
USE32}
\keepn\f2\b\fs30\sb60\sa60
5.1.1. {\f1 USE16} & {\f1 USE32}: Aliases for BITS
\par\pard\plain\sb120
The `{\f1 USE16}' and `{\f1 USE32}' directives can be used in place of 
`{\f1 BITS\'A016}' and `{\f1 BITS\'A032}', for compatibility with other 
assemblers.
\par\sb120
\page
#{\footnote section_5_2}
${\footnote 5.2. SECTION or SEGMENT: Changing and Defining Sections}
+{\footnote browse:00121}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_5')");
EnableButton("btn_up")}
K{\footnote changing sections;
defining sections;
SECTION;
SEGMENT;
standardised section names;
switching between sections}
\keepn\f2\b\fs30\sb60\sa60
5.2. {\f1 SECTION} or {\f1 SEGMENT}: Changing and Defining Sections
\par\pard\plain\sb120
The {\f1 SECTION} directive ({\f1 SEGMENT} is an exactly equivalent 
synonym) changes which section of the output file the code you write will 
be assembled into. In some object file formats, the number and names of 
sections are fixed; in others, the user may make up as many as they wish. 
Hence {\f1 SECTION} may sometimes give an error message, or may define a 
new section, if you try to switch to a section that does not (yet) exist.
\par\sb120
The Unix object formats, and the {\f1 bin} object format (but see 
{\uldb section 6.1.3}{\v section_6_1_3}, all support the standardised 
section names {\f1 .text}, {\f1 .data} and {\f1 .bss} for the code, data 
and uninitialised-data sections. The {\f1 obj} format, by contrast, does 
not recognise these section names as being special, and indeed will strip 
off the leading period of any section name that has one.
\par\sb120
\li360\fi-360
{\uldb Section 5.2.1: The __SECT__ Macro}{\v section_5_2_1}\par\sb0
\pard\sb120
\page
#{\footnote section_5_2_1}
${\footnote 5.2.1. The __SECT__ Macro}
+{\footnote browse:00122}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_5_2')");
EnableButton("btn_up")}
K{\footnote __SECT__}
\keepn\f2\b\fs30\sb60\sa60
5.2.1. The {\f1 __SECT__} Macro
\par\pard\plain\sb120
The {\f1 SECTION} directive is unusual in that its user-level form 
functions differently from its primitive form. The primitive form, 
{\f1 [SECTION\'A0xyz]}, simply switches the current target section to the 
one given. The user-level form, {\f1 SECTION\'A0xyz}, however, first 
defines the single-line macro {\f1 __SECT__} to be the primitive 
{\f1 [SECTION]} directive which it is about to issue, and then issues it. 
So the user-level directive
\par\sb120
\keep\f1\sb120
        SECTION .text\par\sb0
\pard\f0\sb120
expands to the two lines
\par\sb120
\keep\f1\sb120
%define __SECT__        [SECTION .text] \par\sb0
        [SECTION .text]\par\sb0
\pard\f0\sb120
Users may find it useful to make use of this in their own macros. For 
example, the {\f1 writefile} macro defined in {\uldb section 
4.3.3}{\v section_4_3_3} can be usefully rewritten in the following more 
sophisticated form:
\par\sb120
\keep\f1\sb120
%macro  writefile 2+ \par\sb0
\par\sb0
        [section .data] \par\sb0
\par\sb0
  %%str:        db      %2 \par\sb0
  %%endstr: \par\sb0
\par\sb0
        __SECT__ \par\sb0
\par\sb0
        mov     dx,%%str \par\sb0
        mov     cx,%%endstr-%%str \par\sb0
        mov     bx,%1 \par\sb0
        mov     ah,0x40 \par\sb0
        int     0x21 \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
This form of the macro, once passed a string to output, first switches 
temporarily to the data section of the file, using the primitive form of 
the {\f1 SECTION} directive so as not to modify {\f1 __SECT__}. It then 
declares its string in the data section, and then invokes {\f1 __SECT__} to 
switch back to {\i whichever} section the user was previously working in. 
It thus avoids the need, in the previous version of the macro, to include a 
{\f1 JMP} instruction to jump over the data, and also does not fail if, in 
a complicated {\f1 OBJ} format module, the user could potentially be 
assembling the code in any of several separate code sections.
\par\sb120
\page
#{\footnote section_5_3}
${\footnote 5.3. ABSOLUTE: Defining Absolute Labels}
+{\footnote browse:00123}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_5')");
EnableButton("btn_up")}
K{\footnote ABSOLUTE;
critical expression;
ENDSTRUC;
__SECT__;
STRUC}
\keepn\f2\b\fs30\sb60\sa60
5.3. {\f1 ABSOLUTE}: Defining Absolute Labels
\par\pard\plain\sb120
The {\f1 ABSOLUTE} directive can be thought of as an alternative form of 
{\f1 SECTION}: it causes the subsequent code to be directed at no physical 
section, but at the hypothetical section starting at the given absolute 
address. The only instructions you can use in this mode are the {\f1 RESB} 
family.
\par\sb120
{\f1 ABSOLUTE} is used as follows:
\par\sb120
\keep\f1\sb120
absolute 0x1A \par\sb0
\par\sb0
    kbuf_chr    resw    1 \par\sb0
    kbuf_free   resw    1 \par\sb0
    kbuf        resw    16\par\sb0
\pard\f0\sb120
This example describes a section of the PC BIOS data area, at segment 
address 0x40: the above code defines {\f1 kbuf_chr} to be 0x1A, 
{\f1 kbuf_free} to be 0x1C, and {\f1 kbuf} to be 0x1E.
\par\sb120
The user-level form of {\f1 ABSOLUTE}, like that of {\f1 SECTION}, 
redefines the {\f1 __SECT__} macro when it is invoked.
\par\sb120
{\f1 STRUC} and {\f1 ENDSTRUC} are defined as macros which use 
{\f1 ABSOLUTE} (and also {\f1 __SECT__}).
\par\sb120
{\f1 ABSOLUTE} doesn't have to take an absolute constant as an argument: it 
can take an expression (actually, a critical expression: see {\uldb section 
3.8}{\v section_3_8}) and it can be a value in a segment. For example, a 
TSR can re-use its setup code as run-time BSS like this:
\par\sb120
\keep\f1\sb120
        org     100h               ; it's a .COM program \par\sb0
\par\sb0
        jmp     setup              ; setup code comes last \par\sb0
\par\sb0
        ; the resident part of the TSR goes here \par\sb0
setup: \par\sb0
        ; now write the code that installs the TSR here \par\sb0
\par\sb0
absolute setup \par\sb0
\par\sb0
runtimevar1     resw    1 \par\sb0
runtimevar2     resd    20 \par\sb0
\par\sb0
tsr_end:\par\sb0
\pard\f0\sb120
This defines some variables `on top of' the setup code, so that after the 
setup has finished running, the space it took up can be re-used as data 
storage for the running TSR. The symbol `tsr_end' can be used to calculate 
the total size of the part of the TSR that needs to be made resident.
\par\sb120
\page
#{\footnote section_5_4}
${\footnote 5.4. EXTERN: Importing Symbols from Other Modules}
+{\footnote browse:00124}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_5')");
EnableButton("btn_up")}
K{\footnote EXTERN;
importing symbols}
\keepn\f2\b\fs30\sb60\sa60
5.4. {\f1 EXTERN}: Importing Symbols from Other Modules
\par\pard\plain\sb120
{\f1 EXTERN} is similar to the MASM directive {\f1 EXTRN} and the C keyword 
{\f1 extern}: it is used to declare a symbol which is not defined anywhere 
in the module being assembled, but is assumed to be defined in some other 
module and needs to be referred to by this one. Not every object-file 
format can support external variables: the {\f1 bin} format cannot.
\par\sb120
The {\f1 EXTERN} directive takes as many arguments as you like. Each 
argument is the name of a symbol:
\par\sb120
\keep\f1\sb120
extern  _printf \par\sb0
extern  _sscanf,_fscanf\par\sb0
\pard\f0\sb120
Some object-file formats provide extra features to the {\f1 EXTERN} 
directive. In all cases, the extra features are used by suffixing a colon 
to the symbol name followed by object-format specific text. For example, 
the {\f1 obj} format allows you to declare that the default segment base of 
an external should be the group {\f1 dgroup} by means of the directive
\par\sb120
\keep\f1\sb120
extern  _variable:wrt dgroup\par\sb0
\pard\f0\sb120
The primitive form of {\f1 EXTERN} differs from the user-level form only in 
that it can take only one argument at a time: the support for multiple 
arguments is implemented at the preprocessor level.
\par\sb120
You can declare the same variable as {\f1 EXTERN} more than once: NASM will 
quietly ignore the second and later redeclarations. You can't declare a 
variable as {\f1 EXTERN} as well as something else, though.
\par\sb120
\page
#{\footnote section_5_5}
${\footnote 5.5. GLOBAL: Exporting Symbols to Other Modules}
+{\footnote browse:00125}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_5')");
EnableButton("btn_up")}
K{\footnote exporting symbols;
GLOBAL;
PUBLIC}
\keepn\f2\b\fs30\sb60\sa60
5.5. {\f1 GLOBAL}: Exporting Symbols to Other Modules
\par\pard\plain\sb120
{\f1 GLOBAL} is the other end of {\f1 EXTERN}: if one module declares a 
symbol as {\f1 EXTERN} and refers to it, then in order to prevent linker 
errors, some other module must actually {\i define} the symbol and declare 
it as {\f1 GLOBAL}. Some assemblers use the name {\f1 PUBLIC} for this 
purpose.
\par\sb120
The {\f1 GLOBAL} directive applying to a symbol must appear {\i before} the 
definition of the symbol.
\par\sb120
{\f1 GLOBAL} uses the same syntax as {\f1 EXTERN}, except that it must 
refer to symbols which {\i are} defined in the same module as the 
{\f1 GLOBAL} directive. For example:
\par\sb120
\keep\f1\sb120
global _main \par\sb0
_main: \par\sb0
        ; some code\par\sb0
\pard\f0\sb120
{\f1 GLOBAL}, like {\f1 EXTERN}, allows object formats to define private 
extensions by means of a colon. The {\f1 elf} object format, for example, 
lets you specify whether global data items are functions or data:
\par\sb120
\keep\f1\sb120
global  hashlookup:function, hashtable:data\par\sb0
\pard\f0\sb120
Like {\f1 EXTERN}, the primitive form of {\f1 GLOBAL} differs from the 
user-level form only in that it can take only one argument at a time.
\par\sb120
\page
#{\footnote section_5_6}
${\footnote 5.6. COMMON: Defining Common Data Areas}
+{\footnote browse:00126}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_5')");
EnableButton("btn_up")}
K{\footnote COMMON;
common variables}
\keepn\f2\b\fs30\sb60\sa60
5.6. {\f1 COMMON}: Defining Common Data Areas
\par\pard\plain\sb120
The {\f1 COMMON} directive is used to declare {\i common variables}. A 
common variable is much like a global variable declared in the 
uninitialised data section, so that
\par\sb120
\keep\f1\sb120
common  intvar  4\par\sb0
\pard\f0\sb120
is similar in function to
\par\sb120
\keep\f1\sb120
global  intvar \par\sb0
section .bss \par\sb0
\par\sb0
intvar  resd    1\par\sb0
\pard\f0\sb120
The difference is that if more than one module defines the same common 
variable, then at link time those variables will be {\i merged}, and 
references to {\f1 intvar} in all modules will point at the same piece of 
memory.
\par\sb120
Like {\f1 GLOBAL} and {\f1 EXTERN}, {\f1 COMMON} supports object-format 
specific extensions. For example, the {\f1 obj} format allows common 
variables to be NEAR or FAR, and the {\f1 elf} format allows you to specify 
the alignment requirements of a common variable:
\par\sb120
\keep\f1\sb120
common  commvar  4:near  ; works in OBJ \par\sb0
common  intarray 100:4   ; works in ELF: 4 byte aligned\par\sb0
\pard\f0\sb120
Once again, like {\f1 EXTERN} and {\f1 GLOBAL}, the primitive form of 
{\f1 COMMON} differs from the user-level form only in that it can take only 
one argument at a time.
\par\sb120
\page
#{\footnote section_5_7}
${\footnote 5.7. CPU: Defining CPU Dependencies}
+{\footnote browse:00127}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_5')");
EnableButton("btn_up")}
K{\footnote CPU}
\keepn\f2\b\fs30\sb60\sa60
5.7. {\f1 CPU}: Defining CPU Dependencies
\par\pard\plain\sb120
The {\f1 CPU} directive restricts assembly to those instructions which are 
available on the specified CPU.
\par\sb120
Options are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A08086} Assemble only 8086 instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0186} Assemble instructions up to the 80186 instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0286} Assemble instructions up to the 286 instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0386} Assemble instructions up to the 386 instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0486} 486 instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0586} Pentium instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0PENTIUM} Same as 586
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0686} P6 instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0PPRO} Same as 686
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0P2} Same as 686
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0P3} Pentium III (Katmai) instruction sets
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0KATMAI} Same as P3
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0P4} Pentium 4 (Willamette) instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0WILLAMETTE} Same as P4
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0PRESCOTT} Prescott instruction set
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CPU\'A0IA64} IA64 CPU (in x86 mode) instruction set
\par\pard\sb120
All options are case insensitive. All instructions will be selected only if 
they apply to the selected CPU or lower. By default, all instructions are 
available.
\par\sb120
\page
#{\footnote chapter_6}
${\footnote Chapter 6: Output Formats}
+{\footnote browse:00128}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
K{\footnote command\'ADline;
default name;
extension;
\'ADf option;
output formats}
\keepn\f2\b\fs30\sb60\sa60
Chapter 6: Output Formats
\par\pard\plain\sb120
NASM is a portable assembler, designed to be able to compile on any ANSI 
C-supporting platform and produce output to run on a variety of Intel x86 
operating systems. For this reason, it has a large number of available 
output formats, selected using the {\f1 \'ADf} option on the NASM command 
line. Each of these formats, along with its extensions to the base NASM 
syntax, is detailed in this chapter.
\par\sb120
As stated in {\uldb section 2.1.1}{\v section_2_1_1}, NASM chooses a 
default name for your output file based on the input file name and the 
chosen output format. This will be generated by removing the extension 
({\f1 .asm}, {\f1 .s}, or whatever you like to use) from the input file 
name, and substituting an extension defined by the output format. The 
extensions are given with each format below.
\par\sb120
\li360\fi-360
{\uldb Section 6.1: bin: Flat\'ADForm Binary Output}{\v section_6_1}\par\sb0
{\uldb Section 6.2: obj: Microsoft OMF Object Files}{\v section_6_2}\par\sb0
{\uldb Section 6.3: win32: Microsoft Win32 Object Files}{\v section_6_3}\par\sb0
{\uldb Section 6.4: coff: Common Object File Format}{\v section_6_4}\par\sb0
{\uldb Section 6.5: elf: Executable and Linkable Format Object Files}{\v section_6_5}\par\sb0
{\uldb Section 6.6: aout: Linux a.out Object Files}{\v section_6_6}\par\sb0
{\uldb Section 6.7: aoutb: NetBSD/FreeBSD/OpenBSD a.out Object Files}{\v section_6_7}\par\sb0
{\uldb Section 6.8: as86: Minix/Linux as86 Object Files}{\v section_6_8}\par\sb0
{\uldb Section 6.9: rdf: Relocatable Dynamic Object File Format}{\v section_6_9}\par\sb0
{\uldb Section 6.10: dbg: Debugging Format}{\v section_6_10}\par\sb0
\pard\sb120
\page
#{\footnote section_6_1}
${\footnote 6.1. bin: Flat\'ADForm Binary Output}
+{\footnote browse:00129}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote bin;
BITS;
boot loader;
.COM;
flat\'ADform binary;
MS-DOS;
multiple section names;
operating system;
pure binary;
.SYS}
\keepn\f2\b\fs30\sb60\sa60
6.1. {\f1 bin}: Flat\'ADForm Binary Output
\par\pard\plain\sb120
The {\f1 bin} format does not produce object files: it generates nothing in 
the output file except the code you wrote. Such `pure binary' files are 
used by MS\'ADDOS: {\f1 .COM} executables and {\f1 .SYS} device drivers are 
pure binary files. Pure binary output is also useful for operating system 
and boot loader development.
\par\sb120
The {\f1 bin} format supports multiple section names. For details of how 
nasm handles sections in the {\f1 bin} format, see {\uldb section 
6.1.3}{\v section_6_1_3}.
\par\sb120
Using the {\f1 bin} format puts NASM by default into 16-bit mode (see 
{\uldb section 5.1}{\v section_5_1}). In order to use {\f1 bin} to write 
32-bit code such as an OS kernel, you need to explicitly issue the 
{\f1 BITS\'A032} directive.
\par\sb120
{\f1 bin} has no default output file name extension: instead, it leaves 
your file name as it is once the original extension has been removed. Thus, 
the default is for NASM to assemble {\f1 binprog.asm} into a binary file 
called {\f1 binprog}.
\par\sb120
\li360\fi-360
{\uldb Section 6.1.1: ORG: Binary File Program Origin}{\v section_6_1_1}\par\sb0
{\uldb Section 6.1.2: bin Extensions to the SECTION Directive}{\v section_6_1_2}\par\sb0
{\uldb Section 6.1.3: Multisection support for the BIN format.}{\v section_6_1_3}\par\sb0
{\uldb Section 6.1.4: Map files}{\v section_6_1_4}\par\sb0
\pard\sb120
\page
#{\footnote section_6_1_1}
${\footnote 6.1.1. ORG: Binary File Program Origin}
+{\footnote browse:00130}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_1')");
EnableButton("btn_up")}
K{\footnote ORG;
program origin}
\keepn\f2\b\fs30\sb60\sa60
6.1.1. {\f1 ORG}: Binary File Program Origin
\par\pard\plain\sb120
The {\f1 bin} format provides an additional directive to the list given in 
{\uldb chapter 5}{\v chapter_5}: {\f1 ORG}. The function of the {\f1 ORG} 
directive is to specify the origin address which NASM will assume the 
program begins at when it is loaded into memory.
\par\sb120
For example, the following code will generate the longword 
{\f1 0x00000104}:
\par\sb120
\keep\f1\sb120
        org     0x100 \par\sb0
        dd      label \par\sb0
label:\par\sb0
\pard\f0\sb120
Unlike the {\f1 ORG} directive provided by MASM-compatible assemblers, 
which allows you to jump around in the object file and overwrite code you 
have already generated, NASM's {\f1 ORG} does exactly what the directive 
says: {\i origin}. Its sole function is to specify one offset which is 
added to all internal address references within the section; it does not 
permit any of the trickery that MASM's version does. See {\uldb section 
10.1.3}{\v section_10_1_3} for further comments.
\par\sb120
\page
#{\footnote section_6_1_2}
${\footnote 6.1.2. bin Extensions to the SECTION Directive}
+{\footnote browse:00131}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_1')");
EnableButton("btn_up")}
K{\footnote ALIGN;
alignment, in bin sections;
section alignment, in bin;
section, bin extensions to;
segment alignment, in bin}
\keepn\f2\b\fs30\sb60\sa60
6.1.2. {\f1 bin} Extensions to the {\f1 SECTION} Directive
\par\pard\plain\sb120
The {\f1 bin} output format extends the {\f1 SECTION} (or {\f1 SEGMENT}) 
directive to allow you to specify the alignment requirements of segments. 
This is done by appending the {\f1 ALIGN} qualifier to the end of the 
section-definition line. For example,
\par\sb120
\keep\f1\sb120
section .data   align=16\par\sb0
\pard\f0\sb120
switches to the section {\f1 .data} and also specifies that it must be 
aligned on a 16-byte boundary.
\par\sb120
The parameter to {\f1 ALIGN} specifies how many low bits of the section 
start address must be forced to zero. The alignment value given may be any 
power of two.
\par\sb120
\page
#{\footnote section_6_1_3}
${\footnote 6.1.3. Multisection support for the BIN format.}
+{\footnote browse:00132}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_1')");
EnableButton("btn_up")}
K{\footnote bin, multisection;
follows=;
Multisection;
nobits;
progbits;
start=;
vfollows=;
vstart=}
\keepn\f2\b\fs30\sb60\sa60
6.1.3. {\f1 Multisection} support for the BIN format.
\par\pard\plain\sb120
The {\f1 bin} format allows the use of multiple sections, of arbitrary 
names, besides the "known" {\f1 .text}, {\f1 .data}, and {\f1 .bss} names.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Sections may be designated {\f1 progbits} or {\f1 nobits}. Default is 
{\f1 progbits} (except {\f1 .bss}, which defaults to {\f1 nobits}, of 
course).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Sections can be aligned at a specified boundary following the previous 
section with {\f1 align=}, or at an arbitrary byte-granular position with 
{\f1 start=}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Sections can be given a virtual start address, which will be used for the 
calculation of all memory references within that section with 
{\f1 vstart=}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Sections can be ordered using {\f1 follows=}{\f1 <section>} or 
{\f1 vfollows=}{\f1 <section>} as an alternative to specifying an explicit 
start address.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Arguments to {\f1 org}, {\f1 start}, {\f1 vstart}, and {\f1 align=} are 
critical expressions. See {\uldb section 3.8}{\v section_3_8}. E.g. 
{\f1 align=(1\'A0<<\'A0ALIGN_SHIFT)} \'96 {\f1 ALIGN_SHIFT} must be defined 
before it is used here.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Any code which comes before an explicit {\f1 SECTION} directive is directed 
by default into the {\f1 .text} section.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If an {\f1 ORG} statement is not given, {\f1 ORG\'A00} is used by default.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 .bss} section will be placed after the last {\f1 progbits} 
section, unless {\f1 start=}, {\f1 vstart=}, {\f1 follows=}, or 
{\f1 vfollows=} has been specified.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
All sections are aligned on dword boundaries, unless a different alignment 
has been specified.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Sections may not overlap.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Nasm creates the {\f1 section.<secname>.start} for each section, which may 
be used in your code.
\par\pard\sb120
\page
#{\footnote section_6_1_4}
${\footnote 6.1.4. Map files}
+{\footnote browse:00133}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_1')");
EnableButton("btn_up")}
K{\footnote map files}
\keepn\f2\b\fs30\sb60\sa60
6.1.4. Map files
\par\pard\plain\sb120
Map files can be generated in {\f1 \'ADf\'A0bin} format by means of the 
{\f1 [map]} option. Map types of {\f1 all} (default), {\f1 brief}, 
{\f1 sections}, {\f1 segments}, or {\f1 symbols} may be specified. Output 
may be directed to {\f1 stdout} (default), {\f1 stderr}, or a specified 
file. E.g. {\f1 [map\'A0symbols\'A0myfile.map]}. No "user form" exists, the 
square brackets must be used.
\par\sb120
\page
#{\footnote section_6_2}
${\footnote 6.2. obj: Microsoft OMF Object Files}
+{\footnote browse:00134}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote Borland, Win32 compilers;
.EXE;
MASM;
Microsoft OMF;
__NASMDEFSEG;
obj;
OMF;
OS/2;
SEG;
tasm;
Win32;
WRT}
\keepn\f2\b\fs30\sb60\sa60
6.2. {\f1 obj}: Microsoft OMF Object Files
\par\pard\plain\sb120
The {\f1 obj} file format (NASM calls it {\f1 obj} rather than {\f1 omf} 
for historical reasons) is the one produced by MASM and TASM, which is 
typically fed to 16-bit DOS linkers to produce {\f1 .EXE} files. It is also 
the format used by OS/2.
\par\sb120
{\f1 obj} provides a default output file-name extension of {\f1 .obj}.
\par\sb120
{\f1 obj} is not exclusively a 16-bit format, though: NASM has full support 
for the 32-bit extensions to the format. In particular, 32-bit {\f1 obj} 
format files are used by Borland's Win32 compilers, instead of using 
Microsoft's newer {\f1 win32} object file format.
\par\sb120
The {\f1 obj} format does not define any special segment names: you can 
call your segments anything you like. Typical names for segments in 
{\f1 obj} format files are {\f1 CODE}, {\f1 DATA} and {\f1 BSS}.
\par\sb120
If your source file contains code before specifying an explicit 
{\f1 SEGMENT} directive, then NASM will invent its own segment called 
{\f1 __NASMDEFSEG} for you.
\par\sb120
When you define a segment in an {\f1 obj} file, NASM defines the segment 
name as a symbol as well, so that you can access the segment address of the 
segment. So, for example:
\par\sb120
\keep\f1\sb120
segment data \par\sb0
\par\sb0
dvar:   dw      1234 \par\sb0
\par\sb0
segment code \par\sb0
\par\sb0
function: \par\sb0
        mov     ax,data         ; get segment address of data \par\sb0
        mov     ds,ax           ; and move it into DS \par\sb0
        inc     word [dvar]     ; now this reference will work \par\sb0
        ret\par\sb0
\pard\f0\sb120
The {\f1 obj} format also enables the use of the {\f1 SEG} and {\f1 WRT} 
operators, so that you can write code which does things like
\par\sb120
\keep\f1\sb120
extern  foo \par\sb0
\par\sb0
      mov   ax,seg foo            ; get preferred segment of foo \par\sb0
      mov   ds,ax \par\sb0
      mov   ax,data               ; a different segment \par\sb0
      mov   es,ax \par\sb0
      mov   ax,[ds:foo]           ; this accesses `foo' \par\sb0
      mov   [es:foo wrt data],bx  ; so does this\par\sb0
\pard\f0\sb120
\li360\fi-360
{\uldb Section 6.2.1: obj Extensions to the SEGMENT Directive}{\v section_6_2_1}\par\sb0
{\uldb Section 6.2.2: GROUP: Defining Groups of Segments}{\v section_6_2_2}\par\sb0
{\uldb Section 6.2.3: UPPERCASE: Disabling Case Sensitivity in Output}{\v section_6_2_3}\par\sb0
{\uldb Section 6.2.4: IMPORT: Importing DLL Symbols}{\v section_6_2_4}\par\sb0
{\uldb Section 6.2.5: EXPORT: Exporting DLL Symbols}{\v section_6_2_5}\par\sb0
{\uldb Section 6.2.6: ..start: Defining the Program Entry Point}{\v section_6_2_6}\par\sb0
{\uldb Section 6.2.7: obj Extensions to the EXTERN Directive}{\v section_6_2_7}\par\sb0
{\uldb Section 6.2.8: obj Extensions to the COMMON Directive}{\v section_6_2_8}\par\sb0
\pard\sb120
\page
#{\footnote section_6_2_1}
${\footnote 6.2.1. obj Extensions to the SEGMENT Directive}
+{\footnote browse:00135}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_2')");
EnableButton("btn_up")}
K{\footnote ABSOLUTE;
ALIGN;
alignment, in obj sections;
CLASS;
COMMON;
FLAT;
OS/2;
OVERLAY;
PharLap;
PRIVATE;
PUBLIC;
section alignment, in obj;
SEGMENT, elf extensions to;
segment alignment, in obj;
STACK;
USE16;
USE32}
\keepn\f2\b\fs30\sb60\sa60
6.2.1. {\f1 obj} Extensions to the {\f1 SEGMENT} Directive
\par\pard\plain\sb120
The {\f1 obj} output format extends the {\f1 SEGMENT} (or {\f1 SECTION}) 
directive to allow you to specify various properties of the segment you are 
defining. This is done by appending extra qualifiers to the end of the 
segment-definition line. For example,
\par\sb120
\keep\f1\sb120
segment code private align=16\par\sb0
\pard\f0\sb120
defines the segment {\f1 code}, but also declares it to be a private 
segment, and requires that the portion of it described in this code module 
must be aligned on a 16-byte boundary.
\par\sb120
The available qualifiers are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PRIVATE}, {\f1 PUBLIC}, {\f1 COMMON} and {\f1 STACK} specify the 
combination characteristics of the segment. {\f1 PRIVATE} segments do not 
get combined with any others by the linker; {\f1 PUBLIC} and {\f1 STACK} 
segments get concatenated together at link time; and {\f1 COMMON} segments 
all get overlaid on top of each other rather than stuck end-to-end.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 ALIGN} is used, as shown above, to specify how many low bits of the 
segment start address must be forced to zero. The alignment value given may 
be any power of two from 1 to 4096; in reality, the only values supported 
are 1, 2, 4, 16, 256 and 4096, so if 8 is specified it will be rounded up 
to 16, and 32, 64 and 128 will all be rounded up to 256, and so on. Note 
that alignment to 4096-byte boundaries is a PharLap extension to the format 
and may not be supported by all linkers.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CLASS} can be used to specify the segment class; this feature 
indicates to the linker that segments of the same class should be placed 
near each other in the output file. The class name can be any word, e.g. 
{\f1 CLASS=CODE}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 OVERLAY}, like {\f1 CLASS}, is specified with an arbitrary word as an 
argument, and provides overlay information to an overlay-capable linker.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Segments can be declared as {\f1 USE16} or {\f1 USE32}, which has the 
effect of recording the choice in the object file and also ensuring that 
NASM's default assembly mode when assembling in that segment is 16-bit or 
32-bit respectively.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
When writing OS/2 object files, you should declare 32-bit segments as 
{\f1 FLAT}, which causes the default segment base for anything in the 
segment to be the special group {\f1 FLAT}, and also defines the group if 
it is not already defined.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 obj} file format also allows segments to be declared as having a 
pre-defined absolute segment address, although no linkers are currently 
known to make sensible use of this feature; nevertheless, NASM allows you 
to declare a segment such as {\f1 SEGMENT\'A0SCREEN\'A0ABSOLUTE=0xB800} if 
you need to. The {\f1 ABSOLUTE} and {\f1 ALIGN} keywords are mutually 
exclusive.
\par\pard\sb120
NASM's default segment attributes are {\f1 PUBLIC}, {\f1 ALIGN=1}, no 
class, no overlay, and {\f1 USE16}.
\par\sb120
\page
#{\footnote section_6_2_2}
${\footnote 6.2.2. GROUP: Defining Groups of Segments}
+{\footnote browse:00136}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_2')");
EnableButton("btn_up")}
K{\footnote GROUP;
segments, groups of}
\keepn\f2\b\fs30\sb60\sa60
6.2.2. {\f1 GROUP}: Defining Groups of Segments
\par\pard\plain\sb120
The {\f1 obj} format also allows segments to be grouped, so that a single 
segment register can be used to refer to all the segments in a group. NASM 
therefore supplies the {\f1 GROUP} directive, whereby you can code
\par\sb120
\keep\f1\sb120
segment data \par\sb0
\par\sb0
        ; some data \par\sb0
\par\sb0
segment bss \par\sb0
\par\sb0
        ; some uninitialised data \par\sb0
\par\sb0
group dgroup data bss\par\sb0
\pard\f0\sb120
which will define a group called {\f1 dgroup} to contain the segments 
{\f1 data} and {\f1 bss}. Like {\f1 SEGMENT}, {\f1 GROUP} causes the group 
name to be defined as a symbol, so that you can refer to a variable 
{\f1 var} in the {\f1 data} segment as {\f1 var\'A0wrt\'A0data} or as 
{\f1 var\'A0wrt\'A0dgroup}, depending on which segment value is currently 
in your segment register.
\par\sb120
If you just refer to {\f1 var}, however, and {\f1 var} is declared in a 
segment which is part of a group, then NASM will default to giving you the 
offset of {\f1 var} from the beginning of the {\i group}, not the 
{\i segment}. Therefore {\f1 SEG\'A0var}, also, will return the group base 
rather than the segment base.
\par\sb120
NASM will allow a segment to be part of more than one group, but will 
generate a warning if you do this. Variables declared in a segment which is 
part of more than one group will default to being relative to the first 
group that was defined to contain the segment.
\par\sb120
A group does not have to contain any segments; you can still make {\f1 WRT} 
references to a group which does not contain the variable you are referring 
to. OS/2, for example, defines the special group {\f1 FLAT} with no 
segments in it.
\par\sb120
\page
#{\footnote section_6_2_3}
${\footnote 6.2.3. UPPERCASE: Disabling Case Sensitivity in Output}
+{\footnote browse:00137}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_2')");
EnableButton("btn_up")}
K{\footnote case sensitivity;
UPPERCASE}
\keepn\f2\b\fs30\sb60\sa60
6.2.3. {\f1 UPPERCASE}: Disabling Case Sensitivity in Output
\par\pard\plain\sb120
Although NASM itself is case sensitive, some OMF linkers are not; therefore 
it can be useful for NASM to output single-case object files. The 
{\f1 UPPERCASE} format-specific directive causes all segment, group and 
symbol names that are written to the object file to be forced to upper case 
just before being written. Within a source file, NASM is still 
case-sensitive; but the object file can be written entirely in upper case 
if desired.
\par\sb120
{\f1 UPPERCASE} is used alone on a line; it requires no parameters.
\par\sb120
\page
#{\footnote section_6_2_4}
${\footnote 6.2.4. IMPORT: Importing DLL Symbols}
+{\footnote browse:00138}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_2')");
EnableButton("btn_up")}
K{\footnote DLL symbols, importing;
IMPORT;
import library;
symbols, importing from DLLs}
\keepn\f2\b\fs30\sb60\sa60
6.2.4. {\f1 IMPORT}: Importing DLL Symbols
\par\pard\plain\sb120
The {\f1 IMPORT} format-specific directive defines a symbol to be imported 
from a DLL, for use if you are writing a DLL's import library in NASM. You 
still need to declare the symbol as {\f1 EXTERN} as well as using the 
{\f1 IMPORT} directive.
\par\sb120
The {\f1 IMPORT} directive takes two required parameters, separated by 
white space, which are (respectively) the name of the symbol you wish to 
import and the name of the library you wish to import it from. For example:
\par\sb120
\keep\f1\sb120
    import  WSAStartup wsock32.dll\par\sb0
\pard\f0\sb120
A third optional parameter gives the name by which the symbol is known in 
the library you are importing it from, in case this is not the same as the 
name you wish the symbol to be known by to your code once you have imported 
it. For example:
\par\sb120
\keep\f1\sb120
    import  asyncsel wsock32.dll WSAAsyncSelect\par\sb0
\pard\f0\sb120
\page
#{\footnote section_6_2_5}
${\footnote 6.2.5. EXPORT: Exporting DLL Symbols}
+{\footnote browse:00139}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_2')");
EnableButton("btn_up")}
K{\footnote DLL symbols, exporting;
EXPORT;
symbols, exporting from DLLs}
\keepn\f2\b\fs30\sb60\sa60
6.2.5. {\f1 EXPORT}: Exporting DLL Symbols
\par\pard\plain\sb120
The {\f1 EXPORT} format-specific directive defines a global symbol to be 
exported as a DLL symbol, for use if you are writing a DLL in NASM. You 
still need to declare the symbol as {\f1 GLOBAL} as well as using the 
{\f1 EXPORT} directive.
\par\sb120
{\f1 EXPORT} takes one required parameter, which is the name of the symbol 
you wish to export, as it was defined in your source file. An optional 
second parameter (separated by white space from the first) gives the 
{\i external} name of the symbol: the name by which you wish the symbol to 
be known to programs using the DLL. If this name is the same as the 
internal name, you may leave the second parameter off.
\par\sb120
Further parameters can be given to define attributes of the exported 
symbol. These parameters, like the second, are separated by white space. If 
further parameters are given, the external name must also be specified, 
even if it is the same as the internal name. The available attributes are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 resident} indicates that the exported name is to be kept resident by 
the system loader. This is an optimisation for frequently used symbols 
imported by name.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 nodata} indicates that the exported symbol is a function which does 
not make use of any initialised data.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 parm=NNN}, where {\f1 NNN} is an integer, sets the number of parameter 
words for the case in which the symbol is a call gate between 32-bit and 
16-bit segments.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
An attribute which is just a number indicates that the symbol should be 
exported with an identifying number (ordinal), and gives the desired 
number.
\par\pard\sb120
For example:
\par\sb120
\keep\f1\sb120
    export  myfunc \par\sb0
    export  myfunc TheRealMoreFormalLookingFunctionName \par\sb0
    export  myfunc myfunc 1234  ; export by ordinal \par\sb0
    export  myfunc myfunc resident parm=23 nodata\par\sb0
\pard\f0\sb120
\page
#{\footnote section_6_2_6}
${\footnote 6.2.6. ..start: Defining the Program Entry Point}
+{\footnote browse:00140}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_2')");
EnableButton("btn_up")}
K{\footnote program entry point;
..start}
\keepn\f2\b\fs30\sb60\sa60
6.2.6. {\f1 ..start}: Defining the Program Entry Point
\par\pard\plain\sb120
{\f1 OMF} linkers require exactly one of the object files being linked to 
define the program entry point, where execution will begin when the program 
is run. If the object file that defines the entry point is assembled using 
NASM, you specify the entry point by declaring the special symbol 
{\f1 ..start} at the point where you wish execution to begin.
\par\sb120
\page
#{\footnote section_6_2_7}
${\footnote 6.2.7. obj Extensions to the EXTERN Directive}
+{\footnote browse:00141}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_2')");
EnableButton("btn_up")}
K{\footnote default-WRT mechanism;
EXTERN, obj extensions to}
\keepn\f2\b\fs30\sb60\sa60
6.2.7. {\f1 obj} Extensions to the {\f1 EXTERN} Directive
\par\pard\plain\sb120
If you declare an external symbol with the directive
\par\sb120
\keep\f1\sb120
    extern  foo\par\sb0
\pard\f0\sb120
then references such as {\f1 mov\'A0ax,foo} will give you the offset of 
{\f1 foo} from its preferred segment base (as specified in whichever module 
{\f1 foo} is actually defined in). So to access the contents of {\f1 foo} 
you will usually need to do something like
\par\sb120
\keep\f1\sb120
        mov     ax,seg foo      ; get preferred segment base \par\sb0
        mov     es,ax           ; move it into ES \par\sb0
        mov     ax,[es:foo]     ; and use offset `foo' from it\par\sb0
\pard\f0\sb120
This is a little unwieldy, particularly if you know that an external is 
going to be accessible from a given segment or group, say {\f1 dgroup}. So 
if {\f1 DS} already contained {\f1 dgroup}, you could simply code
\par\sb120
\keep\f1\sb120
        mov     ax,[foo wrt dgroup]\par\sb0
\pard\f0\sb120
However, having to type this every time you want to access {\f1 foo} can be 
a pain; so NASM allows you to declare {\f1 foo} in the alternative form
\par\sb120
\keep\f1\sb120
    extern  foo:wrt dgroup\par\sb0
\pard\f0\sb120
This form causes NASM to pretend that the preferred segment base of 
{\f1 foo} is in fact {\f1 dgroup}; so the expression {\f1 seg\'A0foo} will 
now return {\f1 dgroup}, and the expression {\f1 foo} is equivalent to 
{\f1 foo\'A0wrt\'A0dgroup}.
\par\sb120
This default-{\f1 WRT} mechanism can be used to make externals appear to be 
relative to any group or segment in your program. It can also be applied to 
common variables: see {\uldb section 6.2.8}{\v section_6_2_8}.
\par\sb120
\page
#{\footnote section_6_2_8}
${\footnote 6.2.8. obj Extensions to the COMMON Directive}
+{\footnote browse:00142}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_2')");
EnableButton("btn_up")}
K{\footnote COMMON, obj extensions to;
common variables, element size;
element size, in common variables;
far common variables;
near common variables}
\keepn\f2\b\fs30\sb60\sa60
6.2.8. {\f1 obj} Extensions to the {\f1 COMMON} Directive
\par\pard\plain\sb120
The {\f1 obj} format allows common variables to be either near or far; NASM 
allows you to specify which your variables should be by the use of the 
syntax
\par\sb120
\keep\f1\sb120
common  nearvar 2:near   ; `nearvar' is a near common \par\sb0
common  farvar  10:far   ; and `farvar' is far\par\sb0
\pard\f0\sb120
Far common variables may be greater in size than 64Kb, and so the OMF 
specification says that they are declared as a number of {\i elements} of a 
given size. So a 10-byte far common variable could be declared as ten 
one-byte elements, five two-byte elements, two five-byte elements or one 
ten-byte element.
\par\sb120
Some {\f1 OMF} linkers require the element size, as well as the variable 
size, to match when resolving common variables declared in more than one 
module. Therefore NASM must allow you to specify the element size on your 
far common variables. This is done by the following syntax:
\par\sb120
\keep\f1\sb120
common  c_5by2  10:far 5        ; two five-byte elements \par\sb0
common  c_2by5  10:far 2        ; five two-byte elements\par\sb0
\pard\f0\sb120
If no element size is specified, the default is 1. Also, the {\f1 FAR} 
keyword is not required when an element size is specified, since only far 
commons may have element sizes at all. So the above declarations could 
equivalently be
\par\sb120
\keep\f1\sb120
common  c_5by2  10:5            ; two five-byte elements \par\sb0
common  c_2by5  10:2            ; five two-byte elements\par\sb0
\pard\f0\sb120
In addition to these extensions, the {\f1 COMMON} directive in {\f1 obj} 
also supports default-{\f1 WRT} specification like {\f1 EXTERN} does 
(explained in {\uldb section 6.2.7}{\v section_6_2_7}). So you can also 
declare things like
\par\sb120
\keep\f1\sb120
common  foo     10:wrt dgroup \par\sb0
common  bar     16:far 2:wrt data \par\sb0
common  baz     24:wrt data:6\par\sb0
\pard\f0\sb120
\page
#{\footnote section_6_3}
${\footnote 6.3. win32: Microsoft Win32 Object Files}
+{\footnote browse:00143}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote Visual C++;
Win32}
\keepn\f2\b\fs30\sb60\sa60
6.3. {\f1 win32}: Microsoft Win32 Object Files
\par\pard\plain\sb120
The {\f1 win32} output format generates Microsoft Win32 object files, 
suitable for passing to Microsoft linkers such as Visual C++. Note that 
Borland Win32 compilers do not use this format, but use {\f1 obj} instead 
(see {\uldb section 6.2}{\v section_6_2}).
\par\sb120
{\f1 win32} provides a default output file-name extension of {\f1 .obj}.
\par\sb120
Note that although Microsoft say that Win32 object files follow the 
{\f1 COFF} (Common Object File Format) standard, the object files produced 
by Microsoft Win32 compilers are not compatible with COFF linkers such as 
DJGPP's, and vice versa. This is due to a difference of opinion over the 
precise semantics of PC-relative relocations. To produce COFF files 
suitable for DJGPP, use NASM's {\f1 coff} output format; conversely, the 
{\f1 coff} format does not produce object files that Win32 linkers can 
generate correct output from.
\par\sb120
\li360\fi-360
{\uldb Section 6.3.1: win32 Extensions to the SECTION Directive}{\v section_6_3_1}\par\sb0
\pard\sb120
\page
#{\footnote section_6_3_1}
${\footnote 6.3.1. win32 Extensions to the SECTION Directive}
+{\footnote browse:00144}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_3')");
EnableButton("btn_up")}
K{\footnote alignment, in win32 sections;
.drectve;
informational section;
SECTION, win32 extensions to;
section alignment, in win32;
standardised section names}
\keepn\f2\b\fs30\sb60\sa60
6.3.1. {\f1 win32} Extensions to the {\f1 SECTION} Directive
\par\pard\plain\sb120
Like the {\f1 obj} format, {\f1 win32} allows you to specify additional 
information on the {\f1 SECTION} directive line, to control the type and 
properties of sections you declare. Section types and properties are 
generated automatically by NASM for the standard section names {\f1 .text}, 
{\f1 .data} and {\f1 .bss}, but may still be overridden by these 
qualifiers.
\par\sb120
The available qualifiers are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 code}, or equivalently {\f1 text}, defines the section to be a code 
section. This marks the section as readable and executable, but not 
writable, and also indicates to the linker that the type of the section is 
code.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 data} and {\f1 bss} define the section to be a data section, 
analogously to {\f1 code}. Data sections are marked as readable and 
writable, but not executable. {\f1 data} declares an initialised data 
section, whereas {\f1 bss} declares an uninitialised data section.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 rdata} declares an initialised data section that is readable but not 
writable. Microsoft compilers use this section to place constants in it.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 info} defines the section to be an informational section, which is not 
included in the executable file by the linker, but may (for example) pass 
information {\i to} the linker. For example, declaring an 
{\f1 info}\'96type section called {\f1 .drectve} causes the linker to 
interpret the contents of the section as command-line options.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 align=}, used with a trailing number as in {\f1 obj}, gives the 
alignment requirements of the section. The maximum you may specify is 64: 
the Win32 object file format contains no means to request a greater section 
alignment than this. If alignment is not explicitly specified, the defaults 
are 16-byte alignment for code sections, 8-byte alignment for rdata 
sections and 4-byte alignment for data (and BSS) sections. Informational 
sections get a default alignment of 1 byte (no alignment), though the value 
does not matter.
\par\pard\sb120
The defaults assumed by NASM if you do not specify the above qualifiers 
are:
\par\sb120
\keep\f1\sb120
section .text    code  align=16 \par\sb0
section .data    data  align=4 \par\sb0
section .rdata   rdata align=8 \par\sb0
section .bss     bss   align=4\par\sb0
\pard\f0\sb120
Any other section name is treated by default like {\f1 .text}.
\par\sb120
\page
#{\footnote section_6_4}
${\footnote 6.4. coff: Common Object File Format}
+{\footnote browse:00145}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote coff;
Common Object File Format;
DJGPP}
\keepn\f2\b\fs30\sb60\sa60
6.4. {\f1 coff}: Common Object File Format
\par\pard\plain\sb120
The {\f1 coff} output type produces {\f1 COFF} object files suitable for 
linking with the DJGPP linker.
\par\sb120
{\f1 coff} provides a default output file-name extension of {\f1 .o}.
\par\sb120
The {\f1 coff} format supports the same extensions to the {\f1 SECTION} 
directive as {\f1 win32} does, except that the {\f1 align} qualifier and 
the {\f1 info} section type are not supported.
\par\sb120
\page
#{\footnote section_6_5}
${\footnote 6.5. elf: Executable and Linkable Format Object Files}
+{\footnote browse:00146}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote ELF;
Executable and Linkable Format;
Linux, ELF;
Solaris x86;
Unix, SCO;
Unix, System V;
UnixWare}
\keepn\f2\b\fs30\sb60\sa60
6.5. {\f1 elf}: Executable and Linkable Format Object Files
\par\pard\plain\sb120
The {\f1 elf} output format generates {\f1 ELF32} (Executable and Linkable 
Format) object files, as used by Linux as well as Unix System V, including 
Solaris x86, UnixWare and SCO Unix. {\f1 elf} provides a default output 
file-name extension of {\f1 .o}.
\par\sb120
\li360\fi-360
{\uldb Section 6.5.1: elf Extensions to the SECTION Directive}{\v section_6_5_1}\par\sb0
{\uldb Section 6.5.2: Position\'ADIndependent Code: elf Special Symbols and WRT}{\v section_6_5_2}\par\sb0
{\uldb Section 6.5.3: elf Extensions to the GLOBAL Directive}{\v section_6_5_3}\par\sb0
{\uldb Section 6.5.4: elf Extensions to the COMMON Directive }{\v section_6_5_4}\par\sb0
{\uldb Section 6.5.5: 16-bit code and ELF }{\v section_6_5_5}\par\sb0
\pard\sb120
\page
#{\footnote section_6_5_1}
${\footnote 6.5.1. elf Extensions to the SECTION Directive}
+{\footnote browse:00147}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_5')");
EnableButton("btn_up")}
K{\footnote alignment, in elf sections;
alloc;
.bss;
.data;
exec;
noalloc;
nobits;
noexec;
nowrite;
progbits;
SECTION, elf extensions to;
section alignment, in elf;
standardised section names;
.text;
write}
\keepn\f2\b\fs30\sb60\sa60
6.5.1. {\f1 elf} Extensions to the {\f1 SECTION} Directive
\par\pard\plain\sb120
Like the {\f1 obj} format, {\f1 elf} allows you to specify additional 
information on the {\f1 SECTION} directive line, to control the type and 
properties of sections you declare. Section types and properties are 
generated automatically by NASM for the standard section names {\f1 .text}, 
{\f1 .data} and {\f1 .bss}, but may still be overridden by these 
qualifiers.
\par\sb120
The available qualifiers are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 alloc} defines the section to be one which is loaded into memory when 
the program is run. {\f1 noalloc} defines it to be one which is not, such 
as an informational or comment section.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 exec} defines the section to be one which should have execute 
permission when the program is run. {\f1 noexec} defines it as one which 
should not.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 write} defines the section to be one which should be writable when the 
program is run. {\f1 nowrite} defines it as one which should not.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 progbits} defines the section to be one with explicit contents stored 
in the object file: an ordinary code or data section, for example, 
{\f1 nobits} defines the section to be one with no explicit contents given, 
such as a BSS section.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 align=}, used with a trailing number as in {\f1 obj}, gives the 
alignment requirements of the section.
\par\pard\sb120
The defaults assumed by NASM if you do not specify the above qualifiers 
are:
\par\sb120
\keep\f1\sb120
section .text    progbits  alloc  exec    nowrite  align=16 \par\sb0
section .rodata  progbits  alloc  noexec  nowrite  align=4 \par\sb0
section .data    progbits  alloc  noexec  write    align=4 \par\sb0
section .bss     nobits    alloc  noexec  write    align=4 \par\sb0
section other    progbits  alloc  noexec  nowrite  align=1\par\sb0
\pard\f0\sb120
(Any section name other than {\f1 .text}, {\f1 .rodata}, {\f1 .data} and 
{\f1 .bss} is treated by default like {\f1 other} in the above code.)
\par\sb120
\page
#{\footnote section_6_5_2}
${\footnote 6.5.2. Position\'ADIndependent Code: elf Special Symbols and WRT}
+{\footnote browse:00148}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_5')");
EnableButton("btn_up")}
K{\footnote $$ token;
ELF, shared libraries;
_GLOBAL_OFFSET_TABLE_;
..got;
GOT;
..gotoff;
..gotpc;
PIC;
..plt;
PLT relocations;
position\'ADindependent code;
procedure linkage table;
relocations, PIC-specific;
..sym;
WRT}
\keepn\f2\b\fs30\sb60\sa60
6.5.2. Position\'ADIndependent Code: {\f1 elf} Special Symbols and {\f1 WRT}
\par\pard\plain\sb120
The {\f1 ELF} specification contains enough features to allow 
position-independent code (PIC) to be written, which makes ELF shared 
libraries very flexible. However, it also means NASM has to be able to 
generate a variety of strange relocation types in ELF object files, if it 
is to be an assembler which can write PIC.
\par\sb120
Since {\f1 ELF} does not support segment-base references, the {\f1 WRT} 
operator is not used for its normal purpose; therefore NASM's {\f1 elf} 
output format makes use of {\f1 WRT} for a different purpose, namely the 
PIC-specific relocation types.
\par\sb120
{\f1 elf} defines five special symbols which you can use as the right-hand 
side of the {\f1 WRT} operator to obtain PIC relocation types. They are 
{\f1 ..gotpc}, {\f1 ..gotoff}, {\f1 ..got}, {\f1 ..plt} and {\f1 ..sym}. 
Their functions are summarised here:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Referring to the symbol marking the global offset table base using 
{\f1 wrt\'A0..gotpc} will end up giving the distance from the beginning of 
the current section to the global offset table. 
({\f1 _GLOBAL_OFFSET_TABLE_} is the standard symbol name used to refer to 
the GOT.) So you would then need to add {\f1 $$} to the result to get the 
real address of the GOT.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Referring to a location in one of your own sections using 
{\f1 wrt\'A0..gotoff} will give the distance from the beginning of the GOT 
to the specified location, so that adding on the address of the GOT would 
give the real address of the location you wanted.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Referring to an external or global symbol using {\f1 wrt\'A0..got} causes 
the linker to build an entry {\i in} the GOT containing the address of the 
symbol, and the reference gives the distance from the beginning of the GOT 
to the entry; so you can add on the address of the GOT, load from the 
resulting address, and end up with the address of the symbol.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Referring to a procedure name using {\f1 wrt\'A0..plt} causes the linker to 
build a procedure linkage table entry for the symbol, and the reference 
gives the address of the PLT entry. You can only use this in contexts which 
would generate a PC-relative relocation normally (i.e. as the destination 
for {\f1 CALL} or {\f1 JMP}), since ELF contains no relocation type to 
refer to PLT entries absolutely.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Referring to a symbol name using {\f1 wrt\'A0..sym} causes NASM to write an 
ordinary relocation, but instead of making the relocation relative to the 
start of the section and then adding on the offset to the symbol, it will 
write a relocation record aimed directly at the symbol in question. The 
distinction is a necessary one due to a peculiarity of the dynamic linker.
\par\pard\sb120
A fuller explanation of how to use these relocation types to write shared 
libraries entirely in NASM is given in {\uldb section 8.2}{\v section_8_2}.
\par\sb120
\page
#{\footnote section_6_5_3}
${\footnote 6.5.3. elf Extensions to the GLOBAL Directive}
+{\footnote browse:00149}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_5')");
EnableButton("btn_up")}
K{\footnote data;
function;
GLOBAL, aoutb extensions to;
GLOBAL, elf extensions to;
object;
shared library;
size, of symbols;
symbol sizes, specifying;
symbol types, specifying;
type, of symbols}
\keepn\f2\b\fs30\sb60\sa60
6.5.3. {\f1 elf} Extensions to the {\f1 GLOBAL} Directive
\par\pard\plain\sb120
{\f1 ELF} object files can contain more information about a global symbol 
than just its address: they can contain the size of the symbol and its type 
as well. These are not merely debugger conveniences, but are actually 
necessary when the program being written is a shared library. NASM 
therefore supports some extensions to the {\f1 GLOBAL} directive, allowing 
you to specify these features.
\par\sb120
You can specify whether a global variable is a function or a data object by 
suffixing the name with a colon and the word {\f1 function} or {\f1 data}. 
({\f1 object} is a synonym for {\f1 data}.) For example:
\par\sb120
\keep\f1\sb120
global   hashlookup:function, hashtable:data\par\sb0
\pard\f0\sb120
exports the global symbol {\f1 hashlookup} as a function and 
{\f1 hashtable} as a data object.
\par\sb120
You can also specify the size of the data associated with the symbol, as a 
numeric expression (which may involve labels, and even forward references) 
after the type specifier. Like this:
\par\sb120
\keep\f1\sb120
global  hashtable:data (hashtable.end - hashtable) \par\sb0
\par\sb0
hashtable: \par\sb0
        db this,that,theother  ; some data here \par\sb0
.end:\par\sb0
\pard\f0\sb120
This makes NASM automatically calculate the length of the table and place 
that information into the {\f1 ELF} symbol table.
\par\sb120
Declaring the type and size of global symbols is necessary when writing 
shared library code. For more information, see {\uldb section 
8.2.4}{\v section_8_2_4}.
\par\sb120
\page
#{\footnote section_6_5_4}
${\footnote 6.5.4. elf Extensions to the COMMON Directive }
+{\footnote browse:00150}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_5')");
EnableButton("btn_up")}
K{\footnote alignment, of elf common variables;
COMMON, elf extensions to;
common variables, alignment in elf}
\keepn\f2\b\fs30\sb60\sa60
6.5.4. {\f1 elf} Extensions to the {\f1 COMMON} Directive 
\par\pard\plain\sb120
{\f1 ELF} also allows you to specify alignment requirements on common 
variables. This is done by putting a number (which must be a power of two) 
after the name and size of the common variable, separated (as usual) by a 
colon. For example, an array of doublewords would benefit from 4-byte 
alignment:
\par\sb120
\keep\f1\sb120
common  dwordarray 128:4\par\sb0
\pard\f0\sb120
This declares the total size of the array to be 128 bytes, and requires 
that it be aligned on a 4-byte boundary.
\par\sb120
\page
#{\footnote section_6_5_5}
${\footnote 6.5.5. 16-bit code and ELF }
+{\footnote browse:00151}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_5')");
EnableButton("btn_up")}
K{\footnote ELF, 16-bit code and}
\keepn\f2\b\fs30\sb60\sa60
6.5.5. 16-bit code and ELF 
\par\pard\plain\sb120
The {\f1 ELF32} specification doesn't provide relocations for 8- and 16-bit 
values, but the GNU {\f1 ld} linker adds these as an extension. NASM can 
generate GNU-compatible relocations, to allow 16-bit code to be linked as 
ELF using GNU {\f1 ld}. If NASM is used with the 
{\f1 \'ADw+gnu\'ADelf\'ADextensions} option, a warning is issued when one 
of these relocations is generated.
\par\sb120
\page
#{\footnote section_6_6}
${\footnote 6.6. aout: Linux a.out Object Files}
+{\footnote browse:00152}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote a.out, Linux version;
aout;
.bss;
.data;
Linux, a.out;
standardised section names;
.text}
\keepn\f2\b\fs30\sb60\sa60
6.6. {\f1 aout}: Linux {\f1 a.out} Object Files
\par\pard\plain\sb120
The {\f1 aout} format generates {\f1 a.out} object files, in the form used 
by early Linux systems (current Linux systems use ELF, see {\uldb section 
6.5}{\v section_6_5}.) These differ from other {\f1 a.out} object files in 
that the magic number in the first four bytes of the file is different; 
also, some implementations of {\f1 a.out}, for example NetBSD's, support 
position-independent code, which Linux's implementation does not.
\par\sb120
{\f1 a.out} provides a default output file-name extension of {\f1 .o}.
\par\sb120
{\f1 a.out} is a very simple object format. It supports no special 
directives, no special symbols, no use of {\f1 SEG} or {\f1 WRT}, and no 
extensions to any standard directives. It supports only the three standard 
section names {\f1 .text}, {\f1 .data} and {\f1 .bss}.
\par\sb120
\page
#{\footnote section_6_7}
${\footnote 6.7. aoutb: NetBSD/FreeBSD/OpenBSD a.out Object Files}
+{\footnote browse:00153}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote a.out, BSD version;
aoutb;
.bss;
.data;
FreeBSD;
NetBSD;
OpenBSD;
PIC;
position\'ADindependent code;
shared libraries;
standardised section names;
.text;
WRT}
\keepn\f2\b\fs30\sb60\sa60
6.7. {\f1 aoutb}: NetBSD/FreeBSD/OpenBSD {\f1 a.out} Object Files
\par\pard\plain\sb120
The {\f1 aoutb} format generates {\f1 a.out} object files, in the form used 
by the various free {\f1 BSD\'A0Unix} clones, {\f1 NetBSD}, {\f1 FreeBSD} 
and {\f1 OpenBSD}. For simple object files, this object format is exactly 
the same as {\f1 aout} except for the magic number in the first four bytes 
of the file. However, the {\f1 aoutb} format supports 
position\'ADindependent code in the same way as the {\f1 elf} format, so 
you can use it to write {\f1 BSD} shared libraries.
\par\sb120
{\f1 aoutb} provides a default output file-name extension of {\f1 .o}.
\par\sb120
{\f1 aoutb} supports no special directives, no special symbols, and only 
the three standard section names {\f1 .text}, {\f1 .data} and {\f1 .bss}. 
However, it also supports the same use of {\f1 WRT} as {\f1 elf} does, to 
provide position-independent code relocation types. See {\uldb section 
6.5.2}{\v section_6_5_2} for full documentation of this feature.
\par\sb120
{\f1 aoutb} also supports the same extensions to the {\f1 GLOBAL} directive 
as {\f1 elf} does: see {\uldb section 6.5.3}{\v section_6_5_3} for 
documentation of this.
\par\sb120
\page
#{\footnote section_6_8}
${\footnote 6.8. as86: Minix/Linux as86 Object Files}
+{\footnote browse:00154}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote as86;
.bss;
.data;
ld86;
Linux, as86;
Minix;
standardised section names;
.text}
\keepn\f2\b\fs30\sb60\sa60
6.8. {\f1 as86}: Minix/Linux {\f1 as86} Object Files
\par\pard\plain\sb120
The Minix/Linux 16-bit assembler {\f1 as86} has its own non-standard object 
file format. Although its companion linker {\f1 ld86} produces something 
close to ordinary {\f1 a.out} binaries as output, the object file format 
used to communicate between {\f1 as86} and {\f1 ld86} is not itself 
{\f1 a.out}.
\par\sb120
NASM supports this format, just in case it is useful, as {\f1 as86}. 
{\f1 as86} provides a default output file-name extension of {\f1 .o}.
\par\sb120
{\f1 as86} is a very simple object format (from the NASM user's point of 
view). It supports no special directives, no special symbols, no use of 
{\f1 SEG} or {\f1 WRT}, and no extensions to any standard directives. It 
supports only the three standard section names {\f1 .text}, {\f1 .data} and 
{\f1 .bss}.
\par\sb120
\page
#{\footnote section_6_9}
${\footnote 6.9. rdf: Relocatable Dynamic Object File Format}
+{\footnote browse:00155}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote .bss;
.data;
rdf;
rdoff subdirectory;
Relocatable Dynamic Object File Format;
standardised section names;
.text}
\keepn\f2\b\fs30\sb60\sa60
6.9. {\f1 rdf}: Relocatable Dynamic Object File Format
\par\pard\plain\sb120
The {\f1 rdf} output format produces {\f1 RDOFF} object files. {\f1 RDOFF} 
(Relocatable Dynamic Object File Format) is a home-grown object-file 
format, designed alongside NASM itself and reflecting in its file format 
the internal structure of the assembler.
\par\sb120
{\f1 RDOFF} is not used by any well-known operating systems. Those writing 
their own systems, however, may well wish to use {\f1 RDOFF} as their 
object format, on the grounds that it is designed primarily for simplicity 
and contains very little file-header bureaucracy.
\par\sb120
The Unix NASM archive, and the DOS archive which includes sources, both 
contain an {\f1 rdoff} subdirectory holding a set of RDOFF utilities: an 
RDF linker, an {\f1 RDF} static-library manager, an RDF file dump utility, 
and a program which will load and execute an RDF executable under Linux.
\par\sb120
{\f1 rdf} supports only the standard section names {\f1 .text}, {\f1 .data} 
and {\f1 .bss}.
\par\sb120
\li360\fi-360
{\uldb Section 6.9.1: Requiring a Library: The LIBRARY Directive}{\v section_6_9_1}\par\sb0
{\uldb Section 6.9.2: Specifying a Module Name: The MODULE Directive}{\v section_6_9_2}\par\sb0
{\uldb Section 6.9.3: rdf Extensions to the GLOBAL directive}{\v section_6_9_3}\par\sb0
\pard\sb120
\page
#{\footnote section_6_9_1}
${\footnote 6.9.1. Requiring a Library: The LIBRARY Directive}
+{\footnote browse:00156}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_9')");
EnableButton("btn_up")}
K{\footnote LIBRARY}
\keepn\f2\b\fs30\sb60\sa60
6.9.1. Requiring a Library: The {\f1 LIBRARY} Directive
\par\pard\plain\sb120
{\f1 RDOFF} contains a mechanism for an object file to demand a given 
library to be linked to the module, either at load time or run time. This 
is done by the {\f1 LIBRARY} directive, which takes one argument which is 
the name of the module:
\par\sb120
\keep\f1\sb120
    library  mylib.rdl\par\sb0
\pard\f0\sb120
\page
#{\footnote section_6_9_2}
${\footnote 6.9.2. Specifying a Module Name: The MODULE Directive}
+{\footnote browse:00157}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_9')");
EnableButton("btn_up")}
K{\footnote $, prefix;
MODULE}
\keepn\f2\b\fs30\sb60\sa60
6.9.2. Specifying a Module Name: The {\f1 MODULE} Directive
\par\pard\plain\sb120
Special {\f1 RDOFF} header record is used to store the name of the module. 
It can be used, for example, by run-time loader to perform dynamic linking. 
{\f1 MODULE} directive takes one argument which is the name of current 
module:
\par\sb120
\keep\f1\sb120
    module  mymodname\par\sb0
\pard\f0\sb120
Note that when you statically link modules and tell linker to strip the 
symbols from output file, all module names will be stripped too. To avoid 
it, you should start module names with {\f1 $}, like:
\par\sb120
\keep\f1\sb120
    module  $kernel.core\par\sb0
\pard\f0\sb120
\page
#{\footnote section_6_9_3}
${\footnote 6.9.3. rdf Extensions to the GLOBAL directive}
+{\footnote browse:00158}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_6_9')");
EnableButton("btn_up")}
K{\footnote data;
export;
function;
GLOBAL, rdf extensions to;
object;
proc}
\keepn\f2\b\fs30\sb60\sa60
6.9.3. {\f1 rdf} Extensions to the {\f1 GLOBAL} directive
\par\pard\plain\sb120
{\f1 RDOFF} global symbols can contain additional information needed by the 
static linker. You can mark a global symbol as exported, thus telling the 
linker do not strip it from target executable or library file. Like in 
{\f1 ELF}, you can also specify whether an exported symbol is a procedure 
(function) or data object.
\par\sb120
Suffixing the name with a colon and the word {\f1 export} you make the 
symbol exported:
\par\sb120
\keep\f1\sb120
    global  sys_open:export\par\sb0
\pard\f0\sb120
To specify that exported symbol is a procedure (function), you add the word 
{\f1 proc} or {\f1 function} after declaration:
\par\sb120
\keep\f1\sb120
    global  sys_open:export proc\par\sb0
\pard\f0\sb120
Similarly, to specify exported data object, add the word {\f1 data} or 
{\f1 object} to the directive:
\par\sb120
\keep\f1\sb120
    global  kernel_ticks:export data\par\sb0
\pard\f0\sb120
\page
#{\footnote section_6_10}
${\footnote 6.10. dbg: Debugging Format}
+{\footnote browse:00159}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_6')");
EnableButton("btn_up")}
K{\footnote dbg;
OF_DBG}
\keepn\f2\b\fs30\sb60\sa60
6.10. {\f1 dbg}: Debugging Format
\par\pard\plain\sb120
The {\f1 dbg} output format is not built into NASM in the default 
configuration. If you are building your own NASM executable from the 
sources, you can define {\f1 OF_DBG} in {\f1 outform.h} or on the compiler 
command line, and obtain the {\f1 dbg} output format.
\par\sb120
The {\f1 dbg} format does not output an object file as such; instead, it 
outputs a text file which contains a complete list of all the transactions 
between the main body of NASM and the output-format back end module. It is 
primarily intended to aid people who want to write their own output 
drivers, so that they can get a clearer idea of the various requests the 
main program makes of the output driver, and in what order they happen.
\par\sb120
For simple files, one can easily use the {\f1 dbg} format like this:
\par\sb120
\keep\f1\sb120
nasm -f dbg filename.asm\par\sb0
\pard\f0\sb120
which will generate a diagnostic file called {\f1 filename.dbg}. However, 
this will not work well on files which were designed for a different object 
format, because each object format defines its own macros (usually 
user-level forms of directives), and those macros will not be defined in 
the {\f1 dbg} format. Therefore it can be useful to run NASM twice, in 
order to do the preprocessing with the native object format selected:
\par\sb120
\keep\f1\sb120
nasm -e -f rdf -o rdfprog.i rdfprog.asm \par\sb0
nasm -a -f dbg rdfprog.i\par\sb0
\pard\f0\sb120
This preprocesses {\f1 rdfprog.asm} into {\f1 rdfprog.i}, keeping the 
{\f1 rdf} object format selected in order to make sure RDF special 
directives are converted into primitive form correctly. Then the 
preprocessed source is fed through the {\f1 dbg} format to generate the 
final diagnostic output.
\par\sb120
This workaround will still typically not work for programs intended for 
{\f1 obj} format, because the {\f1 obj} {\f1 SEGMENT} and {\f1 GROUP} 
directives have side effects of defining the segment and group names as 
symbols; {\f1 dbg} will not do this, so the program will not assemble. You 
will have to work around that by defining the symbols yourself (using 
{\f1 EXTERN}, for example) if you really need to get a {\f1 dbg} trace of 
an {\f1 obj}\'96specific source file.
\par\sb120
{\f1 dbg} accepts any section name and any directives at all, and logs them 
all to its output file.
\par\sb120
\page
#{\footnote chapter_7}
${\footnote Chapter 7: Writing 16-bit Code (DOS, Windows 3/3.1)}
+{\footnote browse:00160}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
Chapter 7: Writing 16-bit Code (DOS, Windows 3/3.1)
\par\pard\plain\sb120
This chapter attempts to cover some of the common issues encountered when 
writing 16-bit code to run under {\f1 MS\'ADDOS} or {\f1 Windows\'A03.x}. 
It covers how to link programs to produce {\f1 .EXE} or {\f1 .COM} files, 
how to write {\f1 .SYS} device drivers, and how to interface assembly 
language code with 16-bit C compilers and with Borland Pascal.
\par\sb120
\li360\fi-360
{\uldb Section 7.1: Producing .EXE Files}{\v section_7_1}\par\sb0
{\uldb Section 7.2: Producing .COM Files}{\v section_7_2}\par\sb0
{\uldb Section 7.3: Producing .SYS Files}{\v section_7_3}\par\sb0
{\uldb Section 7.4: Interfacing to 16-bit C Programs}{\v section_7_4}\par\sb0
{\uldb Section 7.5: Interfacing to Borland Pascal Programs}{\v section_7_5}\par\sb0
\pard\sb120
\page
#{\footnote section_7_1}
${\footnote 7.1. Producing .EXE Files}
+{\footnote browse:00161}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_7')");
EnableButton("btn_up")}
K{\footnote .EXE;
.OBJ;
Windows}
\keepn\f2\b\fs30\sb60\sa60
7.1. Producing {\f1 .EXE} Files
\par\pard\plain\sb120
Any large program written under DOS needs to be built as a {\f1 .EXE} file: 
only {\f1 .EXE} files have the necessary internal structure required to 
span more than one 64K segment. Windows programs, also, have to be built as 
{\f1 .EXE} files, since Windows does not support the {\f1 .COM} format.
\par\sb120
In general, you generate {\f1 .EXE} files by using the {\f1 obj} output 
format to produce one or more {\f1 .OBJ} files, and then linking them 
together using a linker. However, NASM also supports the direct generation 
of simple DOS {\f1 .EXE} files using the {\f1 bin} output format (by using 
{\f1 DB} and {\f1 DW} to construct the {\f1 .EXE} file header), and a macro 
package is supplied to do this. Thanks to Yann Guidon for contributing the 
code for this.
\par\sb120
NASM may also support {\f1 .EXE} natively as another output format in 
future releases.
\par\sb120
\li360\fi-360
{\uldb Section 7.1.1: Using the obj Format To Generate .EXE Files}{\v section_7_1_1}\par\sb0
{\uldb Section 7.1.2: Using the bin Format To Generate .EXE Files}{\v section_7_1_2}\par\sb0
\pard\sb120
\page
#{\footnote section_7_1_1}
${\footnote 7.1.1. Using the obj Format To Generate .EXE Files}
+{\footnote browse:00162}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_1')");
EnableButton("btn_up")}
K{\footnote ALINK;
alink.sourceforge.net;
djlink;
FreeLink;
ftp.simtel.net;
linker, free;
program entry point;
..start;
test subdirectory;
VAL;
www.delorie.com;
www.pcorner.com;
x2ftp.oulu.fi}
\keepn\f2\b\fs30\sb60\sa60
7.1.1. Using the {\f1 obj} Format To Generate {\f1 .EXE} Files
\par\pard\plain\sb120
This section describes the usual method of generating {\f1 .EXE} files by 
linking {\f1 .OBJ} files together.
\par\sb120
Most 16-bit programming language packages come with a suitable linker; if 
you have none of these, there is a free linker called VAL, available in 
{\f1 LZH} archive format from {\f1 x2ftp.oulu.fi}. An LZH archiver can be 
found at {\f1 ftp.simtel.net}. There is another `free' linker (though this 
one doesn't come with sources) called FREELINK, available from 
{\f1 www.pcorner.com}. A third, {\f1 djlink}, written by DJ Delorie, is 
available at {\f1 www.delorie.com}. A fourth linker, {\f1 ALINK}, written 
by Anthony A.J. Williams, is available at {\f1 alink.sourceforge.net}.
\par\sb120
When linking several {\f1 .OBJ} files into a {\f1 .EXE} file, you should 
ensure that exactly one of them has a start point defined (using the 
{\f1 ..start} special symbol defined by the {\f1 obj} format: see 
{\uldb section 6.2.6}{\v section_6_2_6}). If no module defines a start 
point, the linker will not know what value to give the entry-point field in 
the output file header; if more than one defines a start point, the linker 
will not know {\i which} value to use.
\par\sb120
An example of a NASM source file which can be assembled to a {\f1 .OBJ} 
file and linked on its own to a {\f1 .EXE} is given here. It demonstrates 
the basic principles of defining a stack, initialising the segment 
registers, and declaring a start point. This file is also provided in the 
{\f1 test} subdirectory of the NASM archives, under the name 
{\f1 objexe.asm}.
\par\sb120
\keep\f1\sb120
segment code \par\sb0
\par\sb0
..start: \par\sb0
        mov     ax,data \par\sb0
        mov     ds,ax \par\sb0
        mov     ax,stack \par\sb0
        mov     ss,ax \par\sb0
        mov     sp,stacktop\par\sb0
\pard\f0\sb120
This initial piece of code sets up {\f1 DS} to point to the data segment, 
and initialises {\f1 SS} and {\f1 SP} to point to the top of the provided 
stack. Notice that interrupts are implicitly disabled for one instruction 
after a move into {\f1 SS}, precisely for this situation, so that there's 
no chance of an interrupt occurring between the loads of {\f1 SS} and 
{\f1 SP} and not having a stack to execute on.
\par\sb120
Note also that the special symbol {\f1 ..start} is defined at the beginning 
of this code, which means that will be the entry point into the resulting 
executable file.
\par\sb120
\keep\f1\sb120
        mov     dx,hello \par\sb0
        mov     ah,9 \par\sb0
        int     0x21\par\sb0
\pard\f0\sb120
The above is the main program: load {\f1 DS:DX} with a pointer to the 
greeting message ({\f1 hello} is implicitly relative to the segment 
{\f1 data}, which was loaded into {\f1 DS} in the setup code, so the full 
pointer is valid), and call the DOS print-string function.
\par\sb120
\keep\f1\sb120
        mov     ax,0x4c00 \par\sb0
        int     0x21\par\sb0
\pard\f0\sb120
This terminates the program using another DOS system call.
\par\sb120
\keep\f1\sb120
segment data \par\sb0
\par\sb0
hello:  db      'hello, world', 13, 10, '$'\par\sb0
\pard\f0\sb120
The data segment contains the string we want to display.
\par\sb120
\keep\f1\sb120
segment stack stack \par\sb0
        resb 64 \par\sb0
stacktop:\par\sb0
\pard\f0\sb120
The above code declares a stack segment containing 64 bytes of 
uninitialised stack space, and points {\f1 stacktop} at the top of it. The 
directive {\f1 segment\'A0stack\'A0stack} defines a segment {\i called} 
{\f1 stack}, and also of {\i type} {\f1 STACK}. The latter is not necessary 
to the correct running of the program, but linkers are likely to issue 
warnings or errors if your program has no segment of type {\f1 STACK}.
\par\sb120
The above file, when assembled into a {\f1 .OBJ} file, will link on its own 
to a valid {\f1 .EXE} file, which when run will print `hello, world' and 
then exit.
\par\sb120
\page
#{\footnote section_7_1_2}
${\footnote 7.1.2. Using the bin Format To Generate .EXE Files}
+{\footnote browse:00163}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_1')");
EnableButton("btn_up")}
K{\footnote EXE_begin;
exebin.mac;
EXE_end;
EXE_stack;
misc subdirectory}
\keepn\f2\b\fs30\sb60\sa60
7.1.2. Using the {\f1 bin} Format To Generate {\f1 .EXE} Files
\par\pard\plain\sb120
The {\f1 .EXE} file format is simple enough that it's possible to build a 
{\f1 .EXE} file by writing a pure-binary program and sticking a 32-byte 
header on the front. This header is simple enough that it can be generated 
using {\f1 DB} and {\f1 DW} commands by NASM itself, so that you can use 
the {\f1 bin} output format to directly generate {\f1 .EXE} files.
\par\sb120
Included in the NASM archives, in the {\f1 misc} subdirectory, is a file 
{\f1 exebin.mac} of macros. It defines three macros: {\f1 EXE_begin}, 
{\f1 EXE_stack} and {\f1 EXE_end}.
\par\sb120
To produce a {\f1 .EXE} file using this method, you should start by using 
{\f1 %include} to load the {\f1 exebin.mac} macro package into your source 
file. You should then issue the {\f1 EXE_begin} macro call (which takes no 
arguments) to generate the file header data. Then write code as normal for 
the {\f1 bin} format \'96 you can use all three standard sections 
{\f1 .text}, {\f1 .data} and {\f1 .bss}. At the end of the file you should 
call the {\f1 EXE_end} macro (again, no arguments), which defines some 
symbols to mark section sizes, and these symbols are referred to in the 
header code generated by {\f1 EXE_begin}.
\par\sb120
In this model, the code you end up writing starts at {\f1 0x100}, just like 
a {\f1 .COM} file \'96 in fact, if you strip off the 32-byte header from 
the resulting {\f1 .EXE} file, you will have a valid {\f1 .COM} program. 
All the segment bases are the same, so you are limited to a 64K program, 
again just like a {\f1 .COM} file. Note that an {\f1 ORG} directive is 
issued by the {\f1 EXE_begin} macro, so you should not explicitly issue one 
of your own.
\par\sb120
You can't directly refer to your segment base value, unfortunately, since 
this would require a relocation in the header, and things would get a lot 
more complicated. So you should get your segment base by copying it out of 
{\f1 CS} instead.
\par\sb120
On entry to your {\f1 .EXE} file, {\f1 SS:SP} are already set up to point 
to the top of a 2Kb stack. You can adjust the default stack size of 2Kb by 
calling the {\f1 EXE_stack} macro. For example, to change the stack size of 
your program to 64 bytes, you would call {\f1 EXE_stack\'A064}.
\par\sb120
A sample program which generates a {\f1 .EXE} file in this way is given in 
the {\f1 test} subdirectory of the NASM archive, as {\f1 binexe.asm}.
\par\sb120
\page
#{\footnote section_7_2}
${\footnote 7.2. Producing .COM Files}
+{\footnote browse:00164}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_7')");
EnableButton("btn_up")}
K{\footnote .COM}
\keepn\f2\b\fs30\sb60\sa60
7.2. Producing {\f1 .COM} Files
\par\pard\plain\sb120
While large DOS programs must be written as {\f1 .EXE} files, small ones 
are often better written as {\f1 .COM} files. {\f1 .COM} files are pure 
binary, and therefore most easily produced using the {\f1 bin} output 
format.
\par\sb120
\li360\fi-360
{\uldb Section 7.2.1: Using the bin Format To Generate .COM Files}{\v section_7_2_1}\par\sb0
{\uldb Section 7.2.2: Using the obj Format To Generate .COM Files}{\v section_7_2_2}\par\sb0
\pard\sb120
\page
#{\footnote section_7_2_1}
${\footnote 7.2.1. Using the bin Format To Generate .COM Files}
+{\footnote browse:00165}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_2')");
EnableButton("btn_up")}
K{\footnote ORG}
\keepn\f2\b\fs30\sb60\sa60
7.2.1. Using the {\f1 bin} Format To Generate {\f1 .COM} Files
\par\pard\plain\sb120
{\f1 .COM} files expect to be loaded at offset {\f1 100h} into their 
segment (though the segment may change). Execution then begins at 
{\f1 100h}, i.e. right at the start of the program. So to write a 
{\f1 .COM} program, you would create a source file looking like
\par\sb120
\keep\f1\sb120
        org 100h \par\sb0
\par\sb0
section .text \par\sb0
\par\sb0
start: \par\sb0
        ; put your code here \par\sb0
\par\sb0
section .data \par\sb0
\par\sb0
        ; put data items here \par\sb0
\par\sb0
section .bss \par\sb0
\par\sb0
        ; put uninitialised data here\par\sb0
\pard\f0\sb120
The {\f1 bin} format puts the {\f1 .text} section first in the file, so you 
can declare data or BSS items before beginning to write code if you want to 
and the code will still end up at the front of the file where it belongs.
\par\sb120
The BSS (uninitialised data) section does not take up space in the 
{\f1 .COM} file itself: instead, addresses of BSS items are resolved to 
point at space beyond the end of the file, on the grounds that this will be 
free memory when the program is run. Therefore you should not rely on your 
BSS being initialised to all zeros when you run.
\par\sb120
To assemble the above program, you should use a command line like
\par\sb120
\keep\f1\sb120
nasm myprog.asm -fbin -o myprog.com\par\sb0
\pard\f0\sb120
The {\f1 bin} format would produce a file called {\f1 myprog} if no 
explicit output file name were specified, so you have to override it and 
give the desired file name.
\par\sb120
\page
#{\footnote section_7_2_2}
${\footnote 7.2.2. Using the obj Format To Generate .COM Files}
+{\footnote browse:00166}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_2')");
EnableButton("btn_up")}
K{\footnote EXE2BIN;
ORG;
TLINK}
\keepn\f2\b\fs30\sb60\sa60
7.2.2. Using the {\f1 obj} Format To Generate {\f1 .COM} Files
\par\pard\plain\sb120
If you are writing a {\f1 .COM} program as more than one module, you may 
wish to assemble several {\f1 .OBJ} files and link them together into a 
{\f1 .COM} program. You can do this, provided you have a linker capable of 
outputting {\f1 .COM} files directly (TLINK does this), or alternatively a 
converter program such as {\f1 EXE2BIN} to transform the {\f1 .EXE} file 
output from the linker into a {\f1 .COM} file.
\par\sb120
If you do this, you need to take care of several things:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The first object file containing code should start its code segment with a 
line like {\f1 RESB\'A0100h}. This is to ensure that the code begins at 
offset {\f1 100h} relative to the beginning of the code segment, so that 
the linker or converter program does not have to adjust address references 
within the file when generating the {\f1 .COM} file. Other assemblers use 
an {\f1 ORG} directive for this purpose, but {\f1 ORG} in NASM is a 
format-specific directive to the {\f1 bin} output format, and does not mean 
the same thing as it does in MASM-compatible assemblers.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
You don't need to define a stack segment.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
All your segments should be in the same group, so that every time your code 
or data references a symbol offset, all offsets are relative to the same 
segment base. This is because, when a {\f1 .COM} file is loaded, all the 
segment registers contain the same value.
\par\pard\sb120
\page
#{\footnote section_7_3}
${\footnote 7.3. Producing .SYS Files}
+{\footnote browse:00167}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_7')");
EnableButton("btn_up")}
K{\footnote comp.os.msdos.programmer;
MS-DOS device drivers;
.SYS}
\keepn\f2\b\fs30\sb60\sa60
7.3. Producing {\f1 .SYS} Files
\par\pard\plain\sb120
MS\'ADDOS device drivers \'96 {\f1 .SYS} files \'96 are pure binary files, 
similar to {\f1 .COM} files, except that they start at origin zero rather 
than {\f1 100h}. Therefore, if you are writing a device driver using the 
{\f1 bin} format, you do not need the {\f1 ORG} directive, since the 
default origin for {\f1 bin} is zero. Similarly, if you are using 
{\f1 obj}, you do not need the {\f1 RESB\'A0100h} at the start of your code 
segment.
\par\sb120
{\f1 .SYS} files start with a header structure, containing pointers to the 
various routines inside the driver which do the work. This structure should 
be defined at the start of the code segment, even though it is not actually 
code.
\par\sb120
For more information on the format of {\f1 .SYS} files, and the data which 
has to go in the header structure, a list of books is given in the 
Frequently Asked Questions list for the newsgroup 
{\f1 comp.os.msdos.programmer}.
\par\sb120
\page
#{\footnote section_7_4}
${\footnote 7.4. Interfacing to 16-bit C Programs}
+{\footnote browse:00168}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_7')");
EnableButton("btn_up")}
K{\footnote mixed\'ADlanguage program}
\keepn\f2\b\fs30\sb60\sa60
7.4. Interfacing to 16-bit C Programs
\par\pard\plain\sb120
This section covers the basics of writing assembly routines that call, or 
are called from, C programs. To do this, you would typically write an 
assembly module as a {\f1 .OBJ} file, and link it with your C modules to 
produce a mixed\'ADlanguage program.
\par\sb120
\li360\fi-360
{\uldb Section 7.4.1: External Symbol Names}{\v section_7_4_1}\par\sb0
{\uldb Section 7.4.2: Memory Models}{\v section_7_4_2}\par\sb0
{\uldb Section 7.4.3: Function Definitions and Function Calls}{\v section_7_4_3}\par\sb0
{\uldb Section 7.4.4: Accessing Data Items}{\v section_7_4_4}\par\sb0
{\uldb Section 7.4.5: c16.mac: Helper Macros for the 16-bit C Interface}{\v section_7_4_5}\par\sb0
\pard\sb120
\page
#{\footnote section_7_4_1}
${\footnote 7.4.1. External Symbol Names}
+{\footnote browse:00169}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_4')");
EnableButton("btn_up")}
K{\footnote C symbol names;
underscore, in C symbols}
\keepn\f2\b\fs30\sb60\sa60
7.4.1. External Symbol Names
\par\pard\plain\sb120
C compilers have the convention that the names of all global symbols 
(functions or data) they define are formed by prefixing an underscore to 
the name as it appears in the C program. So, for example, the function a C 
programmer thinks of as {\f1 printf} appears to an assembly language 
programmer as {\f1 _printf}. This means that in your assembly programs, you 
can define symbols without a leading underscore, and not have to worry 
about name clashes with C symbols.
\par\sb120
If you find the underscores inconvenient, you can define macros to replace 
the {\f1 GLOBAL} and {\f1 EXTERN} directives as follows:
\par\sb120
\keep\f1\sb120
%macro  cglobal 1 \par\sb0
\par\sb0
  global  _%1 \par\sb0
  %define %1 _%1 \par\sb0
\par\sb0
%endmacro \par\sb0
\par\sb0
%macro  cextern 1 \par\sb0
\par\sb0
  extern  _%1 \par\sb0
  %define %1 _%1 \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
(These forms of the macros only take one argument at a time; a {\f1 %rep} 
construct could solve this.)
\par\sb120
If you then declare an external like this:
\par\sb120
\keep\f1\sb120
cextern printf\par\sb0
\pard\f0\sb120
then the macro will expand it as
\par\sb120
\keep\f1\sb120
extern  _printf \par\sb0
%define printf _printf\par\sb0
\pard\f0\sb120
Thereafter, you can reference {\f1 printf} as if it was a symbol, and the 
preprocessor will put the leading underscore on where necessary.
\par\sb120
The {\f1 cglobal} macro works similarly. You must use {\f1 cglobal} before 
defining the symbol in question, but you would have had to do that anyway 
if you used {\f1 GLOBAL}.
\par\sb120
Also see {\uldb section 2.1.21}{\v section_2_1_21}.
\par\sb120
\page
#{\footnote section_7_4_2}
${\footnote 7.4.2. Memory Models}
+{\footnote browse:00170}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_4')");
EnableButton("btn_up")}
K{\footnote _DATA;
memory models;
_TEXT}
\keepn\f2\b\fs30\sb60\sa60
7.4.2. Memory Models
\par\pard\plain\sb120
NASM contains no mechanism to support the various C memory models directly; 
you have to keep track yourself of which one you are writing for. This 
means you have to keep track of the following things:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
In models using a single code segment (tiny, small and compact), functions 
are near. This means that function pointers, when stored in data segments 
or pushed on the stack as function arguments, are 16 bits long and contain 
only an offset field (the {\f1 CS} register never changes its value, and 
always gives the segment part of the full function address), and that 
functions are called using ordinary near {\f1 CALL} instructions and return 
using {\f1 RETN} (which, in NASM, is synonymous with {\f1 RET} anyway). 
This means both that you should write your own routines to return with 
{\f1 RETN}, and that you should call external C routines with near 
{\f1 CALL} instructions.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
In models using more than one code segment (medium, large and huge), 
functions are far. This means that function pointers are 32 bits long 
(consisting of a 16-bit offset followed by a 16-bit segment), and that 
functions are called using {\f1 CALL\'A0FAR} (or {\f1 CALL\'A0seg:offset}) 
and return using {\f1 RETF}. Again, you should therefore write your own 
routines to return with {\f1 RETF} and use {\f1 CALL\'A0FAR} to call 
external routines.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
In models using a single data segment (tiny, small and medium), data 
pointers are 16 bits long, containing only an offset field (the {\f1 DS} 
register doesn't change its value, and always gives the segment part of the 
full data item address).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
In models using more than one data segment (compact, large and huge), data 
pointers are 32 bits long, consisting of a 16-bit offset followed by a 
16-bit segment. You should still be careful not to modify {\f1 DS} in your 
routines without restoring it afterwards, but {\f1 ES} is free for you to 
use to access the contents of 32-bit data pointers you are passed.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The huge memory model allows single data items to exceed 64K in size. In 
all other memory models, you can access the whole of a data item just by 
doing arithmetic on the offset field of the pointer you are given, whether 
a segment field is present or not; in huge model, you have to be more 
careful of your pointer arithmetic.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
In most memory models, there is a {\i default} data segment, whose segment 
address is kept in {\f1 DS} throughout the program. This data segment is 
typically the same segment as the stack, kept in {\f1 SS}, so that 
functions' local variables (which are stored on the stack) and global data 
items can both be accessed easily without changing {\f1 DS}. Particularly 
large data items are typically stored in other segments. However, some 
memory models (though not the standard ones, usually) allow the assumption 
that {\f1 SS} and {\f1 DS} hold the same value to be removed. Be careful 
about functions' local variables in this latter case.
\par\pard\sb120
In models with a single code segment, the segment is called {\f1 _TEXT}, so 
your code segment must also go by this name in order to be linked into the 
same place as the main code segment. In models with a single data segment, 
or with a default data segment, it is called {\f1 _DATA}.
\par\sb120
\page
#{\footnote section_7_4_3}
${\footnote 7.4.3. Function Definitions and Function Calls}
+{\footnote browse:00171}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_4')");
EnableButton("btn_up")}
K{\footnote C calling convention;
frame pointer;
functions, C calling convention}
\keepn\f2\b\fs30\sb60\sa60
7.4.3. Function Definitions and Function Calls
\par\pard\plain\sb120
The C calling convention in 16-bit programs is as follows. In the following 
description, the words {\i caller} and {\i callee} are used to denote the 
function doing the calling and the function which gets called.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The caller pushes the function's parameters on the stack, one after 
another, in reverse order (right to left, so that the first argument 
specified to the function is pushed last).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The caller then executes a {\f1 CALL} instruction to pass control to the 
callee. This {\f1 CALL} is either near or far depending on the memory 
model.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee receives control, and typically (although this is not actually 
necessary, in functions which do not need to access their parameters) 
starts by saving the value of {\f1 SP} in {\f1 BP} so as to be able to use 
{\f1 BP} as a base pointer to find its parameters on the stack. However, 
the caller was probably doing this too, so part of the calling convention 
states that {\f1 BP} must be preserved by any C function. Hence the callee, 
if it is going to set up {\f1 BP} as a {\i frame pointer}, must push the 
previous value first.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee may then access its parameters relative to {\f1 BP}. The word at 
{\f1 [BP]} holds the previous value of {\f1 BP} as it was pushed; the next 
word, at {\f1 [BP+2]}, holds the offset part of the return address, pushed 
implicitly by {\f1 CALL}. In a small-model (near) function, the parameters 
start after that, at {\f1 [BP+4]}; in a large-model (far) function, the 
segment part of the return address lives at {\f1 [BP+4]}, and the 
parameters begin at {\f1 [BP+6]}. The leftmost parameter of the function, 
since it was pushed last, is accessible at this offset from {\f1 BP}; the 
others follow, at successively greater offsets. Thus, in a function such as 
{\f1 printf} which takes a variable number of parameters, the pushing of 
the parameters in reverse order means that the function knows where to find 
its first parameter, which tells it the number and type of the remaining 
ones.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee may also wish to decrease {\f1 SP} further, so as to allocate 
space on the stack for local variables, which will then be accessible at 
negative offsets from {\f1 BP}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee, if it wishes to return a value to the caller, should leave the 
value in {\f1 AL}, {\f1 AX} or {\f1 DX:AX} depending on the size of the 
value. Floating-point results are sometimes (depending on the compiler) 
returned in {\f1 ST0}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Once the callee has finished processing, it restores {\f1 SP} from {\f1 BP} 
if it had allocated local stack space, then pops the previous value of 
{\f1 BP}, and returns via {\f1 RETN} or {\f1 RETF} depending on memory 
model.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
When the caller regains control from the callee, the function parameters 
are still on the stack, so it typically adds an immediate constant to 
{\f1 SP} to remove them (instead of executing a number of slow {\f1 POP} 
instructions). Thus, if a function is accidentally called with the wrong 
number of parameters due to a prototype mismatch, the stack will still be 
returned to a sensible state since the caller, which {\i knows} how many 
parameters it pushed, does the removing.
\par\pard\sb120
It is instructive to compare this calling convention with that for Pascal 
programs (described in {\uldb section 7.5.1}{\v section_7_5_1}). Pascal has 
a simpler convention, since no functions have variable numbers of 
parameters. Therefore the callee knows how many parameters it should have 
been passed, and is able to deallocate them from the stack itself by 
passing an immediate argument to the {\f1 RET} or {\f1 RETF} instruction, 
so the caller does not have to do it. Also, the parameters are pushed in 
left-to-right order, not right-to-left, which means that a compiler can 
give better guarantees about sequence points without performance suffering.
\par\sb120
Thus, you would define a function in C style in the following way. The 
following example is for small model:
\par\sb120
\keep\f1\sb120
global  _myfunc \par\sb0
\par\sb0
_myfunc: \par\sb0
        push    bp \par\sb0
        mov     bp,sp \par\sb0
        sub     sp,0x40         ; 64 bytes of local stack space \par\sb0
        mov     bx,[bp+4]       ; first parameter to function \par\sb0
\par\sb0
        ; some more code \par\sb0
\par\sb0
        mov     sp,bp           ; undo "sub sp,0x40" above \par\sb0
        pop     bp \par\sb0
        ret\par\sb0
\pard\f0\sb120
For a large-model function, you would replace {\f1 RET} by {\f1 RETF}, and 
look for the first parameter at {\f1 [BP+6]} instead of {\f1 [BP+4]}. Of 
course, if one of the parameters is a pointer, then the offsets of 
{\i subsequent} parameters will change depending on the memory model as 
well: far pointers take up four bytes on the stack when passed as a 
parameter, whereas near pointers take up two.
\par\sb120
At the other end of the process, to call a C function from your assembly 
code, you would do something like this:
\par\sb120
\keep\f1\sb120
extern  _printf \par\sb0
\par\sb0
      ; and then, further down... \par\sb0
\par\sb0
      push    word [myint]        ; one of my integer variables \par\sb0
      push    word mystring       ; pointer into my data segment \par\sb0
      call    _printf \par\sb0
      add     sp,byte 4           ; `byte' saves space \par\sb0
\par\sb0
      ; then those data items... \par\sb0
\par\sb0
segment _DATA \par\sb0
\par\sb0
myint         dw    1234 \par\sb0
mystring      db    'This number -> %d <- should be 1234',10,0\par\sb0
\pard\f0\sb120
This piece of code is the small-model assembly equivalent of the C code
\par\sb120
\keep\f1\sb120
    int myint = 1234; \par\sb0
    printf("This number -> %d <- should be 1234\\n", myint);\par\sb0
\pard\f0\sb120
In large model, the function-call code might look more like this. In this 
example, it is assumed that {\f1 DS} already holds the segment base of the 
segment {\f1 _DATA}. If not, you would have to initialise it first.
\par\sb120
\keep\f1\sb120
      push    word [myint] \par\sb0
      push    word seg mystring   ; Now push the segment, and... \par\sb0
      push    word mystring       ; ... offset of "mystring" \par\sb0
      call    far _printf \par\sb0
      add    sp,byte 6\par\sb0
\pard\f0\sb120
The integer value still takes up one word on the stack, since large model 
does not affect the size of the {\f1 int} data type. The first argument 
(pushed last) to {\f1 printf}, however, is a data pointer, and therefore 
has to contain a segment and offset part. The segment should be stored 
second in memory, and therefore must be pushed first. (Of course, 
{\f1 PUSH\'A0DS} would have been a shorter instruction than 
{\f1 PUSH\'A0WORD\'A0SEG\'A0mystring}, if {\f1 DS} was set up as the above 
example assumed.) Then the actual call becomes a far call, since functions 
expect far calls in large model; and {\f1 SP} has to be increased by 6 
rather than 4 afterwards to make up for the extra word of parameters.
\par\sb120
\page
#{\footnote section_7_4_4}
${\footnote 7.4.4. Accessing Data Items}
+{\footnote browse:00172}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_4')");
EnableButton("btn_up")}
K{\footnote data structure;
STRUC}
\keepn\f2\b\fs30\sb60\sa60
7.4.4. Accessing Data Items
\par\pard\plain\sb120
To get at the contents of C variables, or to declare variables which C can 
access, you need only declare the names as {\f1 GLOBAL} or {\f1 EXTERN}. 
(Again, the names require leading underscores, as stated in {\uldb section 
7.4.1}{\v section_7_4_1}.) Thus, a C variable declared as {\f1 int\'A0i} 
can be accessed from assembler as
\par\sb120
\keep\f1\sb120
extern _i \par\sb0
\par\sb0
        mov ax,[_i]\par\sb0
\pard\f0\sb120
And to declare your own integer variable which C programs can access as 
{\f1 extern\'A0int\'A0j}, you do this (making sure you are assembling in 
the {\f1 _DATA} segment, if necessary):
\par\sb120
\keep\f1\sb120
global  _j \par\sb0
\par\sb0
_j      dw      0\par\sb0
\pard\f0\sb120
To access a C array, you need to know the size of the components of the 
array. For example, {\f1 int} variables are two bytes long, so if a C 
program declares an array as {\f1 int\'A0a[10]}, you can access {\f1 a[3]} 
by coding {\f1 mov\'A0ax,[_a+6]}. (The byte offset 6 is obtained by 
multiplying the desired array index, 3, by the size of the array element, 
2.) The sizes of the C base types in 16-bit compilers are: 1 for 
{\f1 char}, 2 for {\f1 short} and {\f1 int}, 4 for {\f1 long} and 
{\f1 float}, and 8 for {\f1 double}.
\par\sb120
To access a C data structure, you need to know the offset from the base of 
the structure to the field you are interested in. You can either do this by 
converting the C structure definition into a NASM structure definition 
(using {\f1 STRUC}), or by calculating the one offset and using just that.
\par\sb120
To do either of these, you should read your C compiler's manual to find out 
how it organises data structures. NASM gives no special alignment to 
structure members in its own {\f1 STRUC} macro, so you have to specify 
alignment yourself if the C compiler generates it. Typically, you might 
find that a structure like
\par\sb120
\keep\f1\sb120
struct @\{ \par\sb0
    char c; \par\sb0
    int i; \par\sb0
@\} foo;\par\sb0
\pard\f0\sb120
might be four bytes long rather than three, since the {\f1 int} field would 
be aligned to a two-byte boundary. However, this sort of feature tends to 
be a configurable option in the C compiler, either using command-line 
options or {\f1 #pragma} lines, so you have to find out how your own 
compiler does it.
\par\sb120
\page
#{\footnote section_7_4_5}
${\footnote 7.4.5. c16.mac: Helper Macros for the 16-bit C Interface}
+{\footnote browse:00173}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_4')");
EnableButton("btn_up")}
K{\footnote arg;
c16.mac;
endproc;
FARCODE;
misc subdirectory;
proc}
\keepn\f2\b\fs30\sb60\sa60
7.4.5. {\f1 c16.mac}: Helper Macros for the 16-bit C Interface
\par\pard\plain\sb120
Included in the NASM archives, in the {\f1 misc} directory, is a file 
{\f1 c16.mac} of macros. It defines three macros: {\f1 proc}, {\f1 arg} and 
{\f1 endproc}. These are intended to be used for C-style procedure 
definitions, and they automate a lot of the work involved in keeping track 
of the calling convention.
\par\sb120
(An alternative, TASM compatible form of {\f1 arg} is also now built into 
NASM's preprocessor. See {\uldb section 4.9}{\v section_4_9} for details.)
\par\sb120
An example of an assembly function using the macro set is given here:
\par\sb120
\keep\f1\sb120
proc    _nearproc \par\sb0
\par\sb0
%$i     arg \par\sb0
%$j     arg \par\sb0
        mov     ax,[bp + %$i] \par\sb0
        mov     bx,[bp + %$j] \par\sb0
        add     ax,[bx] \par\sb0
\par\sb0
endproc\par\sb0
\pard\f0\sb120
This defines {\f1 _nearproc} to be a procedure taking two arguments, the 
first ({\f1 i}) an integer and the second ({\f1 j}) a pointer to an 
integer. It returns {\f1 i\'A0+\'A0*j}.
\par\sb120
Note that the {\f1 arg} macro has an {\f1 EQU} as the first line of its 
expansion, and since the label before the macro call gets prepended to the 
first line of the expanded macro, the {\f1 EQU} works, defining {\f1 %$i} 
to be an offset from {\f1 BP}. A context-local variable is used, local to 
the context pushed by the {\f1 proc} macro and popped by the {\f1 endproc} 
macro, so that the same argument name can be used in later procedures. Of 
course, you don't {\i have} to do that.
\par\sb120
The macro set produces code for near functions (tiny, small and 
compact-model code) by default. You can have it generate far functions 
(medium, large and huge-model code) by means of coding 
{\f1 %define\'A0FARCODE}. This changes the kind of return instruction 
generated by {\f1 endproc}, and also changes the starting point for the 
argument offsets. The macro set contains no intrinsic dependency on whether 
data pointers are far or not.
\par\sb120
{\f1 arg} can take an optional parameter, giving the size of the argument. 
If no size is given, 2 is assumed, since it is likely that many function 
parameters will be of type {\f1 int}.
\par\sb120
The large-model equivalent of the above function would look like this:
\par\sb120
\keep\f1\sb120
%define FARCODE \par\sb0
\par\sb0
proc    _farproc \par\sb0
\par\sb0
%$i     arg \par\sb0
%$j     arg     4 \par\sb0
        mov     ax,[bp + %$i] \par\sb0
        mov     bx,[bp + %$j] \par\sb0
        mov     es,[bp + %$j + 2] \par\sb0
        add     ax,[bx] \par\sb0
\par\sb0
endproc\par\sb0
\pard\f0\sb120
This makes use of the argument to the {\f1 arg} macro to define a parameter 
of size 4, because {\f1 j} is now a far pointer. When we load from {\f1 j}, 
we must load a segment and an offset.
\par\sb120
\page
#{\footnote section_7_5}
${\footnote 7.5. Interfacing to Borland Pascal Programs}
+{\footnote browse:00174}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_7')");
EnableButton("btn_up")}
K{\footnote Borland, Pascal}
\keepn\f2\b\fs30\sb60\sa60
7.5. Interfacing to Borland Pascal Programs
\par\pard\plain\sb120
Interfacing to Borland Pascal programs is similar in concept to interfacing 
to 16-bit C programs. The differences are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The leading underscore required for interfacing to C programs is not 
required for Pascal.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The memory model is always large: functions are far, data pointers are far, 
and no data item can be more than 64K long. (Actually, some functions are 
near, but only those functions that are local to a Pascal unit and never 
called from outside it. All assembly functions that Pascal calls, and all 
Pascal functions that assembly routines are able to call, are far.) 
However, all static data declared in a Pascal program goes into the default 
data segment, which is the one whose segment address will be in {\f1 DS} 
when control is passed to your assembly code. The only things that do not 
live in the default data segment are local variables (they live in the 
stack segment) and dynamically allocated variables. All data {\i pointers}, 
however, are far.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The function calling convention is different \'96 described below.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Some data types, such as strings, are stored differently.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
There are restrictions on the segment names you are allowed to use \'96 
Borland Pascal will ignore code or data declared in a segment it doesn't 
like the name of. The restrictions are described below.
\par\pard\sb120
\li360\fi-360
{\uldb Section 7.5.1: The Pascal Calling Convention}{\v section_7_5_1}\par\sb0
{\uldb Section 7.5.2: Borland Pascal Segment Name Restrictions}{\v section_7_5_2}\par\sb0
{\uldb Section 7.5.3: Using c16.mac With Pascal Programs}{\v section_7_5_3}\par\sb0
\pard\sb120
\page
#{\footnote section_7_5_1}
${\footnote 7.5.1. The Pascal Calling Convention}
+{\footnote browse:00175}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_5')");
EnableButton("btn_up")}
K{\footnote frame pointer;
functions, Pascal calling convention;
Pascal calling convention}
\keepn\f2\b\fs30\sb60\sa60
7.5.1. The Pascal Calling Convention
\par\pard\plain\sb120
The 16-bit Pascal calling convention is as follows. In the following 
description, the words {\i caller} and {\i callee} are used to denote the 
function doing the calling and the function which gets called.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The caller pushes the function's parameters on the stack, one after 
another, in normal order (left to right, so that the first argument 
specified to the function is pushed first).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The caller then executes a far {\f1 CALL} instruction to pass control to 
the callee.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee receives control, and typically (although this is not actually 
necessary, in functions which do not need to access their parameters) 
starts by saving the value of {\f1 SP} in {\f1 BP} so as to be able to use 
{\f1 BP} as a base pointer to find its parameters on the stack. However, 
the caller was probably doing this too, so part of the calling convention 
states that {\f1 BP} must be preserved by any function. Hence the callee, 
if it is going to set up {\f1 BP} as a frame pointer, must push the 
previous value first.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee may then access its parameters relative to {\f1 BP}. The word at 
{\f1 [BP]} holds the previous value of {\f1 BP} as it was pushed. The next 
word, at {\f1 [BP+2]}, holds the offset part of the return address, and the 
next one at {\f1 [BP+4]} the segment part. The parameters begin at 
{\f1 [BP+6]}. The rightmost parameter of the function, since it was pushed 
last, is accessible at this offset from {\f1 BP}; the others follow, at 
successively greater offsets.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee may also wish to decrease {\f1 SP} further, so as to allocate 
space on the stack for local variables, which will then be accessible at 
negative offsets from {\f1 BP}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee, if it wishes to return a value to the caller, should leave the 
value in {\f1 AL}, {\f1 AX} or {\f1 DX:AX} depending on the size of the 
value. Floating-point results are returned in {\f1 ST0}. Results of type 
{\f1 Real} (Borland's own custom floating-point data type, not handled 
directly by the FPU) are returned in {\f1 DX:BX:AX}. To return a result of 
type {\f1 String}, the caller pushes a pointer to a temporary string before 
pushing the parameters, and the callee places the returned string value at 
that location. The pointer is not a parameter, and should not be removed 
from the stack by the {\f1 RETF} instruction.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Once the callee has finished processing, it restores {\f1 SP} from {\f1 BP} 
if it had allocated local stack space, then pops the previous value of 
{\f1 BP}, and returns via {\f1 RETF}. It uses the form of {\f1 RETF} with 
an immediate parameter, giving the number of bytes taken up by the 
parameters on the stack. This causes the parameters to be removed from the 
stack as a side effect of the return instruction.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
When the caller regains control from the callee, the function parameters 
have already been removed from the stack, so it needs to do nothing 
further.
\par\pard\sb120
Thus, you would define a function in Pascal style, taking two 
{\f1 Integer}\'96type parameters, in the following way:
\par\sb120
\keep\f1\sb120
global  myfunc \par\sb0
\par\sb0
myfunc: push    bp \par\sb0
        mov     bp,sp \par\sb0
        sub     sp,0x40         ; 64 bytes of local stack space \par\sb0
        mov     bx,[bp+8]       ; first parameter to function \par\sb0
        mov     bx,[bp+6]       ; second parameter to function \par\sb0
\par\sb0
        ; some more code \par\sb0
\par\sb0
        mov     sp,bp           ; undo "sub sp,0x40" above \par\sb0
        pop     bp \par\sb0
        retf    4               ; total size of params is 4\par\sb0
\pard\f0\sb120
At the other end of the process, to call a Pascal function from your 
assembly code, you would do something like this:
\par\sb120
\keep\f1\sb120
extern  SomeFunc \par\sb0
\par\sb0
       ; and then, further down... \par\sb0
\par\sb0
       push   word seg mystring   ; Now push the segment, and... \par\sb0
       push   word mystring       ; ... offset of "mystring" \par\sb0
       push   word [myint]        ; one of my variables \par\sb0
       call   far SomeFunc\par\sb0
\pard\f0\sb120
This is equivalent to the Pascal code
\par\sb120
\keep\f1\sb120
procedure SomeFunc(String: PChar; Int: Integer); \par\sb0
    SomeFunc(@@mystring, myint);\par\sb0
\pard\f0\sb120
\page
#{\footnote section_7_5_2}
${\footnote 7.5.2. Borland Pascal Segment Name Restrictions}
+{\footnote browse:00176}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_5')");
EnableButton("btn_up")}
K{\footnote segment names, Borland Pascal}
\keepn\f2\b\fs30\sb60\sa60
7.5.2. Borland Pascal Segment Name Restrictions
\par\pard\plain\sb120
Since Borland Pascal's internal unit file format is completely different 
from {\f1 OBJ}, it only makes a very sketchy job of actually reading and 
understanding the various information contained in a real {\f1 OBJ} file 
when it links that in. Therefore an object file intended to be linked to a 
Pascal program must obey a number of restrictions:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Procedures and functions must be in a segment whose name is either 
{\f1 CODE}, {\f1 CSEG}, or something ending in {\f1 _TEXT}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Initialised data must be in a segment whose name is either {\f1 CONST} or 
something ending in {\f1 _DATA}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Uninitialised data must be in a segment whose name is either {\f1 DATA}, 
{\f1 DSEG}, or something ending in {\f1 _BSS}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Any other segments in the object file are completely ignored. {\f1 GROUP} 
directives and segment attributes are also ignored.
\par\pard\sb120
\page
#{\footnote section_7_5_3}
${\footnote 7.5.3. Using c16.mac With Pascal Programs}
+{\footnote browse:00177}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_7_5')");
EnableButton("btn_up")}
K{\footnote c16.mac;
FARCODE;
PASCAL}
\keepn\f2\b\fs30\sb60\sa60
7.5.3. Using {\f1 c16.mac} With Pascal Programs
\par\pard\plain\sb120
The {\f1 c16.mac} macro package, described in {\uldb section 
7.4.5}{\v section_7_4_5}, can also be used to simplify writing functions to 
be called from Pascal programs, if you code {\f1 %define\'A0PASCAL}. This 
definition ensures that functions are far (it implies {\f1 FARCODE}), and 
also causes procedure return instructions to be generated with an operand.
\par\sb120
Defining {\f1 PASCAL} does not change the code which calculates the 
argument offsets; you must declare your function's arguments in reverse 
order. For example:
\par\sb120
\keep\f1\sb120
%define PASCAL \par\sb0
\par\sb0
proc    _pascalproc \par\sb0
\par\sb0
%$j     arg 4 \par\sb0
%$i     arg \par\sb0
        mov     ax,[bp + %$i] \par\sb0
        mov     bx,[bp + %$j] \par\sb0
        mov     es,[bp + %$j + 2] \par\sb0
        add     ax,[bx] \par\sb0
\par\sb0
endproc\par\sb0
\pard\f0\sb120
This defines the same routine, conceptually, as the example in 
{\uldb section 7.4.5}{\v section_7_4_5}: it defines a function taking two 
arguments, an integer and a pointer to an integer, which returns the sum of 
the integer and the contents of the pointer. The only difference between 
this code and the large-model C version is that {\f1 PASCAL} is defined 
instead of {\f1 FARCODE}, and that the arguments are declared in reverse 
order.
\par\sb120
\page
#{\footnote chapter_8}
${\footnote Chapter 8: Writing 32-bit Code (Unix, Win32, DJGPP)}
+{\footnote browse:00178}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
K{\footnote DJGPP;
flat memory model;
Win32}
\keepn\f2\b\fs30\sb60\sa60
Chapter 8: Writing 32-bit Code (Unix, Win32, DJGPP)
\par\pard\plain\sb120
This chapter attempts to cover some of the common issues involved when 
writing 32-bit code, to run under Win32 or Unix, or to be linked with C 
code generated by a Unix-style C compiler such as DJGPP. It covers how to 
write assembly code to interface with 32-bit C routines, and how to write 
position-independent code for shared libraries.
\par\sb120
Almost all 32-bit code, and in particular all code running under 
{\f1 Win32}, {\f1 DJGPP} or any of the PC Unix variants, runs in {\i flat} 
memory model. This means that the segment registers and paging have already 
been set up to give you the same 32-bit 4Gb address space no matter what 
segment you work relative to, and that you should ignore all segment 
registers completely. When writing flat-model application code, you never 
need to use a segment override or modify any segment register, and the 
code-section addresses you pass to {\f1 CALL} and {\f1 JMP} live in the 
same address space as the data-section addresses you access your variables 
by and the stack-section addresses you access local variables and procedure 
parameters by. Every address is 32 bits long and contains only an offset 
part.
\par\sb120
\li360\fi-360
{\uldb Section 8.1: Interfacing to 32-bit C Programs}{\v section_8_1}\par\sb0
{\uldb Section 8.2: Writing NetBSD/FreeBSD/OpenBSD and Linux/ELF Shared Libraries}{\v section_8_2}\par\sb0
\pard\sb120
\page
#{\footnote section_8_1}
${\footnote 8.1. Interfacing to 32-bit C Programs}
+{\footnote browse:00179}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_8')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
8.1. Interfacing to 32-bit C Programs
\par\pard\plain\sb120
A lot of the discussion in {\uldb section 7.4}{\v section_7_4}, about 
interfacing to 16-bit C programs, still applies when working in 32 bits. 
The absence of memory models or segmentation worries simplifies things a 
lot.
\par\sb120
\li360\fi-360
{\uldb Section 8.1.1: External Symbol Names}{\v section_8_1_1}\par\sb0
{\uldb Section 8.1.2: Function Definitions and Function Calls}{\v section_8_1_2}\par\sb0
{\uldb Section 8.1.3: Accessing Data Items}{\v section_8_1_3}\par\sb0
{\uldb Section 8.1.4: c32.mac: Helper Macros for the 32-bit C Interface}{\v section_8_1_4}\par\sb0
\pard\sb120
\page
#{\footnote section_8_1_1}
${\footnote 8.1.1. External Symbol Names}
+{\footnote browse:00180}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_1')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
8.1.1. External Symbol Names
\par\pard\plain\sb120
Most 32-bit C compilers share the convention used by 16-bit compilers, that 
the names of all global symbols (functions or data) they define are formed 
by prefixing an underscore to the name as it appears in the C program. 
However, not all of them do: the {\f1 ELF} specification states that C 
symbols do {\i not} have a leading underscore on their assembly-language 
names.
\par\sb120
The older Linux {\f1 a.out} C compiler, all {\f1 Win32} compilers, 
{\f1 DJGPP}, and {\f1 NetBSD} and {\f1 FreeBSD}, all use the leading 
underscore; for these compilers, the macros {\f1 cextern} and 
{\f1 cglobal}, as given in {\uldb section 7.4.1}{\v section_7_4_1}, will 
still work. For {\f1 ELF}, though, the leading underscore should not be 
used.
\par\sb120
See also {\uldb section 2.1.21}{\v section_2_1_21}.
\par\sb120
\page
#{\footnote section_8_1_2}
${\footnote 8.1.2. Function Definitions and Function Calls}
+{\footnote browse:00181}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_1')");
EnableButton("btn_up")}
K{\footnote C calling convention;
frame pointer;
functions, C calling convention}
\keepn\f2\b\fs30\sb60\sa60
8.1.2. Function Definitions and Function Calls
\par\pard\plain\sb120
The C calling conventionThe C calling convention in 32-bit programs is as 
follows. In the following description, the words {\i caller} and 
{\i callee} are used to denote the function doing the calling and the 
function which gets called.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The caller pushes the function's parameters on the stack, one after 
another, in reverse order (right to left, so that the first argument 
specified to the function is pushed last).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The caller then executes a near {\f1 CALL} instruction to pass control to 
the callee.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee receives control, and typically (although this is not actually 
necessary, in functions which do not need to access their parameters) 
starts by saving the value of {\f1 ESP} in {\f1 EBP} so as to be able to 
use {\f1 EBP} as a base pointer to find its parameters on the stack. 
However, the caller was probably doing this too, so part of the calling 
convention states that {\f1 EBP} must be preserved by any C function. Hence 
the callee, if it is going to set up {\f1 EBP} as a frame pointer, must 
push the previous value first.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee may then access its parameters relative to {\f1 EBP}. The 
doubleword at {\f1 [EBP]} holds the previous value of {\f1 EBP} as it was 
pushed; the next doubleword, at {\f1 [EBP+4]}, holds the return address, 
pushed implicitly by {\f1 CALL}. The parameters start after that, at 
{\f1 [EBP+8]}. The leftmost parameter of the function, since it was pushed 
last, is accessible at this offset from {\f1 EBP}; the others follow, at 
successively greater offsets. Thus, in a function such as {\f1 printf} 
which takes a variable number of parameters, the pushing of the parameters 
in reverse order means that the function knows where to find its first 
parameter, which tells it the number and type of the remaining ones.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee may also wish to decrease {\f1 ESP} further, so as to allocate 
space on the stack for local variables, which will then be accessible at 
negative offsets from {\f1 EBP}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The callee, if it wishes to return a value to the caller, should leave the 
value in {\f1 AL}, {\f1 AX} or {\f1 EAX} depending on the size of the 
value. Floating-point results are typically returned in {\f1 ST0}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Once the callee has finished processing, it restores {\f1 ESP} from 
{\f1 EBP} if it had allocated local stack space, then pops the previous 
value of {\f1 EBP}, and returns via {\f1 RET} (equivalently, {\f1 RETN}).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
When the caller regains control from the callee, the function parameters 
are still on the stack, so it typically adds an immediate constant to 
{\f1 ESP} to remove them (instead of executing a number of slow {\f1 POP} 
instructions). Thus, if a function is accidentally called with the wrong 
number of parameters due to a prototype mismatch, the stack will still be 
returned to a sensible state since the caller, which {\i knows} how many 
parameters it pushed, does the removing.
\par\pard\sb120
There is an alternative calling convention used by Win32 programs for 
Windows API calls, and also for functions called {\i by} the Windows API 
such as window procedures: they follow what Microsoft calls the 
{\f1 __stdcall} convention. This is slightly closer to the Pascal 
convention, in that the callee clears the stack by passing a parameter to 
the {\f1 RET} instruction. However, the parameters are still pushed in 
right-to-left order.
\par\sb120
Thus, you would define a function in C style in the following way:
\par\sb120
\keep\f1\sb120
global  _myfunc \par\sb0
\par\sb0
_myfunc: \par\sb0
        push    ebp \par\sb0
        mov     ebp,esp \par\sb0
        sub     esp,0x40        ; 64 bytes of local stack space \par\sb0
        mov     ebx,[ebp+8]     ; first parameter to function \par\sb0
\par\sb0
        ; some more code \par\sb0
\par\sb0
        leave                   ; mov esp,ebp / pop ebp \par\sb0
        ret\par\sb0
\pard\f0\sb120
At the other end of the process, to call a C function from your assembly 
code, you would do something like this:
\par\sb120
\keep\f1\sb120
extern  _printf \par\sb0
\par\sb0
        ; and then, further down... \par\sb0
\par\sb0
        push    dword [myint]   ; one of my integer variables \par\sb0
        push    dword mystring  ; pointer into my data segment \par\sb0
        call    _printf \par\sb0
        add     esp,byte 8      ; `byte' saves space \par\sb0
\par\sb0
        ; then those data items... \par\sb0
\par\sb0
segment _DATA \par\sb0
\par\sb0
myint       dd   1234 \par\sb0
mystring    db   'This number -> %d <- should be 1234',10,0\par\sb0
\pard\f0\sb120
This piece of code is the assembly equivalent of the C code
\par\sb120
\keep\f1\sb120
    int myint = 1234; \par\sb0
    printf("This number -> %d <- should be 1234\\n", myint);\par\sb0
\pard\f0\sb120
\page
#{\footnote section_8_1_3}
${\footnote 8.1.3. Accessing Data Items}
+{\footnote browse:00182}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_1')");
EnableButton("btn_up")}
K{\footnote data structure;
STRUC}
\keepn\f2\b\fs30\sb60\sa60
8.1.3. Accessing Data Items
\par\pard\plain\sb120
To get at the contents of C variables, or to declare variables which C can 
access, you need only declare the names as {\f1 GLOBAL} or {\f1 EXTERN}. 
(Again, the names require leading underscores, as stated in {\uldb section 
8.1.1}{\v section_8_1_1}.) Thus, a C variable declared as {\f1 int\'A0i} 
can be accessed from assembler as
\par\sb120
\keep\f1\sb120
          extern _i \par\sb0
          mov eax,[_i]\par\sb0
\pard\f0\sb120
And to declare your own integer variable which C programs can access as 
{\f1 extern\'A0int\'A0j}, you do this (making sure you are assembling in 
the {\f1 _DATA} segment, if necessary):
\par\sb120
\keep\f1\sb120
          global _j \par\sb0
_j        dd 0\par\sb0
\pard\f0\sb120
To access a C array, you need to know the size of the components of the 
array. For example, {\f1 int} variables are four bytes long, so if a C 
program declares an array as {\f1 int\'A0a[10]}, you can access {\f1 a[3]} 
by coding {\f1 mov\'A0ax,[_a+12]}. (The byte offset 12 is obtained by 
multiplying the desired array index, 3, by the size of the array element, 
4.) The sizes of the C base types in 32-bit compilers are: 1 for 
{\f1 char}, 2 for {\f1 short}, 4 for {\f1 int}, {\f1 long} and {\f1 float}, 
and 8 for {\f1 double}. Pointers, being 32-bit addresses, are also 4 bytes 
long.
\par\sb120
To access a C data structure, you need to know the offset from the base of 
the structure to the field you are interested in. You can either do this by 
converting the C structure definition into a NASM structure definition 
(using {\f1 STRUC}), or by calculating the one offset and using just that.
\par\sb120
To do either of these, you should read your C compiler's manual to find out 
how it organises data structures. NASM gives no special alignment to 
structure members in its own {\f1 STRUC} macro, so you have to specify 
alignment yourself if the C compiler generates it. Typically, you might 
find that a structure like
\par\sb120
\keep\f1\sb120
struct @\{ \par\sb0
    char c; \par\sb0
    int i; \par\sb0
@\} foo;\par\sb0
\pard\f0\sb120
might be eight bytes long rather than five, since the {\f1 int} field would 
be aligned to a four-byte boundary. However, this sort of feature is 
sometimes a configurable option in the C compiler, either using 
command-line options or {\f1 #pragma} lines, so you have to find out how 
your own compiler does it.
\par\sb120
\page
#{\footnote section_8_1_4}
${\footnote 8.1.4. c32.mac: Helper Macros for the 32-bit C Interface}
+{\footnote browse:00183}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_1')");
EnableButton("btn_up")}
K{\footnote arg;
c32.mac;
endproc;
misc subdirectory;
proc}
\keepn\f2\b\fs30\sb60\sa60
8.1.4. {\f1 c32.mac}: Helper Macros for the 32-bit C Interface
\par\pard\plain\sb120
Included in the NASM archives, in the {\f1 misc} directory, is a file 
{\f1 c32.mac} of macros. It defines three macros: {\f1 proc}, {\f1 arg} and 
{\f1 endproc}. These are intended to be used for C-style procedure 
definitions, and they automate a lot of the work involved in keeping track 
of the calling convention.
\par\sb120
An example of an assembly function using the macro set is given here:
\par\sb120
\keep\f1\sb120
proc    _proc32 \par\sb0
\par\sb0
%$i     arg \par\sb0
%$j     arg \par\sb0
        mov     eax,[ebp + %$i] \par\sb0
        mov     ebx,[ebp + %$j] \par\sb0
        add     eax,[ebx] \par\sb0
\par\sb0
endproc\par\sb0
\pard\f0\sb120
This defines {\f1 _proc32} to be a procedure taking two arguments, the 
first ({\f1 i}) an integer and the second ({\f1 j}) a pointer to an 
integer. It returns {\f1 i\'A0+\'A0*j}.
\par\sb120
Note that the {\f1 arg} macro has an {\f1 EQU} as the first line of its 
expansion, and since the label before the macro call gets prepended to the 
first line of the expanded macro, the {\f1 EQU} works, defining {\f1 %$i} 
to be an offset from {\f1 BP}. A context-local variable is used, local to 
the context pushed by the {\f1 proc} macro and popped by the {\f1 endproc} 
macro, so that the same argument name can be used in later procedures. Of 
course, you don't {\i have} to do that.
\par\sb120
{\f1 arg} can take an optional parameter, giving the size of the argument. 
If no size is given, 4 is assumed, since it is likely that many function 
parameters will be of type {\f1 int} or pointers.
\par\sb120
\page
#{\footnote section_8_2}
${\footnote 8.2. Writing NetBSD/FreeBSD/OpenBSD and Linux/ELF Shared Libraries}
+{\footnote browse:00184}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_8')");
EnableButton("btn_up")}
K{\footnote aoutb;
BSD;
FreeBSD;
global offset table;
GOT;
NetBSD;
OpenBSD;
PIC;
position\'ADindependent code;
shared libraries}
\keepn\f2\b\fs30\sb60\sa60
8.2. Writing NetBSD/FreeBSD/OpenBSD and Linux/ELF Shared Libraries
\par\pard\plain\sb120
{\f1 ELF} replaced the older {\f1 a.out} object file format under Linux 
because it contains support for position\'ADindependent code (PIC), which 
makes writing shared libraries much easier. NASM supports the {\f1 ELF} 
position-independent code features, so you can write Linux {\f1 ELF} shared 
libraries in NASM.
\par\sb120
NetBSD, and its close cousins FreeBSD and OpenBSD, take a different 
approach by hacking PIC support into the {\f1 a.out} format. NASM supports 
this as the {\f1 aoutb} output format, so you can write BSD shared 
libraries in NASM too.
\par\sb120
The operating system loads a PIC shared library by memory-mapping the 
library file at an arbitrarily chosen point in the address space of the 
running process. The contents of the library's code section must therefore 
not depend on where it is loaded in memory.
\par\sb120
Therefore, you cannot get at your variables by writing code like this:
\par\sb120
\keep\f1\sb120
        mov     eax,[myvar]             ; WRONG\par\sb0
\pard\f0\sb120
Instead, the linker provides an area of memory called the {\i global offset 
table}, or GOT; the GOT is situated at a constant distance from your 
library's code, so if you can find out where your library is loaded (which 
is typically done using a {\f1 CALL} and {\f1 POP} combination), you can 
obtain the address of the GOT, and you can then load the addresses of your 
variables out of linker-generated entries in the GOT.
\par\sb120
The {\i data} section of a PIC shared library does not have these 
restrictions: since the data section is writable, it has to be copied into 
memory anyway rather than just paged in from the library file, so as long 
as it's being copied it can be relocated too. So you can put ordinary types 
of relocation in the data section without too much worry (but see 
{\uldb section 8.2.4}{\v section_8_2_4} for a caveat).
\par\sb120
\li360\fi-360
{\uldb Section 8.2.1: Obtaining the Address of the GOT}{\v section_8_2_1}\par\sb0
{\uldb Section 8.2.2: Finding Your Local Data Items}{\v section_8_2_2}\par\sb0
{\uldb Section 8.2.3: Finding External and Common Data Items}{\v section_8_2_3}\par\sb0
{\uldb Section 8.2.4: Exporting Symbols to the Library User}{\v section_8_2_4}\par\sb0
{\uldb Section 8.2.5: Calling Procedures Outside the Library}{\v section_8_2_5}\par\sb0
{\uldb Section 8.2.6: Generating the Library File}{\v section_8_2_6}\par\sb0
\pard\sb120
\page
#{\footnote section_8_2_1}
${\footnote 8.2.1. Obtaining the Address of the GOT}
+{\footnote browse:00185}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_2')");
EnableButton("btn_up")}
K{\footnote GOTPC relocations;
WRT\'A0..gotpc}
\keepn\f2\b\fs30\sb60\sa60
8.2.1. Obtaining the Address of the GOT
\par\pard\plain\sb120
Each code module in your shared library should define the GOT as an 
external symbol:
\par\sb120
\keep\f1\sb120
extern  _GLOBAL_OFFSET_TABLE_   ; in ELF \par\sb0
extern  __GLOBAL_OFFSET_TABLE_  ; in BSD a.out\par\sb0
\pard\f0\sb120
At the beginning of any function in your shared library which plans to 
access your data or BSS sections, you must first calculate the address of 
the GOT. This is typically done by writing the function in this form:
\par\sb120
\keep\f1\sb120
func:   push    ebp \par\sb0
        mov     ebp,esp \par\sb0
        push    ebx \par\sb0
        call    .get_GOT \par\sb0
.get_GOT: \par\sb0
        pop     ebx \par\sb0
        add     ebx,_GLOBAL_OFFSET_TABLE_+$$-.get_GOT wrt ..gotpc \par\sb0
\par\sb0
        ; the function body comes here \par\sb0
\par\sb0
        mov     ebx,[ebp-4] \par\sb0
        mov     esp,ebp \par\sb0
        pop     ebp \par\sb0
        ret\par\sb0
\pard\f0\sb120
(For BSD, again, the symbol {\f1 _GLOBAL_OFFSET_TABLE} requires a second 
leading underscore.)
\par\sb120
The first two lines of this function are simply the standard C prologue to 
set up a stack frame, and the last three lines are standard C function 
epilogue. The third line, and the fourth to last line, save and restore the 
{\f1 EBX} register, because PIC shared libraries use this register to store 
the address of the GOT.
\par\sb120
The interesting bit is the {\f1 CALL} instruction and the following two 
lines. The {\f1 CALL} and {\f1 POP} combination obtains the address of the 
label {\f1 .get_GOT}, without having to know in advance where the program 
was loaded (since the {\f1 CALL} instruction is encoded relative to the 
current position). The {\f1 ADD} instruction makes use of one of the 
special PIC relocation types: GOTPC relocation. With the 
{\f1 WRT\'A0..gotpc} qualifier specified, the symbol referenced (here 
{\f1 _GLOBAL_OFFSET_TABLE_}, the special symbol assigned to the GOT) is 
given as an offset from the beginning of the section. (Actually, {\f1 ELF} 
encodes it as the offset from the operand field of the {\f1 ADD} 
instruction, but NASM simplifies this deliberately, so you do things the 
same way for both {\f1 ELF} and {\f1 BSD}.) So the instruction then 
{\i adds} the beginning of the section, to get the real address of the GOT, 
and subtracts the value of {\f1 .get_GOT} which it knows is in {\f1 EBX}. 
Therefore, by the time that instruction has finished, {\f1 EBX} contains 
the address of the GOT.
\par\sb120
If you didn't follow that, don't worry: it's never necessary to obtain the 
address of the GOT by any other means, so you can put those three 
instructions into a macro and safely ignore them:
\par\sb120
\keep\f1\sb120
%macro  get_GOT 0 \par\sb0
\par\sb0
        call    %%getgot \par\sb0
  %%getgot: \par\sb0
        pop     ebx \par\sb0
        add     ebx,_GLOBAL_OFFSET_TABLE_+$$-%%getgot wrt ..gotpc \par\sb0
\par\sb0
%endmacro\par\sb0
\pard\f0\sb120
\page
#{\footnote section_8_2_2}
${\footnote 8.2.2. Finding Your Local Data Items}
+{\footnote browse:00186}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_2')");
EnableButton("btn_up")}
K{\footnote GOTOFF relocations;
WRT\'A0..gotoff}
\keepn\f2\b\fs30\sb60\sa60
8.2.2. Finding Your Local Data Items
\par\pard\plain\sb120
Having got the GOT, you can then use it to obtain the addresses of your 
data items. Most variables will reside in the sections you have declared; 
they can be accessed using the {\f1 ..gotoff} special {\f1 WRT} type. The 
way this works is like this:
\par\sb120
\keep\f1\sb120
        lea     eax,[ebx+myvar wrt ..gotoff]\par\sb0
\pard\f0\sb120
The expression {\f1 myvar\'A0wrt\'A0..gotoff} is calculated, when the 
shared library is linked, to be the offset to the local variable 
{\f1 myvar} from the beginning of the GOT. Therefore, adding it to 
{\f1 EBX} as above will place the real address of {\f1 myvar} in {\f1 EAX}.
\par\sb120
If you declare variables as {\f1 GLOBAL} without specifying a size for 
them, they are shared between code modules in the library, but do not get 
exported from the library to the program that loaded it. They will still be 
in your ordinary data and BSS sections, so you can access them in the same 
way as local variables, using the above {\f1 ..gotoff} mechanism.
\par\sb120
Note that due to a peculiarity of the way BSD {\f1 a.out} format handles 
this relocation type, there must be at least one non-local symbol in the 
same section as the address you're trying to access.
\par\sb120
\page
#{\footnote section_8_2_3}
${\footnote 8.2.3. Finding External and Common Data Items}
+{\footnote browse:00187}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_2')");
EnableButton("btn_up")}
K{\footnote GOT relocations;
WRT\'A0..got}
\keepn\f2\b\fs30\sb60\sa60
8.2.3. Finding External and Common Data Items
\par\pard\plain\sb120
If your library needs to get at an external variable (external to the 
{\i library}, not just to one of the modules within it), you must use the 
{\f1 ..got} type to get at it. The {\f1 ..got} type, instead of giving you 
the offset from the GOT base to the variable, gives you the offset from the 
GOT base to a GOT {\i entry} containing the address of the variable. The 
linker will set up this GOT entry when it builds the library, and the 
dynamic linker will place the correct address in it at load time. So to 
obtain the address of an external variable {\f1 extvar} in {\f1 EAX}, you 
would code
\par\sb120
\keep\f1\sb120
        mov     eax,[ebx+extvar wrt ..got]\par\sb0
\pard\f0\sb120
This loads the address of {\f1 extvar} out of an entry in the GOT. The 
linker, when it builds the shared library, collects together every 
relocation of type {\f1 ..got}, and builds the GOT so as to ensure it has 
every necessary entry present.
\par\sb120
Common variables must also be accessed in this way.
\par\sb120
\page
#{\footnote section_8_2_4}
${\footnote 8.2.4. Exporting Symbols to the Library User}
+{\footnote browse:00188}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_2')");
EnableButton("btn_up")}
K{\footnote PLT relocations;
procedure linkage table;
WRT\'A0..sym}
\keepn\f2\b\fs30\sb60\sa60
8.2.4. Exporting Symbols to the Library User
\par\pard\plain\sb120
If you want to export symbols to the user of the library, you have to 
declare whether they are functions or data, and if they are data, you have 
to give the size of the data item. This is because the dynamic linker has 
to build procedure linkage table entries for any exported functions, and 
also moves exported data items away from the library's data section in 
which they were declared.
\par\sb120
So to export a function to users of the library, you must use
\par\sb120
\keep\f1\sb120
global  func:function           ; declare it as a function \par\sb0
\par\sb0
func:   push    ebp \par\sb0
\par\sb0
        ; etc.\par\sb0
\pard\f0\sb120
And to export a data item such as an array, you would have to code
\par\sb120
\keep\f1\sb120
global  array:data array.end-array      ; give the size too \par\sb0
\par\sb0
array:  resd    128 \par\sb0
.end:\par\sb0
\pard\f0\sb120
Be careful: If you export a variable to the library user, by declaring it 
as {\f1 GLOBAL} and supplying a size, the variable will end up living in 
the data section of the main program, rather than in your library's data 
section, where you declared it. So you will have to access your own global 
variable with the {\f1 ..got} mechanism rather than {\f1 ..gotoff}, as if 
it were external (which, effectively, it has become).
\par\sb120
Equally, if you need to store the address of an exported global in one of 
your data sections, you can't do it by means of the standard sort of code:
\par\sb120
\keep\f1\sb120
dataptr:        dd      global_data_item        ; WRONG\par\sb0
\pard\f0\sb120
NASM will interpret this code as an ordinary relocation, in which 
{\f1 global_data_item} is merely an offset from the beginning of the 
{\f1 .data} section (or whatever); so this reference will end up pointing 
at your data section instead of at the exported global which resides 
elsewhere.
\par\sb120
Instead of the above code, then, you must write
\par\sb120
\keep\f1\sb120
dataptr:        dd      global_data_item wrt ..sym\par\sb0
\pard\f0\sb120
which makes use of the special {\f1 WRT} type {\f1 ..sym} to instruct NASM 
to search the symbol table for a particular symbol at that address, rather 
than just relocating by section base.
\par\sb120
Either method will work for functions: referring to one of your functions 
by means of
\par\sb120
\keep\f1\sb120
funcptr:        dd      my_function\par\sb0
\pard\f0\sb120
will give the user the address of the code you wrote, whereas
\par\sb120
\keep\f1\sb120
funcptr:        dd      my_function wrt .sym\par\sb0
\pard\f0\sb120
will give the address of the procedure linkage table for the function, 
which is where the calling program will {\i believe} the function lives. 
Either address is a valid way to call the function.
\par\sb120
\page
#{\footnote section_8_2_5}
${\footnote 8.2.5. Calling Procedures Outside the Library}
+{\footnote browse:00189}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_2')");
EnableButton("btn_up")}
K{\footnote PLT relocations;
plt relocations;
procedure linkage table;
WRT\'A0..plt}
\keepn\f2\b\fs30\sb60\sa60
8.2.5. Calling Procedures Outside the Library
\par\pard\plain\sb120
Calling procedures outside your shared library has to be done by means of a 
{\i procedure linkage table}, or PLT. The PLT is placed at a known offset 
from where the library is loaded, so the library code can make calls to the 
PLT in a position-independent way. Within the PLT there is code to jump to 
offsets contained in the GOT, so function calls to other shared libraries 
or to routines in the main program can be transparently passed off to their 
real destinations.
\par\sb120
To call an external routine, you must use another special PIC relocation 
type, {\f1 WRT\'A0..plt}. This is much easier than the GOT-based ones: you 
simply replace calls such as {\f1 CALL\'A0printf} with the PLT-relative 
version {\f1 CALL\'A0printf\'A0WRT\'A0..plt}.
\par\sb120
\page
#{\footnote section_8_2_6}
${\footnote 8.2.6. Generating the Library File}
+{\footnote browse:00190}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_8_2')");
EnableButton("btn_up")}
K{\footnote \'ADsoname}
\keepn\f2\b\fs30\sb60\sa60
8.2.6. Generating the Library File
\par\pard\plain\sb120
Having written some code modules and assembled them to {\f1 .o} files, you 
then generate your shared library with a command such as
\par\sb120
\keep\f1\sb120
ld -shared -o library.so module1.o module2.o       # for ELF \par\sb0
ld -Bshareable -o library.so module1.o module2.o   # for BSD\par\sb0
\pard\f0\sb120
For ELF, if your shared library is going to reside in system directories 
such as {\f1 /usr/lib} or {\f1 /lib}, it is usually worth using the 
{\f1 \'ADsoname} flag to the linker, to store the final library file name, 
with a version number, into the library:
\par\sb120
\keep\f1\sb120
ld -shared -soname library.so.1 -o library.so.1.2 *.o\par\sb0
\pard\f0\sb120
You would then copy {\f1 library.so.1.2} into the library directory, and 
create {\f1 library.so.1} as a symbolic link to it.
\par\sb120
\page
#{\footnote chapter_9}
${\footnote Chapter 9: Mixing 16 and 32 Bit Code}
+{\footnote browse:00191}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
Chapter 9: Mixing 16 and 32 Bit Code
\par\pard\plain\sb120
This chapter tries to cover some of the issues, largely related to unusual 
forms of addressing and jump instructions, encountered when writing 
operating system code such as protected-mode initialisation routines, which 
require code that operates in mixed segment sizes, such as code in a 16-bit 
segment trying to modify data in a 32-bit one, or jumps between 
different-size segments.
\par\sb120
\li360\fi-360
{\uldb Section 9.1: Mixed-Size Jumps}{\v section_9_1}\par\sb0
{\uldb Section 9.2: Addressing Between Different-Size Segments}{\v section_9_2}\par\sb0
{\uldb Section 9.3: Other Mixed-Size Instructions}{\v section_9_3}\par\sb0
\pard\sb120
\page
#{\footnote section_9_1}
${\footnote 9.1. Mixed-Size Jumps}
+{\footnote browse:00192}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_9')");
EnableButton("btn_up")}
K{\footnote JMP\'A0DWORD;
jumps, mixed\'ADsize;
mixed\'ADsize instruction;
operating system, writing;
writing operating systems}
\keepn\f2\b\fs30\sb60\sa60
9.1. Mixed-Size Jumps
\par\pard\plain\sb120
The most common form of mixed\'ADsize instruction is the one used when 
writing a 32-bit OS: having done your setup in 16-bit mode, such as loading 
the kernel, you then have to boot it by switching into protected mode and 
jumping to the 32-bit kernel start address. In a fully 32-bit OS, this 
tends to be the {\i only} mixed-size instruction you need, since everything 
before it can be done in pure 16-bit code, and everything after it can be 
pure 32-bit.
\par\sb120
This jump must specify a 48-bit far address, since the target segment is a 
32-bit one. However, it must be assembled in a 16-bit segment, so just 
coding, for example,
\par\sb120
\keep\f1\sb120
        jmp     0x1234:0x56789ABC       ; wrong!\par\sb0
\pard\f0\sb120
will not work, since the offset part of the address will be truncated to 
{\f1 0x9ABC} and the jump will be an ordinary 16-bit far one.
\par\sb120
The Linux kernel setup code gets round the inability of {\f1 as86} to 
generate the required instruction by coding it manually, using {\f1 DB} 
instructions. NASM can go one better than that, by actually generating the 
right instruction itself. Here's how to do it right:
\par\sb120
\keep\f1\sb120
        jmp     dword 0x1234:0x56789ABC         ; right\par\sb0
\pard\f0\sb120
The {\f1 DWORD} prefix (strictly speaking, it should come {\i after} the 
colon, since it is declaring the {\i offset} field to be a doubleword; but 
NASM will accept either form, since both are unambiguous) forces the offset 
part to be treated as far, in the assumption that you are deliberately 
writing a jump from a 16-bit segment to a 32-bit one.
\par\sb120
You can do the reverse operation, jumping from a 32-bit segment to a 16-bit 
one, by means of the {\f1 WORD} prefix:
\par\sb120
\keep\f1\sb120
        jmp     word 0x8765:0x4321      ; 32 to 16 bit\par\sb0
\pard\f0\sb120
If the {\f1 WORD} prefix is specified in 16-bit mode, or the {\f1 DWORD} 
prefix in 32-bit mode, they will be ignored, since each is explicitly 
forcing NASM into a mode it was in anyway.
\par\sb120
\page
#{\footnote section_9_2}
${\footnote 9.2. Addressing Between Different-Size Segments}
+{\footnote browse:00193}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_9')");
EnableButton("btn_up")}
K{\footnote addressing, mixed\'ADsize;
mixed\'ADsize addressing}
\keepn\f2\b\fs30\sb60\sa60
9.2. Addressing Between Different-Size Segments
\par\pard\plain\sb120
If your OS is mixed 16 and 32-bit, or if you are writing a DOS extender, 
you are likely to have to deal with some 16-bit segments and some 32-bit 
ones. At some point, you will probably end up writing code in a 16-bit 
segment which has to access data in a 32-bit segment, or vice versa.
\par\sb120
If the data you are trying to access in a 32-bit segment lies within the 
first 64K of the segment, you may be able to get away with using an 
ordinary 16-bit addressing operation for the purpose; but sooner or later, 
you will want to do 32-bit addressing from 16-bit mode.
\par\sb120
The easiest way to do this is to make sure you use a register for the 
address, since any effective address containing a 32-bit register is forced 
to be a 32-bit address. So you can do
\par\sb120
\keep\f1\sb120
        mov     eax,offset_into_32_bit_segment_specified_by_fs \par\sb0
        mov     dword [fs:eax],0x11223344\par\sb0
\pard\f0\sb120
This is fine, but slightly cumbersome (since it wastes an instruction and a 
register) if you already know the precise offset you are aiming at. The x86 
architecture does allow 32-bit effective addresses to specify nothing but a 
4-byte offset, so why shouldn't NASM be able to generate the best 
instruction for the purpose?
\par\sb120
It can. As in {\uldb section 9.1}{\v section_9_1}, you need only prefix the 
address with the {\f1 DWORD} keyword, and it will be forced to be a 32-bit 
address:
\par\sb120
\keep\f1\sb120
        mov     dword [fs:dword my_offset],0x11223344\par\sb0
\pard\f0\sb120
Also as in {\uldb section 9.1}{\v section_9_1}, NASM is not fussy about 
whether the {\f1 DWORD} prefix comes before or after the segment override, 
so arguably a nicer-looking way to code the above instruction is
\par\sb120
\keep\f1\sb120
        mov     dword [dword fs:my_offset],0x11223344\par\sb0
\pard\f0\sb120
Don't confuse the {\f1 DWORD} prefix {\i outside} the square brackets, 
which controls the size of the data stored at the address, with the one 
{\f1 inside} the square brackets which controls the length of the address 
itself. The two can quite easily be different:
\par\sb120
\keep\f1\sb120
        mov     word [dword 0x12345678],0x9ABC\par\sb0
\pard\f0\sb120
This moves 16 bits of data to an address specified by a 32-bit offset.
\par\sb120
You can also specify {\f1 WORD} or {\f1 DWORD} prefixes along with the 
{\f1 FAR} prefix to indirect far jumps or calls. For example:
\par\sb120
\keep\f1\sb120
        call    dword far [fs:word 0x4321]\par\sb0
\pard\f0\sb120
This instruction contains an address specified by a 16-bit offset; it loads 
a 48-bit far pointer from that (16-bit segment and 32-bit offset), and 
calls that address.
\par\sb120
\page
#{\footnote section_9_3}
${\footnote 9.3. Other Mixed-Size Instructions}
+{\footnote browse:00194}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_9')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
o16;
o32}
\keepn\f2\b\fs30\sb60\sa60
9.3. Other Mixed-Size Instructions
\par\pard\plain\sb120
The other way you might want to access data might be using the string 
instructions ({\f1 LODSx}, {\f1 STOSx} and so on) or the {\f1 XLATB} 
instruction. These instructions, since they take no parameters, might seem 
to have no easy way to make them perform 32-bit addressing when assembled 
in a 16-bit segment.
\par\sb120
This is the purpose of NASM's {\f1 a16} and {\f1 a32} prefixes. If you are 
coding {\f1 LODSB} in a 16-bit segment but it is supposed to be accessing a 
string in a 32-bit segment, you should load the desired address into 
{\f1 ESI} and then code
\par\sb120
\keep\f1\sb120
        a32     lodsb\par\sb0
\pard\f0\sb120
The prefix forces the addressing size to 32 bits, meaning that {\f1 LODSB} 
loads from {\f1 [DS:ESI]} instead of {\f1 [DS:SI]}. To access a string in a 
16-bit segment when coding in a 32-bit one, the corresponding {\f1 a16} 
prefix can be used.
\par\sb120
The {\f1 a16} and {\f1 a32} prefixes can be applied to any instruction in 
NASM's instruction table, but most of them can generate all the useful 
forms without them. The prefixes are necessary only for instructions with 
implicit addressing: {\f1 CMPSx} ({\uldb section 
B.4.27}{\v section_b_4_27}), {\f1 SCASx} ({\uldb section 
B.4.286}{\v section_b_4_286}), {\f1 LODSx} ({\uldb section 
B.4.141}{\v section_b_4_141}), {\f1 STOSx} ({\uldb section 
B.4.303}{\v section_b_4_303}), {\f1 MOVSx} ({\uldb section 
B.4.178}{\v section_b_4_178}), {\f1 INSx} ({\uldb section 
B.4.121}{\v section_b_4_121}), {\f1 OUTSx} ({\uldb section 
B.4.195}{\v section_b_4_195}), and {\f1 XLATB} ({\uldb section 
B.4.334}{\v section_b_4_334}). Also, the various push and pop instructions 
({\f1 PUSHA} and {\f1 POPF} as well as the more usual {\f1 PUSH} and 
{\f1 POP}) can accept {\f1 a16} or {\f1 a32} prefixes to force a particular 
one of {\f1 SP} or {\f1 ESP} to be used as a stack pointer, in case the 
stack segment in use is a different size from the code segment.
\par\sb120
{\f1 PUSH} and {\f1 POP}, when applied to segment registers in 32-bit mode, 
also have the slightly odd behaviour that they push and pop 4 bytes at a 
time, of which the top two are ignored and the bottom two give the value of 
the segment register being manipulated. To force the 16-bit behaviour of 
segment-register push and pop instructions, you can use the operand-size 
prefix {\f1 o16}:
\par\sb120
\keep\f1\sb120
        o16 push    ss \par\sb0
        o16 push    ds\par\sb0
\pard\f0\sb120
This code saves a doubleword of stack space by fitting two segment 
registers into the space which would normally be consumed by pushing one.
\par\sb120
(You can also use the {\f1 o32} prefix to force the 32-bit behaviour when 
in 16-bit mode, but this seems less useful.)
\par\sb120
\page
#{\footnote chapter_10}
${\footnote Chapter 10: Troubleshooting}
+{\footnote browse:00195}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
Chapter 10: Troubleshooting
\par\pard\plain\sb120
This chapter describes some of the common problems that users have been 
known to encounter with NASM, and answers them. It also gives instructions 
for reporting bugs in NASM if you find a difficulty that isn't listed here.
\par\sb120
\li360\fi-360
{\uldb Section 10.1: Common Problems}{\v section_10_1}\par\sb0
{\uldb Section 10.2: Bugs}{\v section_10_2}\par\sb0
\pard\sb120
\page
#{\footnote section_10_1}
${\footnote 10.1. Common Problems}
+{\footnote browse:00196}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_10')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
10.1. Common Problems
\par\pard\plain\sb120
\li360\fi-360
{\uldb Section 10.1.1: NASM Generates Inefficient Code}{\v section_10_1_1}\par\sb0
{\uldb Section 10.1.2: My Jumps are Out of Range}{\v section_10_1_2}\par\sb0
{\uldb Section 10.1.3: ORG Doesn't Work}{\v section_10_1_3}\par\sb0
{\uldb Section 10.1.4: TIMES Doesn't Work}{\v section_10_1_4}\par\sb0
\pard\sb120
\page
#{\footnote section_10_1_1}
${\footnote 10.1.1. NASM Generates Inefficient Code}
+{\footnote browse:00197}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_10_1')");
EnableButton("btn_up")}
K{\footnote BYTE;
inefficient code}
\keepn\f2\b\fs30\sb60\sa60
10.1.1. NASM Generates Inefficient Code
\par\pard\plain\sb120
We sometimes get `bug' reports about NASM generating inefficient, or even 
`wrong', code on instructions such as {\f1 ADD\'A0ESP,8}. This is a 
deliberate design feature, connected to predictability of output: NASM, on 
seeing {\f1 ADD\'A0ESP,8}, will generate the form of the instruction which 
leaves room for a 32-bit offset. You need to code 
{\f1 ADD\'A0ESP,BYTE\'A08} if you want the space-efficient form of the 
instruction. This isn't a bug, it's user error: if you prefer to have NASM 
produce the more efficient code automatically enable optimization with the 
{\f1 \'ADOn} option (see {\uldb section 2.1.16}{\v section_2_1_16}).
\par\sb120
\page
#{\footnote section_10_1_2}
${\footnote 10.1.2. My Jumps are Out of Range}
+{\footnote browse:00198}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_10_1')");
EnableButton("btn_up")}
K{\footnote conditional jumps;
Jcc\'A0NEAR;
out of range, jumps}
\keepn\f2\b\fs30\sb60\sa60
10.1.2. My Jumps are Out of Range
\par\pard\plain\sb120
Similarly, people complain that when they issue conditional jumps (which 
are {\f1 SHORT} by default) that try to jump too far, NASM reports `short 
jump out of range' instead of making the jumps longer.
\par\sb120
This, again, is partly a predictability issue, but in fact has a more 
practical reason as well. NASM has no means of being told what type of 
processor the code it is generating will be run on; so it cannot decide for 
itself that it should generate {\f1 Jcc\'A0NEAR} type instructions, because 
it doesn't know that it's working for a 386 or above. Alternatively, it 
could replace the out-of-range short {\f1 JNE} instruction with a very 
short {\f1 JE} instruction that jumps over a {\f1 JMP\'A0NEAR}; this is a 
sensible solution for processors below a 386, but hardly efficient on 
processors which have good branch prediction {\i and} could have used 
{\f1 JNE\'A0NEAR} instead. So, once again, it's up to the user, not the 
assembler, to decide what instructions should be generated. See 
{\uldb section 2.1.16}{\v section_2_1_16}.
\par\sb120
\page
#{\footnote section_10_1_3}
${\footnote 10.1.3. ORG Doesn't Work}
+{\footnote browse:00199}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_10_1')");
EnableButton("btn_up")}
K{\footnote boot sector;
ORG;
TIMES}
\keepn\f2\b\fs30\sb60\sa60
10.1.3. {\f1 ORG} Doesn't Work
\par\pard\plain\sb120
People writing boot sector programs in the {\f1 bin} format often complain 
that {\f1 ORG} doesn't work the way they'd like: in order to place the 
{\f1 0xAA55} signature word at the end of a 512-byte boot sector, people 
who are used to MASM tend to code
\par\sb120
\keep\f1\sb120
        ORG 0 \par\sb0
\par\sb0
        ; some boot sector code \par\sb0
\par\sb0
        ORG 510 \par\sb0
        DW 0xAA55\par\sb0
\pard\f0\sb120
This is not the intended use of the {\f1 ORG} directive in NASM, and will 
not work. The correct way to solve this problem in NASM is to use the 
{\f1 TIMES} directive, like this:
\par\sb120
\keep\f1\sb120
        ORG 0 \par\sb0
\par\sb0
        ; some boot sector code \par\sb0
\par\sb0
        TIMES 510-($-$$) DB 0 \par\sb0
        DW 0xAA55\par\sb0
\pard\f0\sb120
The {\f1 TIMES} directive will insert exactly enough zero bytes into the 
output to move the assembly point up to 510. This method also has the 
advantage that if you accidentally fill your boot sector too full, NASM 
will catch the problem at assembly time and report it, so you won't end up 
with a boot sector that you have to disassemble to find out what's wrong 
with it.
\par\sb120
\page
#{\footnote section_10_1_4}
${\footnote 10.1.4. TIMES Doesn't Work}
+{\footnote browse:00200}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_10_1')");
EnableButton("btn_up")}
K{\footnote TIMES}
\keepn\f2\b\fs30\sb60\sa60
10.1.4. {\f1 TIMES} Doesn't Work
\par\pard\plain\sb120
The other common problem with the above code is people who write the 
{\f1 TIMES} line as
\par\sb120
\keep\f1\sb120
        TIMES 510-$ DB 0\par\sb0
\pard\f0\sb120
by reasoning that {\f1 $} should be a pure number, just like 510, so the 
difference between them is also a pure number and can happily be fed to 
{\f1 TIMES}.
\par\sb120
NASM is a {\i modular} assembler: the various component parts are designed 
to be easily separable for re-use, so they don't exchange information 
unnecessarily. In consequence, the {\f1 bin} output format, even though it 
has been told by the {\f1 ORG} directive that the {\f1 .text} section 
should start at 0, does not pass that information back to the expression 
evaluator. So from the evaluator's point of view, {\f1 $} isn't a pure 
number: it's an offset from a section base. Therefore the difference 
between {\f1 $} and 510 is also not a pure number, but involves a section 
base. Values involving section bases cannot be passed as arguments to 
{\f1 TIMES}.
\par\sb120
The solution, as in the previous section, is to code the {\f1 TIMES} line 
in the form
\par\sb120
\keep\f1\sb120
        TIMES 510-($-$$) DB 0\par\sb0
\pard\f0\sb120
in which {\f1 $} and {\f1 $$} are offsets from the same section base, and 
so their difference is a pure number. This will solve the problem and 
generate sensible code.
\par\sb120
\page
#{\footnote section_10_2}
${\footnote 10.2. Bugs}
+{\footnote browse:00201}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`chapter_10')");
EnableButton("btn_up")}
K{\footnote bugs;
bugtracker;
reporting bugs}
\keepn\f2\b\fs30\sb60\sa60
10.2. Bugs
\par\pard\plain\sb120
We have never yet released a version of NASM with any {\i known} bugs. That 
doesn't usually stop there being plenty we didn't know about, though. Any 
that you find should be reported firstly via the {\f1 bugtracker} at 
{\f1 https://sourceforge.net/projects/nasm/} (click on "Bugs"), or if that 
fails then through one of the contacts in {\uldb section 
1.2}{\v section_1_2}.
\par\sb120
Please read {\uldb section 2.2}{\v section_2_2} first, and don't report the 
bug if it's listed in there as a deliberate feature. (If you think the 
feature is badly thought out, feel free to send us reasons why you think it 
should be changed, but don't just send us mail saying `This is a bug' if 
the documentation says we did it on purpose.) Then read {\uldb section 
10.1}{\v section_10_1}, and don't bother reporting the bug if it's listed 
there.
\par\sb120
If you do report a bug, {\i please} give us all of the following 
information:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
What operating system you're running NASM under. DOS, Linux, NetBSD, Win16, 
Win32, VMS (I'd be impressed), whatever.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If you're running NASM under DOS or Win32, tell us whether you've compiled 
your own executable from the DOS source archive, or whether you were using 
the standard distribution binaries out of the archive. If you were using a 
locally built executable, try to reproduce the problem using one of the 
standard binaries, as this will make it easier for us to reproduce your 
problem prior to fixing it.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Which version of NASM you're using, and exactly how you invoked it. Give us 
the precise command line, and the contents of the {\f1 NASMENV} environment 
variable if any.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Which versions of any supplementary programs you're using, and how you 
invoked them. If the problem only becomes visible at link time, tell us 
what linker you're using, what version of it you've got, and the exact 
linker command line. If the problem involves linking against object files 
generated by a compiler, tell us what compiler, what version, and what 
command line or options you used. (If you're compiling in an IDE, please 
try to reproduce the problem with the command-line version of the 
compiler.)
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If at all possible, send us a NASM source file which exhibits the problem. 
If this causes copyright problems (e.g. you can only reproduce the bug in 
restricted-distribution code) then bear in mind the following two points: 
firstly, we guarantee that any source code sent to us for the purposes of 
debugging NASM will be used {\i only} for the purposes of debugging NASM, 
and that we will delete all our copies of it as soon as we have found and 
fixed the bug or bugs in question; and secondly, we would prefer {\i not} 
to be mailed large chunks of code anyway. The smaller the file, the better. 
A three-line sample file that does nothing useful {\i except} demonstrate 
the problem is much easier to work with than a fully fledged 
ten-thousand-line program. (Of course, some errors {\i do} only crop up in 
large files, so this may not be possible.)
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
A description of what the problem actually {\i is}. `It doesn't work' is 
{\i not} a helpful description! Please describe exactly what is happening 
that shouldn't be, or what isn't happening that should. Examples might be: 
`NASM generates an error message saying Line 3 for an error that's actually 
on Line 5'; `NASM generates an error message that I believe it shouldn't be 
generating at all'; `NASM fails to generate an error message that I believe 
it {\i should} be generating'; `the object file produced from this source 
code crashes my linker'; `the ninth byte of the output file is 66 and I 
think it should be 77 instead'.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If you believe the output file from NASM to be faulty, send it to us. That 
allows us to determine whether our own copy of NASM generates the same 
file, or whether the problem is related to portability issues between our 
development platforms and yours. We can handle binary files mailed to us as 
MIME attachments, uuencoded, and even BinHex. Alternatively, we may be able 
to provide an FTP site you can upload the suspect files to; but mailing 
them is easier for us.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Any other information or data files that might be helpful. If, for example, 
the problem involves NASM failing to generate an object file while TASM can 
generate an equivalent file without trouble, then send us {\i both} object 
files, so we can see what TASM is doing differently from us.
\par\pard\sb120
\page
#{\footnote appendix_a}
${\footnote Appendix A: Ndisasm}
+{\footnote browse:00202}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
K{\footnote ndisasm}
\keepn\f2\b\fs30\sb60\sa60
Appendix A: Ndisasm
\par\pard\plain\sb120
The Netwide Disassembler, NDISASM
\par\sb120
\li360\fi-360
{\uldb Section A.1: Introduction}{\v section_a_1}\par\sb0
{\uldb Section A.2: Getting Started: Installation}{\v section_a_2}\par\sb0
{\uldb Section A.3: Running NDISASM}{\v section_a_3}\par\sb0
{\uldb Section A.4: Bugs and Improvements}{\v section_a_4}\par\sb0
\pard\sb120
\page
#{\footnote section_a_1}
${\footnote A.1. Introduction}
+{\footnote browse:00203}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`appendix_a')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
A.1. Introduction
\par\pard\plain\sb120
The Netwide Disassembler is a small companion program to the Netwide 
Assembler, NASM. It seemed a shame to have an x86 assembler, complete with 
a full instruction table, and not make as much use of it as possible, so 
here's a disassembler which shares the instruction table (and some other 
bits of code) with NASM.
\par\sb120
The Netwide Disassembler does nothing except to produce disassemblies of 
{\i binary} source files. NDISASM does not have any understanding of object 
file formats, like {\f1 objdump}, and it will not understand 
{\f1 DOS\'A0.EXE} files like {\f1 debug} will. It just disassembles.
\par\sb120
\page
#{\footnote section_a_2}
${\footnote A.2. Getting Started: Installation}
+{\footnote browse:00204}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`appendix_a')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
A.2. Getting Started: Installation
\par\pard\plain\sb120
See {\uldb section 1.3}{\v section_1_3} for installation instructions. 
NDISASM, like NASM, has a {\f1 man\'A0page} which you may want to put 
somewhere useful, if you are on a Unix system.
\par\sb120
\page
#{\footnote section_a_3}
${\footnote A.3. Running NDISASM}
+{\footnote browse:00205}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`appendix_a')");
EnableButton("btn_up")}
K{\footnote \'ADb;
\'ADh;
\'ADr;
\'ADu option}
\keepn\f2\b\fs30\sb60\sa60
A.3. Running NDISASM
\par\pard\plain\sb120
To disassemble a file, you will typically use a command of the form
\par\sb120
\keep\f1\sb120
       ndisasm [-b16 | -b32] filename\par\sb0
\pard\f0\sb120
NDISASM can disassemble 16-bit code or 32-bit code equally easily, provided 
of course that you remember to specify which it is to work with. If no 
{\f1 \'ADb} switch is present, NDISASM works in 16-bit mode by default. The 
{\f1 \'ADu} switch (for USE32) also invokes 32-bit mode.
\par\sb120
Two more command line options are {\f1 \'ADr} which reports the version 
number of NDISASM you are running, and {\f1 \'ADh} which gives a short 
summary of command line options.
\par\sb120
\li360\fi-360
{\uldb Section A.3.1: COM Files: Specifying an Origin}{\v section_a_3_1}\par\sb0
{\uldb Section A.3.2: Code Following Data: Synchronisation}{\v section_a_3_2}\par\sb0
{\uldb Section A.3.3: Mixed Code and Data: Automatic (Intelligent) Synchronisation }{\v section_a_3_3}\par\sb0
{\uldb Section A.3.4: Other Options}{\v section_a_3_4}\par\sb0
\pard\sb120
\page
#{\footnote section_a_3_1}
${\footnote A.3.1. COM Files: Specifying an Origin}
+{\footnote browse:00206}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_a_3')");
EnableButton("btn_up")}
K{\footnote \'ADo option}
\keepn\f2\b\fs30\sb60\sa60
A.3.1. COM Files: Specifying an Origin
\par\pard\plain\sb120
To disassemble a {\f1 DOS\'A0.COM} file correctly, a disassembler must 
assume that the first instruction in the file is loaded at address 
{\f1 0x100}, rather than at zero. NDISASM, which assumes by default that 
any file you give it is loaded at zero, will therefore need to be informed 
of this.
\par\sb120
The {\f1 \'ADo} option allows you to declare a different origin for the 
file you are disassembling. Its argument may be expressed in any of the 
NASM numeric formats: decimal by default, if it begins with `{\f1 $}' or 
`{\f1 0x}' or ends in `{\f1 H}' it's {\f1 hex}, if it ends in `{\f1 Q}' 
it's {\f1 octal}, and if it ends in `{\f1 B}' it's {\f1 binary}.
\par\sb120
Hence, to disassemble a {\f1 .COM} file:
\par\sb120
\keep\f1\sb120
       ndisasm -o100h filename.com\par\sb0
\pard\f0\sb120
will do the trick.
\par\sb120
\page
#{\footnote section_a_3_2}
${\footnote A.3.2. Code Following Data: Synchronisation}
+{\footnote browse:00207}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_a_3')");
EnableButton("btn_up")}
K{\footnote \'ADs option;
synchronisation}
\keepn\f2\b\fs30\sb60\sa60
A.3.2. Code Following Data: Synchronisation
\par\pard\plain\sb120
Suppose you are disassembling a file which contains some data which isn't 
machine code, and {\i then} contains some machine code. NDISASM will 
faithfully plough through the data section, producing machine instructions 
wherever it can (although most of them will look bizarre, and some may have 
unusual prefixes, e.g. `{\f1 FS\'A0OR\'A0AX,0x240A}'), and generating `DB' 
instructions ever so often if it's totally stumped. Then it will reach the 
code section.
\par\sb120
Supposing NDISASM has just finished generating a strange machine 
instruction from part of the data section, and its file position is now one 
byte {\i before} the beginning of the code section. It's entirely possible 
that another spurious instruction will get generated, starting with the 
final byte of the data section, and then the correct first instruction in 
the code section will not be seen because the starting point skipped over 
it. This isn't really ideal.
\par\sb120
To avoid this, you can specify a `{\f1 synchronisation}' point, or indeed 
as many synchronisation points as you like (although NDISASM can only 
handle 8192 sync points internally). The definition of a sync point is 
this: NDISASM guarantees to hit sync points exactly during disassembly. If 
it is thinking about generating an instruction which would cause it to jump 
over a sync point, it will discard that instruction and output a `{\f1 db}' 
instead. So it {\i will} start disassembly exactly from the sync point, and 
so you {\i will} see all the instructions in your code section.
\par\sb120
Sync points are specified using the {\f1 \'ADs} option: they are measured 
in terms of the program origin, not the file position. So if you want to 
synchronise after 32 bytes of a {\f1 .COM} file, you would have to do
\par\sb120
\keep\f1\sb120
       ndisasm -o100h -s120h file.com\par\sb0
\pard\f0\sb120
rather than
\par\sb120
\keep\f1\sb120
       ndisasm -o100h -s20h file.com\par\sb0
\pard\f0\sb120
As stated above, you can specify multiple sync markers if you need to, just 
by repeating the {\f1 \'ADs} option.
\par\sb120
\page
#{\footnote section_a_3_3}
${\footnote A.3.3. Mixed Code and Data: Automatic (Intelligent) Synchronisation }
+{\footnote browse:00208}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_a_3')");
EnableButton("btn_up")}
K{\footnote \'ADa option;
auto\'ADsync;
\'ADi option}
\keepn\f2\b\fs30\sb60\sa60
A.3.3. Mixed Code and Data: Automatic (Intelligent) Synchronisation 
\par\pard\plain\sb120
Suppose you are disassembling the boot sector of a {\f1 DOS} floppy (maybe 
it has a virus, and you need to understand the virus so that you know what 
kinds of damage it might have done you). Typically, this will contain a 
{\f1 JMP} instruction, then some data, then the rest of the code. So there 
is a very good chance of NDISASM being {\i misaligned} when the data ends 
and the code begins. Hence a sync point is needed.
\par\sb120
On the other hand, why should you have to specify the sync point manually? 
What you'd do in order to find where the sync point would be, surely, would 
be to read the {\f1 JMP} instruction, and then to use its target address as 
a sync point. So can NDISASM do that for you?
\par\sb120
The answer, of course, is yes: using either of the synonymous switches 
{\f1 \'ADa} (for automatic sync) or {\f1 \'ADi} (for intelligent sync) will 
enable {\f1 auto\'ADsync} mode. Auto-sync mode automatically generates a 
sync point for any forward-referring PC-relative jump or call instruction 
that NDISASM encounters. (Since NDISASM is one-pass, if it encounters a 
PC-relative jump whose target has already been processed, there isn't much 
it can do about it...)
\par\sb120
Only PC-relative jumps are processed, since an absolute jump is either 
through a register (in which case NDISASM doesn't know what the register 
contains) or involves a segment address (in which case the target code 
isn't in the same segment that NDISASM is working in, and so the sync point 
can't be placed anywhere useful).
\par\sb120
For some kinds of file, this mechanism will automatically put sync points 
in all the right places, and save you from having to place any sync points 
manually. However, it should be stressed that auto-sync mode is {\i not} 
guaranteed to catch all the sync points, and you may still have to place 
some manually.
\par\sb120
Auto-sync mode doesn't prevent you from declaring manual sync points: it 
just adds automatically generated ones to the ones you provide. It's 
perfectly feasible to specify {\f1 \'ADi} {\i and} some {\f1 \'ADs} 
options.
\par\sb120
Another caveat with auto-sync mode is that if, by some unpleasant fluke, 
something in your data section should disassemble to a PC-relative call or 
jump instruction, NDISASM may obediently place a sync point in a totally 
random place, for example in the middle of one of the instructions in your 
code section. So you may end up with a wrong disassembly even if you use 
auto-sync. Again, there isn't much I can do about this. If you have 
problems, you'll have to use manual sync points, or use the {\f1 \'ADk} 
option (documented below) to suppress disassembly of the data area.
\par\sb120
\page
#{\footnote section_a_3_4}
${\footnote A.3.4. Other Options}
+{\footnote browse:00209}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_a_3')");
EnableButton("btn_up")}
K{\footnote \'ADe option;
\'ADk}
\keepn\f2\b\fs30\sb60\sa60
A.3.4. Other Options
\par\pard\plain\sb120
The {\f1 \'ADe} option skips a header on the file, by ignoring the first N 
bytes. This means that the header is {\i not} counted towards the 
disassembly offset: if you give {\f1 \'ADe10\'A0\'ADo10}, disassembly will 
start at byte 10 in the file, and this will be given offset 10, not 20.
\par\sb120
The {\f1 \'ADk} option is provided with two comma-separated numeric 
arguments, the first of which is an assembly offset and the second is a 
number of bytes to skip. This {\i will} count the skipped bytes towards the 
assembly offset: its use is to suppress disassembly of a data section which 
wouldn't contain anything you wanted to see anyway.
\par\sb120
\page
#{\footnote section_a_4}
${\footnote A.4. Bugs and Improvements}
+{\footnote browse:00210}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`appendix_a')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
A.4. Bugs and Improvements
\par\pard\plain\sb120
There are no known bugs. However, any you find, with patches if possible, 
should be sent to {\f1 jules@dsf.org.uk} or {\f1 anakin@pobox.com}, or to 
the developer's site at {\f1 https://sourceforge.net/projects/nasm/} and 
we'll try to fix them. Feel free to send contributions and new features as 
well.
\par\sb120
Future plans include awareness of which processors certain instructions 
will run on, and marking of instructions that are too advanced for some 
processor (or are {\f1 FPU} instructions, or are undocumented opcodes, or 
are privileged protected-mode instructions, or whatever).
\par\sb120
That's All Folks!
\par\sb120
I hope NDISASM is of some use to somebody. Including me. :-)
\par\sb120
I don't recommend taking NDISASM apart to see how an efficient disassembler 
works, because as far as I know, it isn't an efficient one anyway. You have 
been warned.
\par\sb120
\page
#{\footnote appendix_b}
${\footnote Appendix B: x86 Instruction Reference}
+{\footnote browse:00211}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`top')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
Appendix B: x86 Instruction Reference
\par\pard\plain\sb120
This appendix provides a complete list of the machine instructions which 
NASM will assemble, and a short description of the function of each one.
\par\sb120
It is not intended to be exhaustive documentation on the fine details of 
the instructions' function, such as which exceptions they can trigger: for 
such documentation, you should go to Intel's Web site, 
{\f1 http://developer.intel.com/design/Pentium4/manuals/}.
\par\sb120
Instead, this appendix is intended primarily to provide documentation on 
the way the instructions may be used within NASM. For example, looking up 
{\f1 LOOP} will tell you that NASM allows {\f1 CX} or {\f1 ECX} to be 
specified as an optional second argument to the {\f1 LOOP} instruction, to 
enforce which of the two possible counter registers should be used if the 
default is not the one desired.
\par\sb120
The instructions are not quite listed in alphabetical order, since groups 
of instructions with similar functions are lumped together in the same 
entry. Most of them don't move very far from their alphabetic position 
because of this.
\par\sb120
\li360\fi-360
{\uldb Section B.1: Key to Operand Specifications}{\v section_b_1}\par\sb0
{\uldb Section B.2: Key to Opcode Descriptions}{\v section_b_2}\par\sb0
{\uldb Section B.3: Key to Instruction Flags}{\v section_b_3}\par\sb0
{\uldb Section B.4: x86 Instruction Set}{\v section_b_4}\par\sb0
\pard\sb120
\page
#{\footnote section_b_1}
${\footnote B.1. Key to Operand Specifications}
+{\footnote browse:00212}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`appendix_b')");
EnableButton("btn_up")}
K{\footnote general purpose register;
immediate operand;
memory references;
restricted memory references}
\keepn\f2\b\fs30\sb60\sa60
B.1. Key to Operand Specifications
\par\pard\plain\sb120
The instruction descriptions in this appendix specify their operands using 
the following notation:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Registers: {\f1 reg8} denotes an 8-bit general purpose register, 
{\f1 reg16} denotes a 16-bit general purpose register, and {\f1 reg32} a 
32-bit one. {\f1 fpureg} denotes one of the eight FPU stack registers, 
{\f1 mmxreg} denotes one of the eight 64-bit MMX registers, and 
{\f1 segreg} denotes a segment register. In addition, some registers (such 
as {\f1 AL}, {\f1 DX} or {\f1 ECX}) may be specified explicitly.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Immediate operands: {\f1 imm} denotes a generic immediate operand. 
{\f1 imm8}, {\f1 imm16} and {\f1 imm32} are used when the operand is 
intended to be a specific size. For some of these instructions, NASM needs 
an explicit specifier: for example, {\f1 ADD\'A0ESP,16} could be 
interpreted as either {\f1 ADD\'A0r/m32,imm32} or {\f1 ADD\'A0r/m32,imm8}. 
NASM chooses the former by default, and so you must specify 
{\f1 ADD\'A0ESP,BYTE\'A016} for the latter.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Memory references: {\f1 mem} denotes a generic memory reference; 
{\f1 mem8}, {\f1 mem16}, {\f1 mem32}, {\f1 mem64} and {\f1 mem80} are used 
when the operand needs to be a specific size. Again, a specifier is needed 
in some cases: {\f1 DEC\'A0[address]} is ambiguous and will be rejected by 
NASM. You must specify {\f1 DEC\'A0BYTE\'A0[address]}, 
{\f1 DEC\'A0WORD\'A0[address]} or {\f1 DEC\'A0DWORD\'A0[address]} instead.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Restricted memory references: one form of the {\f1 MOV} instruction allows 
a memory address to be specified {\i without} allowing the normal range of 
register combinations and effective address processing. This is denoted by 
{\f1 memoffs8}, {\f1 memoffs16} and {\f1 memoffs32}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Register or memory choices: many instructions can accept either a register 
{\i or} a memory reference as an operand. {\f1 r/m8} is a shorthand for 
{\f1 reg8/mem8}; similarly {\f1 r/m16} and {\f1 r/m32}. {\f1 r/m64} is 
MMX-related, and is a shorthand for {\f1 mmxreg/mem64}.
\par\pard\sb120
\page
#{\footnote section_b_2}
${\footnote B.2. Key to Opcode Descriptions}
+{\footnote browse:00213}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`appendix_b')");
EnableButton("btn_up")}
K{\footnote ModR/M byte;
SIB byte}
\keepn\f2\b\fs30\sb60\sa60
B.2. Key to Opcode Descriptions
\par\pard\plain\sb120
This appendix also provides the opcodes which NASM will generate for each 
form of each instruction. The opcodes are listed in the following way:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
A hex number, such as {\f1 3F}, indicates a fixed byte containing that 
number.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
A hex number followed by {\f1 +r}, such as {\f1 C8+r}, indicates that one 
of the operands to the instruction is a register, and the `register value' 
of that register should be added to the hex number to produce the generated 
byte. For example, EDX has register value 2, so the code {\f1 C8+r}, when 
the register operand is EDX, generates the hex byte {\f1 CA}. Register 
values for specific registers are given in {\uldb section 
B.2.1}{\v section_b_2_1}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
A hex number followed by {\f1 +cc}, such as {\f1 40+cc}, indicates that the 
instruction name has a condition code suffix, and the numeric 
representation of the condition code should be added to the hex number to 
produce the generated byte. For example, the code {\f1 40+cc}, when the 
instruction contains the {\f1 NE} condition, generates the hex byte 
{\f1 45}. Condition codes and their numeric representations are given in 
{\uldb section B.2.2}{\v section_b_2_2}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
A slash followed by a digit, such as {\f1 /2}, indicates that one of the 
operands to the instruction is a memory address or register (denoted 
{\f1 mem} or {\f1 r/m}, with an optional size). This is to be encoded as an 
effective address, with a ModR/M byte, an optional SIB byte, and an 
optional displacement, and the spare (register) field of the ModR/M byte 
should be the digit given (which will be from 0 to 7, so it fits in three 
bits). The encoding of effective addresses is given in {\uldb section 
B.2.5}{\v section_b_2_5}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The code {\f1 /r} combines the above two: it indicates that one of the 
operands is a memory address or {\f1 r/m}, and another is a register, and 
that an effective address should be generated with the spare (register) 
field in the ModR/M byte being equal to the `register value' of the 
register operand. The encoding of effective addresses is given in 
{\uldb section B.2.5}{\v section_b_2_5}; register values are given in 
{\uldb section B.2.1}{\v section_b_2_1}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The codes {\f1 ib}, {\f1 iw} and {\f1 id} indicate that one of the operands 
to the instruction is an immediate value, and that this is to be encoded as 
a byte, little-endian word or little-endian doubleword respectively.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The codes {\f1 rb}, {\f1 rw} and {\f1 rd} indicate that one of the operands 
to the instruction is an immediate value, and that the {\i difference} 
between this value and the address of the end of the instruction is to be 
encoded as a byte, word or doubleword respectively. Where the form 
{\f1 rw/rd} appears, it indicates that either {\f1 rw} or {\f1 rd} should 
be used according to whether assembly is being performed in 
{\f1 BITS\'A016} or {\f1 BITS\'A032} state respectively.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The codes {\f1 ow} and {\f1 od} indicate that one of the operands to the 
instruction is a reference to the contents of a memory address specified as 
an immediate value: this encoding is used in some forms of the {\f1 MOV} 
instruction in place of the standard effective-address mechanism. The 
displacement is encoded as a word or doubleword. Again, {\f1 ow/od} denotes 
that {\f1 ow} or {\f1 od} should be chosen according to the {\f1 BITS} 
setting.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The codes {\f1 o16} and {\f1 o32} indicate that the given form of the 
instruction should be assembled with operand size 16 or 32 bits. In other 
words, {\f1 o16} indicates a {\f1 66} prefix in {\f1 BITS\'A032} state, but 
generates no code in {\f1 BITS\'A016} state; and {\f1 o32} indicates a 
{\f1 66} prefix in {\f1 BITS\'A016} state but generates nothing in 
{\f1 BITS\'A032}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The codes {\f1 a16} and {\f1 a32}, similarly to {\f1 o16} and {\f1 o32}, 
indicate the address size of the given form of the instruction. Where this 
does not match the {\f1 BITS} setting, a {\f1 67} prefix is required.
\par\pard\sb120
\li360\fi-360
{\uldb Section B.2.1: Register Values}{\v section_b_2_1}\par\sb0
{\uldb Section B.2.2: Condition Codes}{\v section_b_2_2}\par\sb0
{\uldb Section B.2.3: SSE Condition Predicates}{\v section_b_2_3}\par\sb0
{\uldb Section B.2.4: Status Flags}{\v section_b_2_4}\par\sb0
{\uldb Section B.2.5: Effective Address Encoding: ModR/M and SIB}{\v section_b_2_5}\par\sb0
\pard\sb120
\page
#{\footnote section_b_2_1}
${\footnote B.2.1. Register Values}
+{\footnote browse:00214}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_2')");
EnableButton("btn_up")}
K{\footnote control registers;
debug registers;
floating\'ADpoint, registers;
MMX registers;
segment registers;
test registers}
\keepn\f2\b\fs30\sb60\sa60
B.2.1. Register Values
\par\pard\plain\sb120
Where an instruction requires a register value, it is already implicit in 
the encoding of the rest of the instruction what type of register is 
intended: an 8-bit general-purpose register, a segment register, a debug 
register, an MMX register, or whatever. Therefore there is no problem with 
registers of different types sharing an encoding value.
\par\sb120
The encodings for the various classes of register are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
8-bit general registers: {\f1 AL} is 0, {\f1 CL} is 1, {\f1 DL} is 2, 
{\f1 BL} is 3, {\f1 AH} is 4, {\f1 CH} is 5, {\f1 DH} is 6, and {\f1 BH} is 
7.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
16-bit general registers: {\f1 AX} is 0, {\f1 CX} is 1, {\f1 DX} is 2, 
{\f1 BX} is 3, {\f1 SP} is 4, {\f1 BP} is 5, {\f1 SI} is 6, and {\f1 DI} is 
7.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
32-bit general registers: {\f1 EAX} is 0, {\f1 ECX} is 1, {\f1 EDX} is 2, 
{\f1 EBX} is 3, {\f1 ESP} is 4, {\f1 EBP} is 5, {\f1 ESI} is 6, and 
{\f1 EDI} is 7.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Segment registers: {\f1 ES} is 0, {\f1 CS} is 1, {\f1 SS} is 2, {\f1 DS} is 
3, {\f1 FS} is 4, and {\f1 GS} is 5.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Floating-point registers: {\f1 ST0} is 0, {\f1 ST1} is 1, {\f1 ST2} is 2, 
{\f1 ST3} is 3, {\f1 ST4} is 4, {\f1 ST5} is 5, {\f1 ST6} is 6, and 
{\f1 ST7} is 7.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
64-bit MMX registers: {\f1 MM0} is 0, {\f1 MM1} is 1, {\f1 MM2} is 2, 
{\f1 MM3} is 3, {\f1 MM4} is 4, {\f1 MM5} is 5, {\f1 MM6} is 6, and 
{\f1 MM7} is 7.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Control registers: {\f1 CR0} is 0, {\f1 CR2} is 2, {\f1 CR3} is 3, and 
{\f1 CR4} is 4.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Debug registers: {\f1 DR0} is 0, {\f1 DR1} is 1, {\f1 DR2} is 2, {\f1 DR3} 
is 3, {\f1 DR6} is 6, and {\f1 DR7} is 7.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Test registers: {\f1 TR3} is 3, {\f1 TR4} is 4, {\f1 TR5} is 5, {\f1 TR6} 
is 6, and {\f1 TR7} is 7.
\par\pard\sb120
(Note that wherever a register name contains a number, that number is also 
the register value for that register.)
\par\sb120
\page
#{\footnote section_b_2_2}
${\footnote B.2.2. Condition Codes}
+{\footnote browse:00215}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_2')");
EnableButton("btn_up")}
K{\footnote condition codes}
\keepn\f2\b\fs30\sb60\sa60
B.2.2. Condition Codes
\par\pard\plain\sb120
The available condition codes are given here, along with their numeric 
representations as part of opcodes. Many of these condition codes have 
synonyms, so several will be listed at a time.
\par\sb120
In the following descriptions, the word `either', when applied to two 
possible trigger conditions, is used to mean `either or both'. If `either 
but not both' is meant, the phrase `exactly one of' is used.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 O} is 0 (trigger if the overflow flag is set); {\f1 NO} is 1.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 B}, {\f1 C} and {\f1 NAE} are 2 (trigger if the carry flag is set); 
{\f1 AE}, {\f1 NB} and {\f1 NC} are 3.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 E} and {\f1 Z} are 4 (trigger if the zero flag is set); {\f1 NE} and 
{\f1 NZ} are 5.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 BE} and {\f1 NA} are 6 (trigger if either of the carry or zero flags 
is set); {\f1 A} and {\f1 NBE} are 7.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 S} is 8 (trigger if the sign flag is set); {\f1 NS} is 9.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 P} and {\f1 PE} are 10 (trigger if the parity flag is set); {\f1 NP} 
and {\f1 PO} are 11.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 L} and {\f1 NGE} are 12 (trigger if exactly one of the sign and 
overflow flags is set); {\f1 GE} and {\f1 NL} are 13.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 LE} and {\f1 NG} are 14 (trigger if either the zero flag is set, or 
exactly one of the sign and overflow flags is set); {\f1 G} and {\f1 NLE} 
are 15.
\par\pard\sb120
Note that in all cases, the sense of a condition code may be reversed by 
changing the low bit of the numeric representation.
\par\sb120
For details of when an instruction sets each of the status flags, see the 
individual instruction, plus the Status Flags reference in {\uldb section 
B.2.4}{\v section_b_2_4}
\par\sb120
\page
#{\footnote section_b_2_3}
${\footnote B.2.3. SSE Condition Predicates}
+{\footnote browse:00216}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_2')");
EnableButton("btn_up")}
K{\footnote sse condition predicates}
\keepn\f2\b\fs30\sb60\sa60
B.2.3. SSE Condition Predicates
\par\pard\plain\sb120
The condition predicates for SSE comparison instructions are the codes used 
as part of the opcode, to determine what form of comparison is being 
carried out. In each case, the imm8 value is the final byte of the opcode 
encoding, and the predicate is the code used as part of the mnemonic for 
the instruction (equivalent to the "cc" in an integer instruction that used 
a condition code). The instructions that use this will give details of what 
the various mnemonics are, this table is used to help you work out details 
of what is happening.
\par\sb120
\keep\f1\sb120
Predi-  imm8  Description Relation where:   Emula- Result   QNaN \par\sb0
 cate  Encod-             A Is 1st Operand  tion   if NaN   Signal \par\sb0
        ing               B Is 2nd Operand         Operand  Invalid \par\sb0
\par\sb0
EQ     000B   equal       A = B                    False     No \par\sb0
\par\sb0
LT     001B   less-than   A < B                    False     Yes \par\sb0
\par\sb0
LE     010B   less-than-  A <= B                   False     Yes \par\sb0
               or-equal \par\sb0
\par\sb0
---    ----   greater     A > B             Swap   False     Yes \par\sb0
              than                          Operands, \par\sb0
                                            Use LT \par\sb0
\par\sb0
---    ----   greater-    A >= B            Swap   False     Yes \par\sb0
              than-or-equal                 Operands, \par\sb0
                                            Use LE \par\sb0
\par\sb0
UNORD  011B   unordered   A, B = Unordered         True      No \par\sb0
\par\sb0
NEQ    100B   not-equal   A != B                   True      No \par\sb0
\par\sb0
NLT    101B   not-less-   NOT(A < B)               True      Yes \par\sb0
              than \par\sb0
\par\sb0
NLE    110B   not-less-   NOT(A <= B)              True      Yes \par\sb0
              than-or- \par\sb0
              equal \par\sb0
\par\sb0
---    ----   not-greater NOT(A > B)        Swap   True      Yes \par\sb0
              than                          Operands, \par\sb0
                                            Use NLT \par\sb0
\par\sb0
---    ----   not-greater NOT(A >= B)       Swap   True      Yes \par\sb0
              than-                         Operands, \par\sb0
              or-equal                      Use NLE \par\sb0
\par\sb0
ORD    111B   ordered      A , B = Ordered         False     No\par\sb0
\pard\f0\sb120
The unordered relationship is true when at least one of the two values 
being compared is a NaN or in an unsupported format.
\par\sb120
Note that the comparisons which are listed as not having a predicate or 
encoding can only be achieved through software emulation, as described in 
the "emulation" column. Note in particular that an instruction such as 
{\f1 greater\'ADthan} is not the same as {\f1 NLE}, as, unlike with the 
{\f1 CMP} instruction, it has to take into account the possibility of one 
operand containing a NaN or an unsupported numeric format.
\par\sb120
\page
#{\footnote section_b_2_4}
${\footnote B.2.4. Status Flags}
+{\footnote browse:00217}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_2')");
EnableButton("btn_up")}
K{\footnote status flags}
\keepn\f2\b\fs30\sb60\sa60
B.2.4. Status Flags
\par\pard\plain\sb120
The status flags provide some information about the result of the 
arithmetic instructions. This information can be used by conditional 
instructions (such a {\f1 Jcc} and {\f1 CMOVcc}) as well as by some of the 
other instructions (such as {\f1 ADC} and {\f1 INTO}).
\par\sb120
There are 6 status flags:
\par\sb120
\keep\f1\sb120
CF - Carry flag.\par\sb0
\pard\f0\sb120
Set if an arithmetic operation generates a carry or a borrow out of the 
most-significant bit of the result; cleared otherwise. This flag indicates 
an overflow condition for unsigned-integer arithmetic. It is also used in 
multiple-precision arithmetic.
\par\sb120
\keep\f1\sb120
PF - Parity flag.\par\sb0
\pard\f0\sb120
Set if the least-significant byte of the result contains an even number of 
1 bits; cleared otherwise.
\par\sb120
\keep\f1\sb120
AF - Adjust flag.\par\sb0
\pard\f0\sb120
Set if an arithmetic operation generates a carry or a borrow out of bit 3 
of the result; cleared otherwise. This flag is used in binary-coded decimal 
(BCD) arithmetic.
\par\sb120
\keep\f1\sb120
ZF - Zero flag.\par\sb0
\pard\f0\sb120
Set if the result is zero; cleared otherwise.
\par\sb120
\keep\f1\sb120
SF - Sign flag.\par\sb0
\pard\f0\sb120
Set equal to the most-significant bit of the result, which is the sign bit 
of a signed integer. (0 indicates a positive value and 1 indicates a 
negative value.)
\par\sb120
\keep\f1\sb120
OF - Overflow flag.\par\sb0
\pard\f0\sb120
Set if the integer result is too large a positive number or too small a 
negative number (excluding the sign-bit) to fit in the destination operand; 
cleared otherwise. This flag indicates an overflow condition for 
signed-integer (two's complement) arithmetic.
\par\sb120
\page
#{\footnote section_b_2_5}
${\footnote B.2.5. Effective Address Encoding: ModR/M and SIB}
+{\footnote browse:00218}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_2')");
EnableButton("btn_up")}
K{\footnote effective addresses;
ModR/M byte;
SIB byte}
\keepn\f2\b\fs30\sb60\sa60
B.2.5. Effective Address Encoding: ModR/M and SIB
\par\pard\plain\sb120
An effective address is encoded in up to three parts: a ModR/M byte, an 
optional SIB byte, and an optional byte, word or doubleword displacement 
field.
\par\sb120
The ModR/M byte consists of three fields: the {\f1 mod} field, ranging from 
0 to 3, in the upper two bits of the byte, the {\f1 r/m} field, ranging 
from 0 to 7, in the lower three bits, and the spare (register) field in the 
middle (bit 3 to bit 5). The spare field is not relevant to the effective 
address being encoded, and either contains an extension to the instruction 
opcode or the register value of another operand.
\par\sb120
The ModR/M system can be used to encode a direct register reference rather 
than a memory access. This is always done by setting the {\f1 mod} field to 
3 and the {\f1 r/m} field to the register value of the register in question 
(it must be a general-purpose register, and the size of the register must 
already be implicit in the encoding of the rest of the instruction). In 
this case, the SIB byte and displacement field are both absent.
\par\sb120
In 16-bit addressing mode (either {\f1 BITS\'A016} with no {\f1 67} prefix, 
or {\f1 BITS\'A032} with a {\f1 67} prefix), the SIB byte is never used. 
The general rules for {\f1 mod} and {\f1 r/m} (there is an exception, given 
below) are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 mod} field gives the length of the displacement field: 0 means no 
displacement, 1 means one byte, and 2 means two bytes.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 r/m} field encodes the combination of registers to be added to the 
displacement to give the accessed address: 0 means {\f1 BX+SI}, 1 means 
{\f1 BX+DI}, 2 means {\f1 BP+SI}, 3 means {\f1 BP+DI}, 4 means {\f1 SI} 
only, 5 means {\f1 DI} only, 6 means {\f1 BP} only, and 7 means {\f1 BX} 
only.
\par\pard\sb120
However, there is a special case:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If {\f1 mod} is 0 and {\f1 r/m} is 6, the effective address encoded is not 
{\f1 [BP]} as the above rules would suggest, but instead {\f1 [disp16]}: 
the displacement field is present and is two bytes long, and no registers 
are added to the displacement.
\par\pard\sb120
Therefore the effective address {\f1 [BP]} cannot be encoded as efficiently 
as {\f1 [BX]}; so if you code {\f1 [BP]} in a program, NASM adds a notional 
8-bit zero displacement, and sets {\f1 mod} to 1, {\f1 r/m} to 6, and the 
one-byte displacement field to 0.
\par\sb120
In 32-bit addressing mode (either {\f1 BITS\'A016} with a {\f1 67} prefix, 
or {\f1 BITS\'A032} with no {\f1 67} prefix) the general rules (again, 
there are exceptions) for {\f1 mod} and {\f1 r/m} are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 mod} field gives the length of the displacement field: 0 means no 
displacement, 1 means one byte, and 2 means four bytes.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If only one register is to be added to the displacement, and it is not 
{\f1 ESP}, the {\f1 r/m} field gives its register value, and the SIB byte 
is absent. If the {\f1 r/m} field is 4 (which would encode {\f1 ESP}), the 
SIB byte is present and gives the combination and scaling of registers to 
be added to the displacement.
\par\pard\sb120
If the SIB byte is present, it describes the combination of registers (an 
optional base register, and an optional index register scaled by 
multiplication by 1, 2, 4 or 8) to be added to the displacement. The SIB 
byte is divided into the {\f1 scale} field, in the top two bits, the 
{\f1 index} field in the next three, and the {\f1 base} field in the bottom 
three. The general rules are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 base} field encodes the register value of the base register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 index} field encodes the register value of the index register, 
unless it is 4, in which case no index register is used (so {\f1 ESP} 
cannot be used as an index register).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 scale} field encodes the multiplier by which the index register is 
scaled before adding it to the base and displacement: 0 encodes a 
multiplier of 1, 1 encodes 2, 2 encodes 4 and 3 encodes 8.
\par\pard\sb120
The exceptions to the 32-bit encoding rules are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If {\f1 mod} is 0 and {\f1 r/m} is 5, the effective address encoded is not 
{\f1 [EBP]} as the above rules would suggest, but instead {\f1 [disp32]}: 
the displacement field is present and is four bytes long, and no registers 
are added to the displacement.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If {\f1 mod} is 0, {\f1 r/m} is 4 (meaning the SIB byte is present) and 
{\f1 base} is 4, the effective address encoded is not {\f1 [EBP+index]} as 
the above rules would suggest, but instead {\f1 [disp32+index]}: the 
displacement field is present and is four bytes long, and there is no base 
register (but the index register is still processed in the normal way).
\par\pard\sb120
\page
#{\footnote section_b_3}
${\footnote B.3. Key to Instruction Flags}
+{\footnote browse:00219}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`appendix_b')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
B.3. Key to Instruction Flags
\par\pard\plain\sb120
Given along with each instruction in this appendix is a set of flags, 
denoting the type of the instruction. The types are as follows:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 8086}, {\f1 186}, {\f1 286}, {\f1 386}, {\f1 486}, {\f1 PENT} and 
{\f1 P6} denote the lowest processor type that supports the instruction. 
Most instructions run on all processors above the given type; those that do 
not are documented. The Pentium II contains no additional instructions 
beyond the P6 (Pentium Pro); from the point of view of its instruction set, 
it can be thought of as a P6 with MMX capability.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 3DNOW} indicates that the instruction is a 3DNow! one, and will run on 
the AMD K6-2 and later processors. ATHLON extensions to the 3DNow! 
instruction set are documented as such.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 CYRIX} indicates that the instruction is specific to Cyrix processors, 
for example the extra MMX instructions in the Cyrix extended MMX 
instruction set.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FPU} indicates that the instruction is a floating-point one, and will 
only run on machines with a coprocessor (automatically including 486DX, 
Pentium and above).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 KATMAI} indicates that the instruction was introduced as part of the 
Katmai New Instruction set. These instructions are available on the Pentium 
III and later processors. Those which are not specifically SSE instructions 
are also available on the AMD Athlon.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 MMX} indicates that the instruction is an MMX one, and will run on 
MMX-capable Pentium processors and the Pentium II.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PRIV} indicates that the instruction is a protected-mode management 
instruction. Many of these may only be used in protected mode, or only at 
privilege level zero.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 SSE} and {\f1 SSE2} indicate that the instruction is a Streaming SIMD 
Extension instruction. These instructions operate on multiple values in a 
single operation. SSE was introduced with the Pentium III and SSE2 was 
introduced with the Pentium 4.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 UNDOC} indicates that the instruction is an undocumented one, and not 
part of the official Intel Architecture; it may or may not be supported on 
any given machine.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 WILLAMETTE} indicates that the instruction was introduced as part of 
the new instruction set in the Pentium 4 and Intel Xeon processors. These 
instructions are also known as SSE2 instructions.
\par\pard\sb120
\page
#{\footnote section_b_4}
${\footnote B.4. x86 Instruction Set}
+{\footnote browse:00220}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`appendix_b')");
EnableButton("btn_up")}
\keepn\f2\b\fs30\sb60\sa60
B.4. x86 Instruction Set
\par\pard\plain\sb120
\li360\fi-360
{\uldb Section B.4.1: AAA, AAS, AAM, AAD: ASCII Adjustments}{\v section_b_4_1}\par\sb0
{\uldb Section B.4.2: ADC: Add with Carry}{\v section_b_4_2}\par\sb0
{\uldb Section B.4.3: ADD: Add Integers}{\v section_b_4_3}\par\sb0
{\uldb Section B.4.4: ADDPD: ADD Packed Double-Precision FP Values}{\v section_b_4_4}\par\sb0
{\uldb Section B.4.5: ADDPS: ADD Packed Single-Precision FP Values}{\v section_b_4_5}\par\sb0
{\uldb Section B.4.6: ADDSD: ADD Scalar Double-Precision FP Values}{\v section_b_4_6}\par\sb0
{\uldb Section B.4.7: ADDSS: ADD Scalar Single-Precision FP Values}{\v section_b_4_7}\par\sb0
{\uldb Section B.4.8: AND: Bitwise AND}{\v section_b_4_8}\par\sb0
{\uldb Section B.4.9: ANDNPD: Bitwise Logical AND NOT of Packed Double-Precision FP Values}{\v section_b_4_9}\par\sb0
{\uldb Section B.4.10: ANDNPS: Bitwise Logical AND NOT of Packed Single-Precision FP Values}{\v section_b_4_10}\par\sb0
{\uldb Section B.4.11: ANDPD: Bitwise Logical AND For Single FP}{\v section_b_4_11}\par\sb0
{\uldb Section B.4.12: ANDPS: Bitwise Logical AND For Single FP}{\v section_b_4_12}\par\sb0
{\uldb Section B.4.13: ARPL: Adjust RPL Field of Selector}{\v section_b_4_13}\par\sb0
{\uldb Section B.4.14: BOUND: Check Array Index against Bounds}{\v section_b_4_14}\par\sb0
{\uldb Section B.4.15: BSF, BSR: Bit Scan}{\v section_b_4_15}\par\sb0
{\uldb Section B.4.16: BSWAP: Byte Swap}{\v section_b_4_16}\par\sb0
{\uldb Section B.4.17: BT, BTC, BTR, BTS: Bit Test}{\v section_b_4_17}\par\sb0
{\uldb Section B.4.18: CALL: Call Subroutine}{\v section_b_4_18}\par\sb0
{\uldb Section B.4.19: CBW, CWD, CDQ, CWDE: Sign Extensions}{\v section_b_4_19}\par\sb0
{\uldb Section B.4.20: CLC, CLD, CLI, CLTS: Clear Flags}{\v section_b_4_20}\par\sb0
{\uldb Section B.4.21: CLFLUSH: Flush Cache Line}{\v section_b_4_21}\par\sb0
{\uldb Section B.4.22: CMC: Complement Carry Flag}{\v section_b_4_22}\par\sb0
{\uldb Section B.4.23: CMOVcc: Conditional Move}{\v section_b_4_23}\par\sb0
{\uldb Section B.4.24: CMP: Compare Integers}{\v section_b_4_24}\par\sb0
{\uldb Section B.4.25: CMPccPD: Packed Double-Precision FP Compare        }{\v section_b_4_25}\par\sb0
{\uldb Section B.4.26: CMPccPS: Packed Single-Precision FP Compare        }{\v section_b_4_26}\par\sb0
{\uldb Section B.4.27: CMPSB, CMPSW, CMPSD: Compare Strings}{\v section_b_4_27}\par\sb0
{\uldb Section B.4.28: CMPccSD: Scalar Double-Precision FP Compare        }{\v section_b_4_28}\par\sb0
{\uldb Section B.4.29: CMPccSS: Scalar Single-Precision FP Compare        }{\v section_b_4_29}\par\sb0
{\uldb Section B.4.30: CMPXCHG, CMPXCHG486: Compare and Exchange}{\v section_b_4_30}\par\sb0
{\uldb Section B.4.31: CMPXCHG8B: Compare and Exchange Eight Bytes}{\v section_b_4_31}\par\sb0
{\uldb Section B.4.32: COMISD: Scalar Ordered Double-Precision FP Compare and Set EFLAGS}{\v section_b_4_32}\par\sb0
{\uldb Section B.4.33: COMISS: Scalar Ordered Single-Precision FP Compare and Set EFLAGS}{\v section_b_4_33}\par\sb0
{\uldb Section B.4.34: CPUID: Get CPU Identification Code}{\v section_b_4_34}\par\sb0
{\uldb Section B.4.35: CVTDQ2PD: Packed Signed INT32 to Packed Double-Precision FP Conversion}{\v section_b_4_35}\par\sb0
{\uldb Section B.4.36: CVTDQ2PS: Packed Signed INT32 to Packed Single-Precision FP Conversion}{\v section_b_4_36}\par\sb0
{\uldb Section B.4.37: CVTPD2DQ: Packed Double-Precision FP to Packed Signed INT32 Conversion}{\v section_b_4_37}\par\sb0
{\uldb Section B.4.38: CVTPD2PI: Packed Double-Precision FP to Packed Signed INT32 Conversion}{\v section_b_4_38}\par\sb0
{\uldb Section B.4.39: CVTPD2PS: Packed Double-Precision FP to Packed Single-Precision FP Conversion}{\v section_b_4_39}\par\sb0
{\uldb Section B.4.40: CVTPI2PD: Packed Signed INT32 to Packed Double-Precision FP Conversion}{\v section_b_4_40}\par\sb0
{\uldb Section B.4.41: CVTPI2PS: Packed Signed INT32 to Packed Single-FP Conversion}{\v section_b_4_41}\par\sb0
{\uldb Section B.4.42: CVTPS2DQ: Packed Single-Precision FP to Packed Signed INT32 Conversion}{\v section_b_4_42}\par\sb0
{\uldb Section B.4.43: CVTPS2PD: Packed Single-Precision FP to Packed Double-Precision FP Conversion}{\v section_b_4_43}\par\sb0
{\uldb Section B.4.44: CVTPS2PI: Packed Single-Precision FP to Packed Signed INT32 Conversion}{\v section_b_4_44}\par\sb0
{\uldb Section B.4.45: CVTSD2SI: Scalar Double-Precision FP to Signed INT32 Conversion}{\v section_b_4_45}\par\sb0
{\uldb Section B.4.46: CVTSD2SS: Scalar Double-Precision FP to Scalar Single-Precision FP Conversion}{\v section_b_4_46}\par\sb0
{\uldb Section B.4.47: CVTSI2SD: Signed INT32 to Scalar Double-Precision FP Conversion}{\v section_b_4_47}\par\sb0
{\uldb Section B.4.48: CVTSI2SS: Signed INT32 to Scalar Single-Precision FP Conversion}{\v section_b_4_48}\par\sb0
{\uldb Section B.4.49: CVTSS2SD: Scalar Single-Precision FP to Scalar Double-Precision FP Conversion}{\v section_b_4_49}\par\sb0
{\uldb Section B.4.50: CVTSS2SI: Scalar Single-Precision FP to Signed INT32 Conversion}{\v section_b_4_50}\par\sb0
{\uldb Section B.4.51: CVTTPD2DQ: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation}{\v section_b_4_51}\par\sb0
{\uldb Section B.4.52: CVTTPD2PI: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation}{\v section_b_4_52}\par\sb0
{\uldb Section B.4.53: CVTTPS2DQ: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation}{\v section_b_4_53}\par\sb0
{\uldb Section B.4.54: CVTTPS2PI: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation}{\v section_b_4_54}\par\sb0
{\uldb Section B.4.55: CVTTSD2SI: Scalar Double-Precision FP to Signed INT32 Conversion with Truncation}{\v section_b_4_55}\par\sb0
{\uldb Section B.4.56: CVTTSS2SI: Scalar Single-Precision FP to Signed INT32 Conversion with Truncation}{\v section_b_4_56}\par\sb0
{\uldb Section B.4.57: DAA, DAS: Decimal Adjustments}{\v section_b_4_57}\par\sb0
{\uldb Section B.4.58: DEC: Decrement Integer}{\v section_b_4_58}\par\sb0
{\uldb Section B.4.59: DIV: Unsigned Integer Divide}{\v section_b_4_59}\par\sb0
{\uldb Section B.4.60: DIVPD: Packed Double-Precision FP Divide}{\v section_b_4_60}\par\sb0
{\uldb Section B.4.61: DIVPS: Packed Single-Precision FP Divide}{\v section_b_4_61}\par\sb0
{\uldb Section B.4.62: DIVSD: Scalar Double-Precision FP Divide}{\v section_b_4_62}\par\sb0
{\uldb Section B.4.63: DIVSS: Scalar Single-Precision FP Divide}{\v section_b_4_63}\par\sb0
{\uldb Section B.4.64: EMMS: Empty MMX State}{\v section_b_4_64}\par\sb0
{\uldb Section B.4.65: ENTER: Create Stack Frame}{\v section_b_4_65}\par\sb0
{\uldb Section B.4.66: F2XM1: Calculate 2**X-1}{\v section_b_4_66}\par\sb0
{\uldb Section B.4.67: FABS: Floating-Point Absolute Value}{\v section_b_4_67}\par\sb0
{\uldb Section B.4.68: FADD, FADDP: Floating-Point Addition}{\v section_b_4_68}\par\sb0
{\uldb Section B.4.69: FBLD, FBSTP: BCD Floating-Point Load and Store}{\v section_b_4_69}\par\sb0
{\uldb Section B.4.70: FCHS: Floating-Point Change Sign}{\v section_b_4_70}\par\sb0
{\uldb Section B.4.71: FCLEX, FNCLEX: Clear Floating-Point Exceptions}{\v section_b_4_71}\par\sb0
{\uldb Section B.4.72: FCMOVcc: Floating-Point Conditional Move}{\v section_b_4_72}\par\sb0
{\uldb Section B.4.73: FCOM, FCOMP, FCOMPP, FCOMI, FCOMIP: Floating-Point Compare}{\v section_b_4_73}\par\sb0
{\uldb Section B.4.74: FCOS: Cosine}{\v section_b_4_74}\par\sb0
{\uldb Section B.4.75: FDECSTP: Decrement Floating-Point Stack Pointer}{\v section_b_4_75}\par\sb0
{\uldb Section B.4.76: FxDISI, FxENI: Disable and Enable Floating-Point Interrupts}{\v section_b_4_76}\par\sb0
{\uldb Section B.4.77: FDIV, FDIVP, FDIVR, FDIVRP: Floating-Point Division}{\v section_b_4_77}\par\sb0
{\uldb Section B.4.78: FEMMS: Faster Enter/Exit of the MMX or floating-point state}{\v section_b_4_78}\par\sb0
{\uldb Section B.4.79: FFREE: Flag Floating-Point Register as Unused}{\v section_b_4_79}\par\sb0
{\uldb Section B.4.80: FIADD: Floating-Point/Integer Addition}{\v section_b_4_80}\par\sb0
{\uldb Section B.4.81: FICOM, FICOMP: Floating-Point/Integer Compare}{\v section_b_4_81}\par\sb0
{\uldb Section B.4.82: FIDIV, FIDIVR: Floating-Point/Integer Division}{\v section_b_4_82}\par\sb0
{\uldb Section B.4.83: FILD, FIST, FISTP: Floating-Point/Integer Conversion}{\v section_b_4_83}\par\sb0
{\uldb Section B.4.84: FIMUL: Floating-Point/Integer Multiplication}{\v section_b_4_84}\par\sb0
{\uldb Section B.4.85: FINCSTP: Increment Floating-Point Stack Pointer}{\v section_b_4_85}\par\sb0
{\uldb Section B.4.86: FINIT, FNINIT: Initialise Floating-Point Unit}{\v section_b_4_86}\par\sb0
{\uldb Section B.4.87: FISUB: Floating-Point/Integer Subtraction}{\v section_b_4_87}\par\sb0
{\uldb Section B.4.88: FLD: Floating-Point Load}{\v section_b_4_88}\par\sb0
{\uldb Section B.4.89: FLDxx: Floating-Point Load Constants}{\v section_b_4_89}\par\sb0
{\uldb Section B.4.90: FLDCW: Load Floating-Point Control Word}{\v section_b_4_90}\par\sb0
{\uldb Section B.4.91: FLDENV: Load Floating-Point Environment}{\v section_b_4_91}\par\sb0
{\uldb Section B.4.92: FMUL, FMULP: Floating-Point Multiply}{\v section_b_4_92}\par\sb0
{\uldb Section B.4.93: FNOP: Floating-Point No Operation}{\v section_b_4_93}\par\sb0
{\uldb Section B.4.94: FPATAN, FPTAN: Arctangent and Tangent}{\v section_b_4_94}\par\sb0
{\uldb Section B.4.95: FPREM, FPREM1: Floating-Point Partial Remainder}{\v section_b_4_95}\par\sb0
{\uldb Section B.4.96: FRNDINT: Floating-Point Round to Integer}{\v section_b_4_96}\par\sb0
{\uldb Section B.4.97: FSAVE, FRSTOR: Save/Restore Floating-Point State}{\v section_b_4_97}\par\sb0
{\uldb Section B.4.98: FSCALE: Scale Floating-Point Value by Power of Two}{\v section_b_4_98}\par\sb0
{\uldb Section B.4.99: FSETPM: Set Protected Mode}{\v section_b_4_99}\par\sb0
{\uldb Section B.4.100: FSIN, FSINCOS: Sine and Cosine}{\v section_b_4_100}\par\sb0
{\uldb Section B.4.101: FSQRT: Floating-Point Square Root}{\v section_b_4_101}\par\sb0
{\uldb Section B.4.102: FST, FSTP: Floating-Point Store}{\v section_b_4_102}\par\sb0
{\uldb Section B.4.103: FSTCW: Store Floating-Point Control Word}{\v section_b_4_103}\par\sb0
{\uldb Section B.4.104: FSTENV: Store Floating-Point Environment}{\v section_b_4_104}\par\sb0
{\uldb Section B.4.105: FSTSW: Store Floating-Point Status Word}{\v section_b_4_105}\par\sb0
{\uldb Section B.4.106: FSUB, FSUBP, FSUBR, FSUBRP: Floating-Point Subtract}{\v section_b_4_106}\par\sb0
{\uldb Section B.4.107: FTST: Test ST0 Against Zero}{\v section_b_4_107}\par\sb0
{\uldb Section B.4.108: FUCOMxx: Floating-Point Unordered Compare}{\v section_b_4_108}\par\sb0
{\uldb Section B.4.109: FXAM: Examine Class of Value in ST0}{\v section_b_4_109}\par\sb0
{\uldb Section B.4.110: FXCH: Floating-Point Exchange}{\v section_b_4_110}\par\sb0
{\uldb Section B.4.111: FXRSTOR: Restore FP, MMX and SSE State}{\v section_b_4_111}\par\sb0
{\uldb Section B.4.112: FXSAVE: Store FP, MMX and SSE State}{\v section_b_4_112}\par\sb0
{\uldb Section B.4.113: FXTRACT: Extract Exponent and Significand}{\v section_b_4_113}\par\sb0
{\uldb Section B.4.114: FYL2X, FYL2XP1: Compute Y times Log2(X) or Log2(X+1)}{\v section_b_4_114}\par\sb0
{\uldb Section B.4.115: HLT: Halt Processor}{\v section_b_4_115}\par\sb0
{\uldb Section B.4.116: IBTS: Insert Bit String}{\v section_b_4_116}\par\sb0
{\uldb Section B.4.117: IDIV: Signed Integer Divide}{\v section_b_4_117}\par\sb0
{\uldb Section B.4.118: IMUL: Signed Integer Multiply}{\v section_b_4_118}\par\sb0
{\uldb Section B.4.119: IN: Input from I/O Port}{\v section_b_4_119}\par\sb0
{\uldb Section B.4.120: INC: Increment Integer}{\v section_b_4_120}\par\sb0
{\uldb Section B.4.121: INSB, INSW, INSD: Input String from I/O Port}{\v section_b_4_121}\par\sb0
{\uldb Section B.4.122: INT: Software Interrupt}{\v section_b_4_122}\par\sb0
{\uldb Section B.4.123: INT3, INT1, ICEBP, INT01: Breakpoints}{\v section_b_4_123}\par\sb0
{\uldb Section B.4.124: INTO: Interrupt if Overflow}{\v section_b_4_124}\par\sb0
{\uldb Section B.4.125: INVD: Invalidate Internal Caches}{\v section_b_4_125}\par\sb0
{\uldb Section B.4.126: INVLPG: Invalidate TLB Entry}{\v section_b_4_126}\par\sb0
{\uldb Section B.4.127: IRET, IRETW, IRETD: Return from Interrupt}{\v section_b_4_127}\par\sb0
{\uldb Section B.4.128: Jcc: Conditional Branch}{\v section_b_4_128}\par\sb0
{\uldb Section B.4.129: JCXZ, JECXZ: Jump if CX/ECX Zero}{\v section_b_4_129}\par\sb0
{\uldb Section B.4.130: JMP: Jump}{\v section_b_4_130}\par\sb0
{\uldb Section B.4.131: LAHF: Load AH from Flags}{\v section_b_4_131}\par\sb0
{\uldb Section B.4.132: LAR: Load Access Rights}{\v section_b_4_132}\par\sb0
{\uldb Section B.4.133: LDMXCSR: Load Streaming SIMD Extension Control/Status}{\v section_b_4_133}\par\sb0
{\uldb Section B.4.134: LDS, LES, LFS, LGS, LSS: Load Far Pointer}{\v section_b_4_134}\par\sb0
{\uldb Section B.4.135: LEA: Load Effective Address}{\v section_b_4_135}\par\sb0
{\uldb Section B.4.136: LEAVE: Destroy Stack Frame}{\v section_b_4_136}\par\sb0
{\uldb Section B.4.137: LFENCE: Load Fence}{\v section_b_4_137}\par\sb0
{\uldb Section B.4.138: LGDT, LIDT, LLDT: Load Descriptor Tables}{\v section_b_4_138}\par\sb0
{\uldb Section B.4.139: LMSW: Load/Store Machine Status Word}{\v section_b_4_139}\par\sb0
{\uldb Section B.4.140: LOADALL, LOADALL286: Load Processor State}{\v section_b_4_140}\par\sb0
{\uldb Section B.4.141: LODSB, LODSW, LODSD: Load from String}{\v section_b_4_141}\par\sb0
{\uldb Section B.4.142: LOOP, LOOPE, LOOPZ, LOOPNE, LOOPNZ: Loop with Counter}{\v section_b_4_142}\par\sb0
{\uldb Section B.4.143: LSL: Load Segment Limit}{\v section_b_4_143}\par\sb0
{\uldb Section B.4.144: LTR: Load Task Register}{\v section_b_4_144}\par\sb0
{\uldb Section B.4.145: MASKMOVDQU: Byte Mask Write}{\v section_b_4_145}\par\sb0
{\uldb Section B.4.146: MASKMOVQ: Byte Mask Write}{\v section_b_4_146}\par\sb0
{\uldb Section B.4.147: MAXPD: Return Packed Double-Precision FP Maximum}{\v section_b_4_147}\par\sb0
{\uldb Section B.4.148: MAXPS: Return Packed Single-Precision FP Maximum}{\v section_b_4_148}\par\sb0
{\uldb Section B.4.149: MAXSD: Return Scalar Double-Precision FP Maximum}{\v section_b_4_149}\par\sb0
{\uldb Section B.4.150: MAXSS: Return Scalar Single-Precision FP Maximum}{\v section_b_4_150}\par\sb0
{\uldb Section B.4.151: MFENCE: Memory Fence}{\v section_b_4_151}\par\sb0
{\uldb Section B.4.152: MINPD: Return Packed Double-Precision FP Minimum}{\v section_b_4_152}\par\sb0
{\uldb Section B.4.153: MINPS: Return Packed Single-Precision FP Minimum}{\v section_b_4_153}\par\sb0
{\uldb Section B.4.154: MINSD: Return Scalar Double-Precision FP Minimum}{\v section_b_4_154}\par\sb0
{\uldb Section B.4.155: MINSS: Return Scalar Single-Precision FP Minimum}{\v section_b_4_155}\par\sb0
{\uldb Section B.4.156: MOV: Move Data}{\v section_b_4_156}\par\sb0
{\uldb Section B.4.157: MOVAPD: Move Aligned Packed Double-Precision FP Values}{\v section_b_4_157}\par\sb0
{\uldb Section B.4.158: MOVAPS: Move Aligned Packed Single-Precision FP Values}{\v section_b_4_158}\par\sb0
{\uldb Section B.4.159: MOVD: Move Doubleword to/from MMX Register}{\v section_b_4_159}\par\sb0
{\uldb Section B.4.160: MOVDQ2Q: Move Quadword from XMM to MMX register.}{\v section_b_4_160}\par\sb0
{\uldb Section B.4.161: MOVDQA: Move Aligned Double Quadword}{\v section_b_4_161}\par\sb0
{\uldb Section B.4.162: MOVDQU: Move Unaligned Double Quadword}{\v section_b_4_162}\par\sb0
{\uldb Section B.4.163: MOVHLPS: Move Packed Single-Precision FP High to Low}{\v section_b_4_163}\par\sb0
{\uldb Section B.4.164: MOVHPD: Move High Packed Double-Precision FP}{\v section_b_4_164}\par\sb0
{\uldb Section B.4.165: MOVHPS: Move High Packed Single-Precision FP}{\v section_b_4_165}\par\sb0
{\uldb Section B.4.166: MOVLHPS: Move Packed Single-Precision FP Low to High}{\v section_b_4_166}\par\sb0
{\uldb Section B.4.167: MOVLPD: Move Low Packed Double-Precision FP}{\v section_b_4_167}\par\sb0
{\uldb Section B.4.168: MOVLPS: Move Low Packed Single-Precision FP}{\v section_b_4_168}\par\sb0
{\uldb Section B.4.169: MOVMSKPD: Extract Packed Double-Precision FP Sign Mask}{\v section_b_4_169}\par\sb0
{\uldb Section B.4.170: MOVMSKPS: Extract Packed Single-Precision FP Sign Mask}{\v section_b_4_170}\par\sb0
{\uldb Section B.4.171: MOVNTDQ: Move Double Quadword Non Temporal}{\v section_b_4_171}\par\sb0
{\uldb Section B.4.172: MOVNTI: Move Doubleword Non Temporal}{\v section_b_4_172}\par\sb0
{\uldb Section B.4.173: MOVNTPD: Move Aligned Four Packed Single-Precision FP Values Non Temporal}{\v section_b_4_173}\par\sb0
{\uldb Section B.4.174: MOVNTPS: Move Aligned Four Packed Single-Precision FP Values Non Temporal}{\v section_b_4_174}\par\sb0
{\uldb Section B.4.175: MOVNTQ: Move Quadword Non Temporal}{\v section_b_4_175}\par\sb0
{\uldb Section B.4.176: MOVQ: Move Quadword to/from MMX Register}{\v section_b_4_176}\par\sb0
{\uldb Section B.4.177: MOVQ2DQ: Move Quadword from MMX to XMM register.}{\v section_b_4_177}\par\sb0
{\uldb Section B.4.178: MOVSB, MOVSW, MOVSD: Move String}{\v section_b_4_178}\par\sb0
{\uldb Section B.4.179: MOVSD: Move Scalar Double-Precision FP Value}{\v section_b_4_179}\par\sb0
{\uldb Section B.4.180: MOVSS: Move Scalar Single-Precision FP Value}{\v section_b_4_180}\par\sb0
{\uldb Section B.4.181: MOVSX, MOVZX: Move Data with Sign or Zero Extend}{\v section_b_4_181}\par\sb0
{\uldb Section B.4.182: MOVUPD: Move Unaligned Packed Double-Precision FP Values}{\v section_b_4_182}\par\sb0
{\uldb Section B.4.183: MOVUPS: Move Unaligned Packed Single-Precision FP Values}{\v section_b_4_183}\par\sb0
{\uldb Section B.4.184: MUL: Unsigned Integer Multiply}{\v section_b_4_184}\par\sb0
{\uldb Section B.4.185: MULPD: Packed Single-FP Multiply}{\v section_b_4_185}\par\sb0
{\uldb Section B.4.186: MULPS: Packed Single-FP Multiply}{\v section_b_4_186}\par\sb0
{\uldb Section B.4.187: MULSD: Scalar Single-FP Multiply}{\v section_b_4_187}\par\sb0
{\uldb Section B.4.188: MULSS: Scalar Single-FP Multiply}{\v section_b_4_188}\par\sb0
{\uldb Section B.4.189: NEG, NOT: Two's and One's Complement}{\v section_b_4_189}\par\sb0
{\uldb Section B.4.190: NOP: No Operation}{\v section_b_4_190}\par\sb0
{\uldb Section B.4.191: OR: Bitwise OR}{\v section_b_4_191}\par\sb0
{\uldb Section B.4.192: ORPD: Bit-wise Logical OR of Double-Precision FP Data}{\v section_b_4_192}\par\sb0
{\uldb Section B.4.193: ORPS: Bit-wise Logical OR of Single-Precision FP Data}{\v section_b_4_193}\par\sb0
{\uldb Section B.4.194: OUT: Output Data to I/O Port}{\v section_b_4_194}\par\sb0
{\uldb Section B.4.195: OUTSB, OUTSW, OUTSD: Output String to I/O Port}{\v section_b_4_195}\par\sb0
{\uldb Section B.4.196: PACKSSDW, PACKSSWB, PACKUSWB: Pack Data}{\v section_b_4_196}\par\sb0
{\uldb Section B.4.197: PADDB, PADDW, PADDD: Add Packed Integers}{\v section_b_4_197}\par\sb0
{\uldb Section B.4.198: PADDQ: Add Packed Quadword Integers}{\v section_b_4_198}\par\sb0
{\uldb Section B.4.199: PADDSB, PADDSW: Add Packed Signed Integers With Saturation}{\v section_b_4_199}\par\sb0
{\uldb Section B.4.200: PADDSIW: MMX Packed Addition to Implicit Destination}{\v section_b_4_200}\par\sb0
{\uldb Section B.4.201: PADDUSB, PADDUSW: Add Packed Unsigned Integers With Saturation}{\v section_b_4_201}\par\sb0
{\uldb Section B.4.202: PAND, PANDN: MMX Bitwise AND and AND-NOT}{\v section_b_4_202}\par\sb0
{\uldb Section B.4.203: PAUSE: Spin Loop Hint}{\v section_b_4_203}\par\sb0
{\uldb Section B.4.204: PAVEB: MMX Packed Average}{\v section_b_4_204}\par\sb0
{\uldb Section B.4.205: PAVGB PAVGW: Average Packed Integers}{\v section_b_4_205}\par\sb0
{\uldb Section B.4.206: PAVGUSB: Average of unsigned packed 8-bit values}{\v section_b_4_206}\par\sb0
{\uldb Section B.4.207: PCMPxx: Compare Packed Integers.}{\v section_b_4_207}\par\sb0
{\uldb Section B.4.208: PDISTIB: MMX Packed Distance and Accumulate with Implied Register}{\v section_b_4_208}\par\sb0
{\uldb Section B.4.209: PEXTRW: Extract Word}{\v section_b_4_209}\par\sb0
{\uldb Section B.4.210: PF2ID: Packed Single-Precision FP to Integer Convert}{\v section_b_4_210}\par\sb0
{\uldb Section B.4.211: PF2IW: Packed Single-Precision FP to Integer Word Convert}{\v section_b_4_211}\par\sb0
{\uldb Section B.4.212: PFACC: Packed Single-Precision FP Accumulate}{\v section_b_4_212}\par\sb0
{\uldb Section B.4.213: PFADD: Packed Single-Precision FP Addition}{\v section_b_4_213}\par\sb0
{\uldb Section B.4.214: PFCMPxx: Packed Single-Precision FP Compare   }{\v section_b_4_214}\par\sb0
{\uldb Section B.4.215: PFMAX: Packed Single-Precision FP Maximum}{\v section_b_4_215}\par\sb0
{\uldb Section B.4.216: PFMIN: Packed Single-Precision FP Minimum}{\v section_b_4_216}\par\sb0
{\uldb Section B.4.217: PFMUL: Packed Single-Precision FP Multiply}{\v section_b_4_217}\par\sb0
{\uldb Section B.4.218: PFNACC: Packed Single-Precision FP Negative Accumulate}{\v section_b_4_218}\par\sb0
{\uldb Section B.4.219: PFPNACC: Packed Single-Precision FP Mixed Accumulate}{\v section_b_4_219}\par\sb0
{\uldb Section B.4.220: PFRCP: Packed Single-Precision FP Reciprocal Approximation}{\v section_b_4_220}\par\sb0
{\uldb Section B.4.221: PFRCPIT1: Packed Single-Precision FP Reciprocal, First Iteration Step}{\v section_b_4_221}\par\sb0
{\uldb Section B.4.222: PFRCPIT2: Packed Single-Precision FP Reciprocal/ Reciprocal Square Root, Second Iteration Step}{\v section_b_4_222}\par\sb0
{\uldb Section B.4.223: PFRSQIT1: Packed Single-Precision FP Reciprocal Square Root, First Iteration Step}{\v section_b_4_223}\par\sb0
{\uldb Section B.4.224: PFRSQRT: Packed Single-Precision FP Reciprocal Square Root Approximation}{\v section_b_4_224}\par\sb0
{\uldb Section B.4.225: PFSUB: Packed Single-Precision FP Subtract}{\v section_b_4_225}\par\sb0
{\uldb Section B.4.226: PFSUBR: Packed Single-Precision FP Reverse Subtract}{\v section_b_4_226}\par\sb0
{\uldb Section B.4.227: PI2FD: Packed Doubleword Integer to Single-Precision FP Convert}{\v section_b_4_227}\par\sb0
{\uldb Section B.4.228: PF2IW: Packed Word Integer to Single-Precision FP Convert}{\v section_b_4_228}\par\sb0
{\uldb Section B.4.229: PINSRW: Insert Word}{\v section_b_4_229}\par\sb0
{\uldb Section B.4.230: PMACHRIW: Packed Multiply and Accumulate with Rounding}{\v section_b_4_230}\par\sb0
{\uldb Section B.4.231: PMADDWD: MMX Packed Multiply and Add}{\v section_b_4_231}\par\sb0
{\uldb Section B.4.232: PMAGW: MMX Packed Magnitude}{\v section_b_4_232}\par\sb0
{\uldb Section B.4.233: PMAXSW: Packed Signed Integer Word Maximum}{\v section_b_4_233}\par\sb0
{\uldb Section B.4.234: PMAXUB: Packed Unsigned Integer Byte Maximum}{\v section_b_4_234}\par\sb0
{\uldb Section B.4.235: PMINSW: Packed Signed Integer Word Minimum}{\v section_b_4_235}\par\sb0
{\uldb Section B.4.236: PMINUB: Packed Unsigned Integer Byte Minimum}{\v section_b_4_236}\par\sb0
{\uldb Section B.4.237: PMOVMSKB: Move Byte Mask To Integer}{\v section_b_4_237}\par\sb0
{\uldb Section B.4.238: PMULHRWC, PMULHRIW: Multiply Packed 16-bit Integers With Rounding, and Store High Word}{\v section_b_4_238}\par\sb0
{\uldb Section B.4.239: PMULHRWA: Multiply Packed 16-bit Integers With Rounding, and Store High Word}{\v section_b_4_239}\par\sb0
{\uldb Section B.4.240: PMULHUW: Multiply Packed 16-bit Integers, and Store High Word}{\v section_b_4_240}\par\sb0
{\uldb Section B.4.241: PMULHW, PMULLW: Multiply Packed 16-bit Integers, and Store}{\v section_b_4_241}\par\sb0
{\uldb Section B.4.242: PMULUDQ: Multiply Packed Unsigned 32-bit Integers, and Store.}{\v section_b_4_242}\par\sb0
{\uldb Section B.4.243: PMVccZB: MMX Packed Conditional Move}{\v section_b_4_243}\par\sb0
{\uldb Section B.4.244: POP: Pop Data from Stack}{\v section_b_4_244}\par\sb0
{\uldb Section B.4.245: POPAx: Pop All General-Purpose Registers}{\v section_b_4_245}\par\sb0
{\uldb Section B.4.246: POPFx: Pop Flags Register}{\v section_b_4_246}\par\sb0
{\uldb Section B.4.247: POR: MMX Bitwise OR}{\v section_b_4_247}\par\sb0
{\uldb Section B.4.248: PREFETCH: Prefetch Data Into Caches}{\v section_b_4_248}\par\sb0
{\uldb Section B.4.249: PREFETCHh: Prefetch Data Into Caches    }{\v section_b_4_249}\par\sb0
{\uldb Section B.4.250: PSADBW: Packed Sum of Absolute Differences}{\v section_b_4_250}\par\sb0
{\uldb Section B.4.251: PSHUFD: Shuffle Packed Doublewords}{\v section_b_4_251}\par\sb0
{\uldb Section B.4.252: PSHUFHW: Shuffle Packed High Words}{\v section_b_4_252}\par\sb0
{\uldb Section B.4.253: PSHUFLW: Shuffle Packed Low Words}{\v section_b_4_253}\par\sb0
{\uldb Section B.4.254: PSHUFW: Shuffle Packed Words}{\v section_b_4_254}\par\sb0
{\uldb Section B.4.255: PSLLx: Packed Data Bit Shift Left Logical}{\v section_b_4_255}\par\sb0
{\uldb Section B.4.256: PSRAx: Packed Data Bit Shift Right Arithmetic}{\v section_b_4_256}\par\sb0
{\uldb Section B.4.257: PSRLx: Packed Data Bit Shift Right Logical}{\v section_b_4_257}\par\sb0
{\uldb Section B.4.258: PSUBx: Subtract Packed Integers}{\v section_b_4_258}\par\sb0
{\uldb Section B.4.259: PSUBSxx, PSUBUSx: Subtract Packed Integers With Saturation}{\v section_b_4_259}\par\sb0
{\uldb Section B.4.260: PSUBSIW: MMX Packed Subtract with Saturation to Implied Destination}{\v section_b_4_260}\par\sb0
{\uldb Section B.4.261: PSWAPD: Swap Packed Data }{\v section_b_4_261}\par\sb0
{\uldb Section B.4.262: PUNPCKxxx: Unpack and Interleave Data}{\v section_b_4_262}\par\sb0
{\uldb Section B.4.263: PUSH: Push Data on Stack}{\v section_b_4_263}\par\sb0
{\uldb Section B.4.264: PUSHAx: Push All General-Purpose Registers}{\v section_b_4_264}\par\sb0
{\uldb Section B.4.265: PUSHFx: Push Flags Register}{\v section_b_4_265}\par\sb0
{\uldb Section B.4.266: PXOR: MMX Bitwise XOR}{\v section_b_4_266}\par\sb0
{\uldb Section B.4.267: RCL, RCR: Bitwise Rotate through Carry Bit}{\v section_b_4_267}\par\sb0
{\uldb Section B.4.268: RCPPS: Packed Single-Precision FP Reciprocal}{\v section_b_4_268}\par\sb0
{\uldb Section B.4.269: RCPSS: Scalar Single-Precision FP Reciprocal}{\v section_b_4_269}\par\sb0
{\uldb Section B.4.270: RDMSR: Read Model-Specific Registers}{\v section_b_4_270}\par\sb0
{\uldb Section B.4.271: RDPMC: Read Performance-Monitoring Counters}{\v section_b_4_271}\par\sb0
{\uldb Section B.4.272: RDSHR: Read SMM Header Pointer Register}{\v section_b_4_272}\par\sb0
{\uldb Section B.4.273: RDTSC: Read Time-Stamp Counter}{\v section_b_4_273}\par\sb0
{\uldb Section B.4.274: RET, RETF, RETN: Return from Procedure Call}{\v section_b_4_274}\par\sb0
{\uldb Section B.4.275: ROL, ROR: Bitwise Rotate}{\v section_b_4_275}\par\sb0
{\uldb Section B.4.276: RSDC: Restore Segment Register and Descriptor}{\v section_b_4_276}\par\sb0
{\uldb Section B.4.277: RSLDT: Restore Segment Register and Descriptor}{\v section_b_4_277}\par\sb0
{\uldb Section B.4.278: RSM: Resume from System-Management Mode}{\v section_b_4_278}\par\sb0
{\uldb Section B.4.279: RSQRTPS: Packed Single-Precision FP Square Root Reciprocal}{\v section_b_4_279}\par\sb0
{\uldb Section B.4.280: RSQRTSS: Scalar Single-Precision FP Square Root Reciprocal}{\v section_b_4_280}\par\sb0
{\uldb Section B.4.281: RSTS: Restore TSR and Descriptor}{\v section_b_4_281}\par\sb0
{\uldb Section B.4.282: SAHF: Store AH to Flags}{\v section_b_4_282}\par\sb0
{\uldb Section B.4.283: SAL, SAR: Bitwise Arithmetic Shifts}{\v section_b_4_283}\par\sb0
{\uldb Section B.4.284: SALC: Set AL from Carry Flag}{\v section_b_4_284}\par\sb0
{\uldb Section B.4.285: SBB: Subtract with Borrow}{\v section_b_4_285}\par\sb0
{\uldb Section B.4.286: SCASB, SCASW, SCASD: Scan String}{\v section_b_4_286}\par\sb0
{\uldb Section B.4.287: SETcc: Set Register from Condition}{\v section_b_4_287}\par\sb0
{\uldb Section B.4.288: SFENCE: Store Fence}{\v section_b_4_288}\par\sb0
{\uldb Section B.4.289: SGDT, SIDT, SLDT: Store Descriptor Table Pointers}{\v section_b_4_289}\par\sb0
{\uldb Section B.4.290: SHL, SHR: Bitwise Logical Shifts}{\v section_b_4_290}\par\sb0
{\uldb Section B.4.291: SHLD, SHRD: Bitwise Double-Precision Shifts}{\v section_b_4_291}\par\sb0
{\uldb Section B.4.292: SHUFPD: Shuffle Packed Double-Precision FP Values}{\v section_b_4_292}\par\sb0
{\uldb Section B.4.293: SHUFPS: Shuffle Packed Single-Precision FP Values}{\v section_b_4_293}\par\sb0
{\uldb Section B.4.294: SMI: System Management Interrupt}{\v section_b_4_294}\par\sb0
{\uldb Section B.4.295: SMINT, SMINTOLD: Software SMM Entry (CYRIX)}{\v section_b_4_295}\par\sb0
{\uldb Section B.4.296: SMSW: Store Machine Status Word}{\v section_b_4_296}\par\sb0
{\uldb Section B.4.297: SQRTPD: Packed Double-Precision FP Square Root}{\v section_b_4_297}\par\sb0
{\uldb Section B.4.298: SQRTPS: Packed Single-Precision FP Square Root}{\v section_b_4_298}\par\sb0
{\uldb Section B.4.299: SQRTSD: Scalar Double-Precision FP Square Root}{\v section_b_4_299}\par\sb0
{\uldb Section B.4.300: SQRTSS: Scalar Single-Precision FP Square Root}{\v section_b_4_300}\par\sb0
{\uldb Section B.4.301: STC, STD, STI: Set Flags}{\v section_b_4_301}\par\sb0
{\uldb Section B.4.302: STMXCSR: Store Streaming SIMD Extension Control/Status}{\v section_b_4_302}\par\sb0
{\uldb Section B.4.303: STOSB, STOSW, STOSD: Store Byte to String}{\v section_b_4_303}\par\sb0
{\uldb Section B.4.304: STR: Store Task Register}{\v section_b_4_304}\par\sb0
{\uldb Section B.4.305: SUB: Subtract Integers}{\v section_b_4_305}\par\sb0
{\uldb Section B.4.306: SUBPD: Packed Double-Precision FP Subtract}{\v section_b_4_306}\par\sb0
{\uldb Section B.4.307: SUBPS: Packed Single-Precision FP Subtract}{\v section_b_4_307}\par\sb0
{\uldb Section B.4.308: SUBSD: Scalar Single-FP Subtract}{\v section_b_4_308}\par\sb0
{\uldb Section B.4.309: SUBSS: Scalar Single-FP Subtract}{\v section_b_4_309}\par\sb0
{\uldb Section B.4.310: SVDC: Save Segment Register and Descriptor}{\v section_b_4_310}\par\sb0
{\uldb Section B.4.311: SVLDT: Save LDTR and Descriptor}{\v section_b_4_311}\par\sb0
{\uldb Section B.4.312: SVTS: Save TSR and Descriptor}{\v section_b_4_312}\par\sb0
{\uldb Section B.4.313: SYSCALL: Call Operating System}{\v section_b_4_313}\par\sb0
{\uldb Section B.4.314: SYSENTER: Fast System Call}{\v section_b_4_314}\par\sb0
{\uldb Section B.4.315: SYSEXIT: Fast Return From System Call}{\v section_b_4_315}\par\sb0
{\uldb Section B.4.316: SYSRET: Return From Operating System}{\v section_b_4_316}\par\sb0
{\uldb Section B.4.317: TEST: Test Bits (notional bitwise AND)}{\v section_b_4_317}\par\sb0
{\uldb Section B.4.318: UCOMISD: Unordered Scalar Double-Precision FP compare and set EFLAGS}{\v section_b_4_318}\par\sb0
{\uldb Section B.4.319: UCOMISS: Unordered Scalar Single-Precision FP compare and set EFLAGS}{\v section_b_4_319}\par\sb0
{\uldb Section B.4.320: UD0, UD1, UD2: Undefined Instruction}{\v section_b_4_320}\par\sb0
{\uldb Section B.4.321: UMOV: User Move Data}{\v section_b_4_321}\par\sb0
{\uldb Section B.4.322: UNPCKHPD: Unpack and Interleave High Packed Double-Precision FP Values}{\v section_b_4_322}\par\sb0
{\uldb Section B.4.323: UNPCKHPS: Unpack and Interleave High Packed Single-Precision FP Values}{\v section_b_4_323}\par\sb0
{\uldb Section B.4.324: UNPCKLPD: Unpack and Interleave Low Packed Double-Precision FP Data}{\v section_b_4_324}\par\sb0
{\uldb Section B.4.325: UNPCKLPS: Unpack and Interleave Low Packed Single-Precision FP Data}{\v section_b_4_325}\par\sb0
{\uldb Section B.4.326: VERR, VERW: Verify Segment Readability/Writability}{\v section_b_4_326}\par\sb0
{\uldb Section B.4.327: WAIT: Wait for Floating-Point Processor}{\v section_b_4_327}\par\sb0
{\uldb Section B.4.328: WBINVD: Write Back and Invalidate Cache}{\v section_b_4_328}\par\sb0
{\uldb Section B.4.329: WRMSR: Write Model-Specific Registers}{\v section_b_4_329}\par\sb0
{\uldb Section B.4.330: WRSHR: Write SMM Header Pointer Register}{\v section_b_4_330}\par\sb0
{\uldb Section B.4.331: XADD: Exchange and Add}{\v section_b_4_331}\par\sb0
{\uldb Section B.4.332: XBTS: Extract Bit String}{\v section_b_4_332}\par\sb0
{\uldb Section B.4.333: XCHG: Exchange}{\v section_b_4_333}\par\sb0
{\uldb Section B.4.334: XLATB: Translate Byte in Lookup Table}{\v section_b_4_334}\par\sb0
{\uldb Section B.4.335: XOR: Bitwise Exclusive OR}{\v section_b_4_335}\par\sb0
{\uldb Section B.4.336: XORPD: Bitwise Logical XOR of Double-Precision FP Values}{\v section_b_4_336}\par\sb0
{\uldb Section B.4.337: XORPS: Bitwise Logical XOR of Single-Precision FP Values}{\v section_b_4_337}\par\sb0
\pard\sb120
\page
#{\footnote section_b_4_1}
${\footnote B.4.1. AAA, AAS, AAM, AAD: ASCII Adjustments}
+{\footnote browse:00221}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote AAA;
AAD;
AAM;
AAS}
\keepn\f2\b\fs30\sb60\sa60
B.4.1. {\f1 AAA}, {\f1 AAS}, {\f1 AAM}, {\f1 AAD}: ASCII Adjustments
\par\pard\plain\sb120
\keep\f1\sb120
AAA                           ; 37                   [8086]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
AAS                           ; 3F                   [8086]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
AAD                           ; D5 0A                [8086] \par\sb0
AAD imm                       ; D5 ib                [8086]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
AAM                           ; D4 0A                [8086] \par\sb0
AAM imm                       ; D4 ib                [8086]\par\sb0
\pard\f0\sb120
These instructions are used in conjunction with the add, subtract, multiply 
and divide instructions to perform binary-coded decimal arithmetic in 
{\i unpacked} (one BCD digit per byte \'96 easy to translate to and from 
{\f1 ASCII}, hence the instruction names) form. There are also packed BCD 
instructions {\f1 DAA} and {\f1 DAS}: see {\uldb section 
B.4.57}{\v section_b_4_57}.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 AAA} (ASCII Adjust After Addition) should be used after a one-byte 
{\f1 ADD} instruction whose destination was the {\f1 AL} register: by means 
of examining the value in the low nibble of {\f1 AL} and also the auxiliary 
carry flag {\f1 AF}, it determines whether the addition has overflowed, and 
adjusts it (and sets the carry flag) if so. You can add long BCD strings 
together by doing {\f1 ADD}/{\f1 AAA} on the low digits, then doing 
{\f1 ADC}/{\f1 AAA} on each subsequent digit.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 AAS} (ASCII Adjust AL After Subtraction) works similarly to {\f1 AAA}, 
but is for use after {\f1 SUB} instructions rather than {\f1 ADD}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 AAM} (ASCII Adjust AX After Multiply) is for use after you have 
multiplied two decimal digits together and left the result in {\f1 AL}: it 
divides {\f1 AL} by ten and stores the quotient in {\f1 AH}, leaving the 
remainder in {\f1 AL}. The divisor 10 can be changed by specifying an 
operand to the instruction: a particularly handy use of this is 
{\f1 AAM\'A016}, causing the two nibbles in {\f1 AL} to be separated into 
{\f1 AH} and {\f1 AL}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 AAD} (ASCII Adjust AX Before Division) performs the inverse operation 
to {\f1 AAM}: it multiplies {\f1 AH} by ten, adds it to {\f1 AL}, and sets 
{\f1 AH} to zero. Again, the multiplier 10 can be changed.
\par\pard\sb120
\page
#{\footnote section_b_4_2}
${\footnote B.4.2. ADC: Add with Carry}
+{\footnote browse:00222}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ADC}
\keepn\f2\b\fs30\sb60\sa60
B.4.2. {\f1 ADC}: Add with Carry
\par\pard\plain\sb120
\keep\f1\sb120
ADC r/m8,reg8                 ; 10 /r                [8086] \par\sb0
ADC r/m16,reg16               ; o16 11 /r            [8086] \par\sb0
ADC r/m32,reg32               ; o32 11 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ADC reg8,r/m8                 ; 12 /r                [8086] \par\sb0
ADC reg16,r/m16               ; o16 13 /r            [8086] \par\sb0
ADC reg32,r/m32               ; o32 13 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ADC r/m8,imm8                 ; 80 /2 ib             [8086] \par\sb0
ADC r/m16,imm16               ; o16 81 /2 iw         [8086] \par\sb0
ADC r/m32,imm32               ; o32 81 /2 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ADC r/m16,imm8                ; o16 83 /2 ib         [8086] \par\sb0
ADC r/m32,imm8                ; o32 83 /2 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ADC AL,imm8                   ; 14 ib                [8086] \par\sb0
ADC AX,imm16                  ; o16 15 iw            [8086] \par\sb0
ADC EAX,imm32                 ; o32 15 id            [386]\par\sb0
\pard\f0\sb120
{\f1 ADC} performs integer addition: it adds its two operands together, 
plus the value of the carry flag, and leaves the result in its destination 
(first) operand. The destination operand can be a register or a memory 
location. The source operand can be a register, a memory location or an 
immediate value.
\par\sb120
The flags are set according to the result of the operation: in particular, 
the carry flag is affected and can be used by a subsequent {\f1 ADC} 
instruction.
\par\sb120
In the forms with an 8-bit immediate second operand and a longer first 
operand, the second operand is considered to be signed, and is 
sign-extended to the length of the first operand. In these cases, the 
{\f1 BYTE} qualifier is necessary to force NASM to generate this form of 
the instruction.
\par\sb120
To add two numbers without also adding the contents of the carry flag, use 
{\f1 ADD} ({\uldb section B.4.3}{\v section_b_4_3}).
\par\sb120
\page
#{\footnote section_b_4_3}
${\footnote B.4.3. ADD: Add Integers}
+{\footnote browse:00223}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ADD}
\keepn\f2\b\fs30\sb60\sa60
B.4.3. {\f1 ADD}: Add Integers
\par\pard\plain\sb120
\keep\f1\sb120
ADD r/m8,reg8                 ; 00 /r                [8086] \par\sb0
ADD r/m16,reg16               ; o16 01 /r            [8086] \par\sb0
ADD r/m32,reg32               ; o32 01 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ADD reg8,r/m8                 ; 02 /r                [8086] \par\sb0
ADD reg16,r/m16               ; o16 03 /r            [8086] \par\sb0
ADD reg32,r/m32               ; o32 03 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ADD r/m8,imm8                 ; 80 /0 ib             [8086] \par\sb0
ADD r/m16,imm16               ; o16 81 /0 iw         [8086] \par\sb0
ADD r/m32,imm32               ; o32 81 /0 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ADD r/m16,imm8                ; o16 83 /0 ib         [8086] \par\sb0
ADD r/m32,imm8                ; o32 83 /0 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ADD AL,imm8                   ; 04 ib                [8086] \par\sb0
ADD AX,imm16                  ; o16 05 iw            [8086] \par\sb0
ADD EAX,imm32                 ; o32 05 id            [386]\par\sb0
\pard\f0\sb120
{\f1 ADD} performs integer addition: it adds its two operands together, and 
leaves the result in its destination (first) operand. The destination 
operand can be a register or a memory location. The source operand can be a 
register, a memory location or an immediate value.
\par\sb120
The flags are set according to the result of the operation: in particular, 
the carry flag is affected and can be used by a subsequent {\f1 ADC} 
instruction.
\par\sb120
In the forms with an 8-bit immediate second operand and a longer first 
operand, the second operand is considered to be signed, and is 
sign-extended to the length of the first operand. In these cases, the 
{\f1 BYTE} qualifier is necessary to force NASM to generate this form of 
the instruction.
\par\sb120
\page
#{\footnote section_b_4_4}
${\footnote B.4.4. ADDPD: ADD Packed Double-Precision FP Values}
+{\footnote browse:00224}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ADDPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.4. {\f1 ADDPD}: ADD Packed Double-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
ADDPD xmm1,xmm2/mem128        ; 66 0F 58 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 ADDPD} performs addition on each of two packed double-precision FP 
value pairs.
\par\sb120
\keep\f1\sb120
   dst[0-63]   := dst[0-63]   + src[0-63], \par\sb0
   dst[64-127] := dst[64-127] + src[64-127].\par\sb0
\pard\f0\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
\page
#{\footnote section_b_4_5}
${\footnote B.4.5. ADDPS: ADD Packed Single-Precision FP Values}
+{\footnote browse:00225}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ADDPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.5. {\f1 ADDPS}: ADD Packed Single-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
ADDPS xmm1,xmm2/mem128        ; 0F 58 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 ADDPS} performs addition on each of four packed single-precision FP 
value pairs
\par\sb120
\keep\f1\sb120
   dst[0-31]   := dst[0-31]   + src[0-31], \par\sb0
   dst[32-63]  := dst[32-63]  + src[32-63], \par\sb0
   dst[64-95]  := dst[64-95]  + src[64-95], \par\sb0
   dst[96-127] := dst[96-127] + src[96-127].\par\sb0
\pard\f0\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
\page
#{\footnote section_b_4_6}
${\footnote B.4.6. ADDSD: ADD Scalar Double-Precision FP Values}
+{\footnote browse:00226}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ADDSD}
\keepn\f2\b\fs30\sb60\sa60
B.4.6. {\f1 ADDSD}: ADD Scalar Double-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
ADDSD xmm1,xmm2/mem64         ; F2 0F 58 /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 ADDSD} adds the low double-precision FP values from the source and 
destination operands and stores the double-precision FP result in the 
destination operand.
\par\sb120
\keep\f1\sb120
   dst[0-63]   := dst[0-63] + src[0-63], \par\sb0
   dst[64-127) remains unchanged.\par\sb0
\pard\f0\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 64-bit memory location.
\par\sb120
\page
#{\footnote section_b_4_7}
${\footnote B.4.7. ADDSS: ADD Scalar Single-Precision FP Values}
+{\footnote browse:00227}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ADDSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.7. {\f1 ADDSS}: ADD Scalar Single-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
ADDSS xmm1,xmm2/mem32         ; F3 0F 58 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 ADDSS} adds the low single-precision FP values from the source and 
destination operands and stores the single-precision FP result in the 
destination operand.
\par\sb120
\keep\f1\sb120
   dst[0-31]   := dst[0-31] + src[0-31], \par\sb0
   dst[32-127] remains unchanged.\par\sb0
\pard\f0\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 32-bit memory location.
\par\sb120
\page
#{\footnote section_b_4_8}
${\footnote B.4.8. AND: Bitwise AND}
+{\footnote browse:00228}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote AND}
\keepn\f2\b\fs30\sb60\sa60
B.4.8. {\f1 AND}: Bitwise AND
\par\pard\plain\sb120
\keep\f1\sb120
AND r/m8,reg8                 ; 20 /r                [8086] \par\sb0
AND r/m16,reg16               ; o16 21 /r            [8086] \par\sb0
AND r/m32,reg32               ; o32 21 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
AND reg8,r/m8                 ; 22 /r                [8086] \par\sb0
AND reg16,r/m16               ; o16 23 /r            [8086] \par\sb0
AND reg32,r/m32               ; o32 23 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
AND r/m8,imm8                 ; 80 /4 ib             [8086] \par\sb0
AND r/m16,imm16               ; o16 81 /4 iw         [8086] \par\sb0
AND r/m32,imm32               ; o32 81 /4 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
AND r/m16,imm8                ; o16 83 /4 ib         [8086] \par\sb0
AND r/m32,imm8                ; o32 83 /4 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
AND AL,imm8                   ; 24 ib                [8086] \par\sb0
AND AX,imm16                  ; o16 25 iw            [8086] \par\sb0
AND EAX,imm32                 ; o32 25 id            [386]\par\sb0
\pard\f0\sb120
{\f1 AND} performs a bitwise AND operation between its two operands (i.e. 
each bit of the result is 1 if and only if the corresponding bits of the 
two inputs were both 1), and stores the result in the destination (first) 
operand. The destination operand can be a register or a memory location. 
The source operand can be a register, a memory location or an immediate 
value.
\par\sb120
In the forms with an 8-bit immediate second operand and a longer first 
operand, the second operand is considered to be signed, and is 
sign-extended to the length of the first operand. In these cases, the 
{\f1 BYTE} qualifier is necessary to force NASM to generate this form of 
the instruction.
\par\sb120
The {\f1 MMX} instruction {\f1 PAND} (see {\uldb section 
B.4.202}{\v section_b_4_202}) performs the same operation on the 64-bit 
{\f1 MMX} registers.
\par\sb120
\page
#{\footnote section_b_4_9}
${\footnote B.4.9. ANDNPD: Bitwise Logical AND NOT of Packed Double-Precision FP Values}
+{\footnote browse:00229}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ANDNPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.9. {\f1 ANDNPD}: Bitwise Logical AND NOT of Packed Double-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
ANDNPD xmm1,xmm2/mem128       ; 66 0F 55 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 ANDNPD} inverts the bits of the two double-precision floating-point 
values in the destination register, and then performs a logical AND between 
the two double-precision floating-point values in the source operand and 
the temporary inverted result, storing the result in the destination 
register.
\par\sb120
\keep\f1\sb120
   dst[0-63]   := src[0-63]   AND NOT dst[0-63], \par\sb0
   dst[64-127] := src[64-127] AND NOT dst[64-127].\par\sb0
\pard\f0\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
\page
#{\footnote section_b_4_10}
${\footnote B.4.10. ANDNPS: Bitwise Logical AND NOT of Packed Single-Precision FP Values}
+{\footnote browse:00230}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ANDNPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.10. {\f1 ANDNPS}: Bitwise Logical AND NOT of Packed Single-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
ANDNPS xmm1,xmm2/mem128       ; 0F 55 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 ANDNPS} inverts the bits of the four single-precision floating-point 
values in the destination register, and then performs a logical AND between 
the four single-precision floating-point values in the source operand and 
the temporary inverted result, storing the result in the destination 
register.
\par\sb120
\keep\f1\sb120
   dst[0-31]   := src[0-31]   AND NOT dst[0-31], \par\sb0
   dst[32-63]  := src[32-63]  AND NOT dst[32-63], \par\sb0
   dst[64-95]  := src[64-95]  AND NOT dst[64-95], \par\sb0
   dst[96-127] := src[96-127] AND NOT dst[96-127].\par\sb0
\pard\f0\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
\page
#{\footnote section_b_4_11}
${\footnote B.4.11. ANDPD: Bitwise Logical AND For Single FP}
+{\footnote browse:00231}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ANDPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.11. {\f1 ANDPD}: Bitwise Logical AND For Single FP
\par\pard\plain\sb120
\keep\f1\sb120
ANDPD xmm1,xmm2/mem128        ; 66 0F 54 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 ANDPD} performs a bitwise logical AND of the two double-precision 
floating point values in the source and destination operand, and stores the 
result in the destination register.
\par\sb120
\keep\f1\sb120
   dst[0-63]   := src[0-63]   AND dst[0-63], \par\sb0
   dst[64-127] := src[64-127] AND dst[64-127].\par\sb0
\pard\f0\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
\page
#{\footnote section_b_4_12}
${\footnote B.4.12. ANDPS: Bitwise Logical AND For Single FP}
+{\footnote browse:00232}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ANDPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.12. {\f1 ANDPS}: Bitwise Logical AND For Single FP
\par\pard\plain\sb120
\keep\f1\sb120
ANDPS xmm1,xmm2/mem128        ; 0F 54 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 ANDPS} performs a bitwise logical AND of the four single-precision 
floating point values in the source and destination operand, and stores the 
result in the destination register.
\par\sb120
\keep\f1\sb120
   dst[0-31]   := src[0-31]   AND dst[0-31], \par\sb0
   dst[32-63]  := src[32-63]  AND dst[32-63], \par\sb0
   dst[64-95]  := src[64-95]  AND dst[64-95], \par\sb0
   dst[96-127] := src[96-127] AND dst[96-127].\par\sb0
\pard\f0\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
\page
#{\footnote section_b_4_13}
${\footnote B.4.13. ARPL: Adjust RPL Field of Selector}
+{\footnote browse:00233}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ARPL;
RPL}
\keepn\f2\b\fs30\sb60\sa60
B.4.13. {\f1 ARPL}: Adjust RPL Field of Selector
\par\pard\plain\sb120
\keep\f1\sb120
ARPL r/m16,reg16              ; 63 /r                [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 ARPL} expects its two word operands to be segment selectors. It 
adjusts the {\f1 RPL} (requested privilege level \'96 stored in the bottom 
two bits of the selector) field of the destination (first) operand to 
ensure that it is no less (i.e. no more privileged than) the {\f1 RPL} 
field of the source operand. The zero flag is set if and only if a change 
had to be made.
\par\sb120
\page
#{\footnote section_b_4_14}
${\footnote B.4.14. BOUND: Check Array Index against Bounds}
+{\footnote browse:00234}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote BOUND}
\keepn\f2\b\fs30\sb60\sa60
B.4.14. {\f1 BOUND}: Check Array Index against Bounds
\par\pard\plain\sb120
\keep\f1\sb120
BOUND reg16,mem               ; o16 62 /r            [186] \par\sb0
BOUND reg32,mem               ; o32 62 /r            [386]\par\sb0
\pard\f0\sb120
{\f1 BOUND} expects its second operand to point to an area of memory 
containing two signed values of the same size as its first operand (i.e. 
two words for the 16-bit form; two doublewords for the 32-bit form). It 
performs two signed comparisons: if the value in the register passed as its 
first operand is less than the first of the in-memory values, or is greater 
than or equal to the second, it throws a {\f1 BR} exception. Otherwise, it 
does nothing.
\par\sb120
\page
#{\footnote section_b_4_15}
${\footnote B.4.15. BSF, BSR: Bit Scan}
+{\footnote browse:00235}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote BSF;
BSR}
\keepn\f2\b\fs30\sb60\sa60
B.4.15. {\f1 BSF}, {\f1 BSR}: Bit Scan
\par\pard\plain\sb120
\keep\f1\sb120
BSF reg16,r/m16               ; o16 0F BC /r         [386] \par\sb0
BSF reg32,r/m32               ; o32 0F BC /r         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
BSR reg16,r/m16               ; o16 0F BD /r         [386] \par\sb0
BSR reg32,r/m32               ; o32 0F BD /r         [386]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 BSF} searches for the least significant set bit in its source (second) 
operand, and if it finds one, stores the index in its destination (first) 
operand. If no set bit is found, the contents of the destination operand 
are undefined. If the source operand is zero, the zero flag is set.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 BSR} performs the same function, but searches from the top instead, so 
it finds the most significant set bit.
\par\pard\sb120
Bit indices are from 0 (least significant) to 15 or 31 (most significant). 
The destination operand can only be a register. The source operand can be a 
register or a memory location.
\par\sb120
\page
#{\footnote section_b_4_16}
${\footnote B.4.16. BSWAP: Byte Swap}
+{\footnote browse:00236}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote BSWAP}
\keepn\f2\b\fs30\sb60\sa60
B.4.16. {\f1 BSWAP}: Byte Swap
\par\pard\plain\sb120
\keep\f1\sb120
BSWAP reg32                   ; o32 0F C8+r          [486]\par\sb0
\pard\f0\sb120
{\f1 BSWAP} swaps the order of the four bytes of a 32-bit register: bits 
0-7 exchange places with bits 24-31, and bits 8-15 swap with bits 16-23. 
There is no explicit 16-bit equivalent: to byte-swap {\f1 AX}, {\f1 BX}, 
{\f1 CX} or {\f1 DX}, {\f1 XCHG} can be used. When {\f1 BSWAP} is used with 
a 16-bit register, the result is undefined.
\par\sb120
\page
#{\footnote section_b_4_17}
${\footnote B.4.17. BT, BTC, BTR, BTS: Bit Test}
+{\footnote browse:00237}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote BT;
BTC;
BTR;
BTS}
\keepn\f2\b\fs30\sb60\sa60
B.4.17. {\f1 BT}, {\f1 BTC}, {\f1 BTR}, {\f1 BTS}: Bit Test
\par\pard\plain\sb120
\keep\f1\sb120
BT r/m16,reg16                ; o16 0F A3 /r         [386] \par\sb0
BT r/m32,reg32                ; o32 0F A3 /r         [386] \par\sb0
BT r/m16,imm8                 ; o16 0F BA /4 ib      [386] \par\sb0
BT r/m32,imm8                 ; o32 0F BA /4 ib      [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
BTC r/m16,reg16               ; o16 0F BB /r         [386] \par\sb0
BTC r/m32,reg32               ; o32 0F BB /r         [386] \par\sb0
BTC r/m16,imm8                ; o16 0F BA /7 ib      [386] \par\sb0
BTC r/m32,imm8                ; o32 0F BA /7 ib      [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
BTR r/m16,reg16               ; o16 0F B3 /r         [386] \par\sb0
BTR r/m32,reg32               ; o32 0F B3 /r         [386] \par\sb0
BTR r/m16,imm8                ; o16 0F BA /6 ib      [386] \par\sb0
BTR r/m32,imm8                ; o32 0F BA /6 ib      [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
BTS r/m16,reg16               ; o16 0F AB /r         [386] \par\sb0
BTS r/m32,reg32               ; o32 0F AB /r         [386] \par\sb0
BTS r/m16,imm                 ; o16 0F BA /5 ib      [386] \par\sb0
BTS r/m32,imm                 ; o32 0F BA /5 ib      [386]\par\sb0
\pard\f0\sb120
These instructions all test one bit of their first operand, whose index is 
given by the second operand, and store the value of that bit into the carry 
flag. Bit indices are from 0 (least significant) to 15 or 31 (most 
significant).
\par\sb120
In addition to storing the original value of the bit into the carry flag, 
{\f1 BTR} also resets (clears) the bit in the operand itself. {\f1 BTS} 
sets the bit, and {\f1 BTC} complements the bit. {\f1 BT} does not modify 
its operands.
\par\sb120
The destination can be a register or a memory location. The source can be a 
register or an immediate value.
\par\sb120
If the destination operand is a register, the bit offset should be in the 
range 0-15 (for 16-bit operands) or 0-31 (for 32-bit operands). An 
immediate value outside these ranges will be taken modulo 16/32 by the 
processor.
\par\sb120
If the destination operand is a memory location, then an immediate bit 
offset follows the same rules as for a register. If the bit offset is in a 
register, then it can be anything within the signed range of the register 
used (ie, for a 32-bit operand, it can be (-2^31) to (2^31 \'96 1)
\par\sb120
\page
#{\footnote section_b_4_18}
${\footnote B.4.18. CALL: Call Subroutine}
+{\footnote browse:00238}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CALL;
far call;
near call}
\keepn\f2\b\fs30\sb60\sa60
B.4.18. {\f1 CALL}: Call Subroutine
\par\pard\plain\sb120
\keep\f1\sb120
CALL imm                      ; E8 rw/rd             [8086] \par\sb0
CALL imm:imm16                ; o16 9A iw iw         [8086] \par\sb0
CALL imm:imm32                ; o32 9A id iw         [386] \par\sb0
CALL FAR mem16                ; o16 FF /3            [8086] \par\sb0
CALL FAR mem32                ; o32 FF /3            [386] \par\sb0
CALL r/m16                    ; o16 FF /2            [8086] \par\sb0
CALL r/m32                    ; o32 FF /2            [386]\par\sb0
\pard\f0\sb120
{\f1 CALL} calls a subroutine, by means of pushing the current instruction 
pointer ({\f1 IP}) and optionally {\f1 CS} as well on the stack, and then 
jumping to a given address.
\par\sb120
{\f1 CS} is pushed as well as {\f1 IP} if and only if the call is a far 
call, i.e. a destination segment address is specified in the instruction. 
The forms involving two colon-separated arguments are far calls; so are the 
{\f1 CALL\'A0FAR\'A0mem} forms.
\par\sb120
The immediate near call takes one of two forms ({\f1 call\'A0imm16/imm32}, 
determined by the current segment size limit. For 16-bit operands, you 
would use {\f1 CALL\'A00x1234}, and for 32-bit operands you would use 
{\f1 CALL\'A00x12345678}. The value passed as an operand is a relative 
offset.
\par\sb120
You can choose between the two immediate far call forms 
({\f1 CALL\'A0imm:imm}) by the use of the {\f1 WORD} and {\f1 DWORD} 
keywords: {\f1 CALL\'A0WORD\'A00x1234:0x5678}) or 
{\f1 CALL\'A0DWORD\'A00x1234:0x56789abc}.
\par\sb120
The {\f1 CALL\'A0FAR\'A0mem} forms execute a far call by loading the 
destination address out of memory. The address loaded consists of 16 or 32 
bits of offset (depending on the operand size), and 16 bits of segment. The 
operand size may be overridden using {\f1 CALL\'A0WORD\'A0FAR\'A0mem} or 
{\f1 CALL\'A0DWORD\'A0FAR\'A0mem}.
\par\sb120
The {\f1 CALL\'A0r/m} forms execute a near call (within the same segment), 
loading the destination address out of memory or out of a register. The 
keyword {\f1 NEAR} may be specified, for clarity, in these forms, but is 
not necessary. Again, operand size can be overridden using 
{\f1 CALL\'A0WORD\'A0mem} or {\f1 CALL\'A0DWORD\'A0mem}.
\par\sb120
As a convenience, NASM does not require you to call a far procedure symbol 
by coding the cumbersome {\f1 CALL\'A0SEG\'A0routine:routine}, but instead 
allows the easier synonym {\f1 CALL\'A0FAR\'A0routine}.
\par\sb120
The {\f1 CALL\'A0r/m} forms given above are near calls; NASM will accept 
the {\f1 NEAR} keyword (e.g. {\f1 CALL\'A0NEAR\'A0[address]}), even though 
it is not strictly necessary.
\par\sb120
\page
#{\footnote section_b_4_19}
${\footnote B.4.19. CBW, CWD, CDQ, CWDE: Sign Extensions}
+{\footnote browse:00239}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CBW;
CDQ;
CWD;
CWDE}
\keepn\f2\b\fs30\sb60\sa60
B.4.19. {\f1 CBW}, {\f1 CWD}, {\f1 CDQ}, {\f1 CWDE}: Sign Extensions
\par\pard\plain\sb120
\keep\f1\sb120
CBW                           ; o16 98               [8086] \par\sb0
CWDE                          ; o32 98               [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CWD                           ; o16 99               [8086] \par\sb0
CDQ                           ; o32 99               [386]\par\sb0
\pard\f0\sb120
All these instructions sign-extend a short value into a longer one, by 
replicating the top bit of the original value to fill the extended one.
\par\sb120
{\f1 CBW} extends {\f1 AL} into {\f1 AX} by repeating the top bit of 
{\f1 AL} in every bit of {\f1 AH}. {\f1 CWDE} extends {\f1 AX} into 
{\f1 EAX}. {\f1 CWD} extends {\f1 AX} into {\f1 DX:AX} by repeating the top 
bit of {\f1 AX} throughout {\f1 DX}, and {\f1 CDQ} extends {\f1 EAX} into 
{\f1 EDX:EAX}.
\par\sb120
\page
#{\footnote section_b_4_20}
${\footnote B.4.20. CLC, CLD, CLI, CLTS: Clear Flags}
+{\footnote browse:00240}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CLC;
CLD;
CLI;
CLTS}
\keepn\f2\b\fs30\sb60\sa60
B.4.20. {\f1 CLC}, {\f1 CLD}, {\f1 CLI}, {\f1 CLTS}: Clear Flags
\par\pard\plain\sb120
\keep\f1\sb120
CLC                           ; F8                   [8086] \par\sb0
CLD                           ; FC                   [8086] \par\sb0
CLI                           ; FA                   [8086] \par\sb0
CLTS                          ; 0F 06                [286,PRIV]\par\sb0
\pard\f0\sb120
These instructions clear various flags. {\f1 CLC} clears the carry flag; 
{\f1 CLD} clears the direction flag; {\f1 CLI} clears the interrupt flag 
(thus disabling interrupts); and {\f1 CLTS} clears the task-switched 
({\f1 TS}) flag in {\f1 CR0}.
\par\sb120
To set the carry, direction, or interrupt flags, use the {\f1 STC}, 
{\f1 STD} and {\f1 STI} instructions ({\uldb section 
B.4.301}{\v section_b_4_301}). To invert the carry flag, use {\f1 CMC} 
({\uldb section B.4.22}{\v section_b_4_22}).
\par\sb120
\page
#{\footnote section_b_4_21}
${\footnote B.4.21. CLFLUSH: Flush Cache Line}
+{\footnote browse:00241}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CLFLUSH}
\keepn\f2\b\fs30\sb60\sa60
B.4.21. {\f1 CLFLUSH}: Flush Cache Line
\par\pard\plain\sb120
\keep\f1\sb120
CLFLUSH mem                   ; 0F AE /7        [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CLFLUSH} invalidates the cache line that contains the linear address 
specified by the source operand from all levels of the processor cache 
hierarchy (data and instruction). If, at any level of the cache hierarchy, 
the line is inconsistent with memory (dirty) it is written to memory before 
invalidation. The source operand points to a byte-sized memory location.
\par\sb120
Although {\f1 CLFLUSH} is flagged {\f1 SSE2} and above, it may not be 
present on all processors which have {\f1 SSE2} support, and it may be 
supported on other processors; the {\f1 CPUID} instruction ({\uldb section 
B.4.34}{\v section_b_4_34}) will return a bit which indicates support for 
the {\f1 CLFLUSH} instruction.
\par\sb120
\page
#{\footnote section_b_4_22}
${\footnote B.4.22. CMC: Complement Carry Flag}
+{\footnote browse:00242}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMC}
\keepn\f2\b\fs30\sb60\sa60
B.4.22. {\f1 CMC}: Complement Carry Flag
\par\pard\plain\sb120
\keep\f1\sb120
CMC                           ; F5                   [8086]\par\sb0
\pard\f0\sb120
{\f1 CMC} changes the value of the carry flag: if it was 0, it sets it to 
1, and vice versa.
\par\sb120
\page
#{\footnote section_b_4_23}
${\footnote B.4.23. CMOVcc: Conditional Move}
+{\footnote browse:00243}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMOVcc}
\keepn\f2\b\fs30\sb60\sa60
B.4.23. {\f1 CMOVcc}: Conditional Move
\par\pard\plain\sb120
\keep\f1\sb120
CMOVcc reg16,r/m16            ; o16 0F 40+cc /r      [P6] \par\sb0
CMOVcc reg32,r/m32            ; o32 0F 40+cc /r      [P6]\par\sb0
\pard\f0\sb120
{\f1 CMOV} moves its source (second) operand into its destination (first) 
operand if the given condition code is satisfied; otherwise it does 
nothing.
\par\sb120
For a list of condition codes, see {\uldb section B.2.2}{\v section_b_2_2}.
\par\sb120
Although the {\f1 CMOV} instructions are flagged {\f1 P6} and above, they 
may not be supported by all Pentium Pro processors; the {\f1 CPUID} 
instruction ({\uldb section B.4.34}{\v section_b_4_34}) will return a bit 
which indicates whether conditional moves are supported.
\par\sb120
\page
#{\footnote section_b_4_24}
${\footnote B.4.24. CMP: Compare Integers}
+{\footnote browse:00244}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMP}
\keepn\f2\b\fs30\sb60\sa60
B.4.24. {\f1 CMP}: Compare Integers
\par\pard\plain\sb120
\keep\f1\sb120
CMP r/m8,reg8                 ; 38 /r                [8086] \par\sb0
CMP r/m16,reg16               ; o16 39 /r            [8086] \par\sb0
CMP r/m32,reg32               ; o32 39 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMP reg8,r/m8                 ; 3A /r                [8086] \par\sb0
CMP reg16,r/m16               ; o16 3B /r            [8086] \par\sb0
CMP reg32,r/m32               ; o32 3B /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMP r/m8,imm8                 ; 80 /0 ib             [8086] \par\sb0
CMP r/m16,imm16               ; o16 81 /0 iw         [8086] \par\sb0
CMP r/m32,imm32               ; o32 81 /0 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMP r/m16,imm8                ; o16 83 /0 ib         [8086] \par\sb0
CMP r/m32,imm8                ; o32 83 /0 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMP AL,imm8                   ; 3C ib                [8086] \par\sb0
CMP AX,imm16                  ; o16 3D iw            [8086] \par\sb0
CMP EAX,imm32                 ; o32 3D id            [386]\par\sb0
\pard\f0\sb120
{\f1 CMP} performs a `mental' subtraction of its second operand from its 
first operand, and affects the flags as if the subtraction had taken place, 
but does not store the result of the subtraction anywhere.
\par\sb120
In the forms with an 8-bit immediate second operand and a longer first 
operand, the second operand is considered to be signed, and is 
sign-extended to the length of the first operand. In these cases, the 
{\f1 BYTE} qualifier is necessary to force NASM to generate this form of 
the instruction.
\par\sb120
The destination operand can be a register or a memory location. The source 
can be a register, memory location or an immediate value of the same size 
as the destination.
\par\sb120
\page
#{\footnote section_b_4_25}
${\footnote B.4.25. CMPccPD: Packed Double-Precision FP Compare        }
+{\footnote browse:00245}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMPccPD;
CMPEQPD;
CMPLEPD;
CMPLTPD;
CMPNEQPD;
CMPNLEPD;
CMPNLTPD;
CMPORDPD;
CMPUNORDPD;
condition predicates}
\keepn\f2\b\fs30\sb60\sa60
B.4.25. {\f1 CMPccPD}: Packed Double-Precision FP Compare        
\par\pard\plain\sb120
\keep\f1\sb120
CMPPD xmm1,xmm2/mem128,imm8   ; 66 0F C2 /r ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMPEQPD xmm1,xmm2/mem128      ; 66 0F C2 /r 00  [WILLAMETTE,SSE2] \par\sb0
CMPLTPD xmm1,xmm2/mem128      ; 66 0F C2 /r 01  [WILLAMETTE,SSE2] \par\sb0
CMPLEPD xmm1,xmm2/mem128      ; 66 0F C2 /r 02  [WILLAMETTE,SSE2] \par\sb0
CMPUNORDPD xmm1,xmm2/mem128   ; 66 0F C2 /r 03  [WILLAMETTE,SSE2] \par\sb0
CMPNEQPD xmm1,xmm2/mem128     ; 66 0F C2 /r 04  [WILLAMETTE,SSE2] \par\sb0
CMPNLTPD xmm1,xmm2/mem128     ; 66 0F C2 /r 05  [WILLAMETTE,SSE2] \par\sb0
CMPNLEPD xmm1,xmm2/mem128     ; 66 0F C2 /r 06  [WILLAMETTE,SSE2] \par\sb0
CMPORDPD xmm1,xmm2/mem128     ; 66 0F C2 /r 07  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
The {\f1 CMPccPD} instructions compare the two packed double-precision FP 
values in the source and destination operands, and returns the result of 
the comparison in the destination register. The result of each comparison 
is a quadword mask of all 1s (comparison true) or all 0s (comparison 
false).
\par\sb120
The destination is an {\f1 XMM} register. The source can be either an 
{\f1 XMM} register or a 128-bit memory location.
\par\sb120
The third operand is an 8-bit immediate value, of which the low 3 bits 
define the type of comparison. For ease of programming, the 8 two-operand 
pseudo-instructions are provided, with the third operand already filled in. 
The  {\f1 Condition\'A0Predicates} are:
\par\sb120
\keep\f1\sb120
EQ     0   Equal \par\sb0
LT     1   Less-than \par\sb0
LE     2   Less-than-or-equal \par\sb0
UNORD  3   Unordered \par\sb0
NE     4   Not-equal \par\sb0
NLT    5   Not-less-than \par\sb0
NLE    6   Not-less-than-or-equal \par\sb0
ORD    7   Ordered\par\sb0
\pard\f0\sb120
For more details of the comparison predicates, and details of how to 
emulate the "greater-than" equivalents, see {\uldb section 
B.2.3}{\v section_b_2_3}
\par\sb120
\page
#{\footnote section_b_4_26}
${\footnote B.4.26. CMPccPS: Packed Single-Precision FP Compare        }
+{\footnote browse:00246}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMPccPS;
CMPEQPS;
CMPLEPS;
CMPLTPS;
CMPNEQPS;
CMPNLEPS;
CMPNLTPS;
CMPORDPS;
CMPUNORDPS;
condition predicates}
\keepn\f2\b\fs30\sb60\sa60
B.4.26. {\f1 CMPccPS}: Packed Single-Precision FP Compare        
\par\pard\plain\sb120
\keep\f1\sb120
CMPPS xmm1,xmm2/mem128,imm8   ; 0F C2 /r ib     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMPEQPS xmm1,xmm2/mem128      ; 0F C2 /r 00     [KATMAI,SSE] \par\sb0
CMPLTPS xmm1,xmm2/mem128      ; 0F C2 /r 01     [KATMAI,SSE] \par\sb0
CMPLEPS xmm1,xmm2/mem128      ; 0F C2 /r 02     [KATMAI,SSE] \par\sb0
CMPUNORDPS xmm1,xmm2/mem128   ; 0F C2 /r 03     [KATMAI,SSE] \par\sb0
CMPNEQPS xmm1,xmm2/mem128     ; 0F C2 /r 04     [KATMAI,SSE] \par\sb0
CMPNLTPS xmm1,xmm2/mem128     ; 0F C2 /r 05     [KATMAI,SSE] \par\sb0
CMPNLEPS xmm1,xmm2/mem128     ; 0F C2 /r 06     [KATMAI,SSE] \par\sb0
CMPORDPS xmm1,xmm2/mem128     ; 0F C2 /r 07     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
The {\f1 CMPccPS} instructions compare the two packed single-precision FP 
values in the source and destination operands, and returns the result of 
the comparison in the destination register. The result of each comparison 
is a doubleword mask of all 1s (comparison true) or all 0s (comparison 
false).
\par\sb120
The destination is an {\f1 XMM} register. The source can be either an 
{\f1 XMM} register or a 128-bit memory location.
\par\sb120
The third operand is an 8-bit immediate value, of which the low 3 bits 
define the type of comparison. For ease of programming, the 8 two-operand 
pseudo-instructions are provided, with the third operand already filled in. 
The  {\f1 Condition\'A0Predicates} are:
\par\sb120
\keep\f1\sb120
EQ     0   Equal \par\sb0
LT     1   Less-than \par\sb0
LE     2   Less-than-or-equal \par\sb0
UNORD  3   Unordered \par\sb0
NE     4   Not-equal \par\sb0
NLT    5   Not-less-than \par\sb0
NLE    6   Not-less-than-or-equal \par\sb0
ORD    7   Ordered\par\sb0
\pard\f0\sb120
For more details of the comparison predicates, and details of how to 
emulate the "greater-than" equivalents, see {\uldb section 
B.2.3}{\v section_b_2_3}
\par\sb120
\page
#{\footnote section_b_4_27}
${\footnote B.4.27. CMPSB, CMPSW, CMPSD: Compare Strings}
+{\footnote browse:00247}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
CMPSB;
CMPSD;
CMPSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.27. {\f1 CMPSB}, {\f1 CMPSW}, {\f1 CMPSD}: Compare Strings
\par\pard\plain\sb120
\keep\f1\sb120
CMPSB                         ; A6                   [8086] \par\sb0
CMPSW                         ; o16 A7               [8086] \par\sb0
CMPSD                         ; o32 A7               [386]\par\sb0
\pard\f0\sb120
{\f1 CMPSB} compares the byte at {\f1 [DS:SI]} or {\f1 [DS:ESI]} with the 
byte at {\f1 [ES:DI]} or {\f1 [ES:EDI]}, and sets the flags accordingly. It 
then increments or decrements (depending on the direction flag: increments 
if the flag is clear, decrements if it is set) {\f1 SI} and {\f1 DI} (or 
{\f1 ESI} and {\f1 EDI}).
\par\sb120
The registers used are {\f1 SI} and {\f1 DI} if the address size is 16 
bits, and {\f1 ESI} and {\f1 EDI} if it is 32 bits. If you need to use an 
address size not equal to the current {\f1 BITS} setting, you can use an 
explicit {\f1 a16} or {\f1 a32} prefix.
\par\sb120
The segment register used to load from {\f1 [SI]} or {\f1 [ESI]} can be 
overridden by using a segment register name as a prefix (for example, 
{\f1 ES\'A0CMPSB}). The use of {\f1 ES} for the load from {\f1 [DI]} or 
{\f1 [EDI]} cannot be overridden.
\par\sb120
{\f1 CMPSW} and {\f1 CMPSD} work in the same way, but they compare a word 
or a doubleword instead of a byte, and increment or decrement the 
addressing registers by 2 or 4 instead of 1.
\par\sb120
The {\f1 REPE} and {\f1 REPNE} prefixes (equivalently, {\f1 REPZ} and 
{\f1 REPNZ}) may be used to repeat the instruction up to {\f1 CX} (or 
{\f1 ECX} \'96 again, the address size chooses which) times until the first 
unequal or equal byte is found.
\par\sb120
\page
#{\footnote section_b_4_28}
${\footnote B.4.28. CMPccSD: Scalar Double-Precision FP Compare        }
+{\footnote browse:00248}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMPccSD;
CMPEQSD;
CMPLESD;
CMPLTSD;
CMPNEQSD;
CMPNLESD;
CMPNLTSD;
CMPORDSD;
CMPUNORDSD;
condition predicates}
\keepn\f2\b\fs30\sb60\sa60
B.4.28. {\f1 CMPccSD}: Scalar Double-Precision FP Compare        
\par\pard\plain\sb120
\keep\f1\sb120
CMPSD xmm1,xmm2/mem64,imm8    ; F2 0F C2 /r ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMPEQSD xmm1,xmm2/mem64       ; F2 0F C2 /r 00  [WILLAMETTE,SSE2] \par\sb0
CMPLTSD xmm1,xmm2/mem64       ; F2 0F C2 /r 01  [WILLAMETTE,SSE2] \par\sb0
CMPLESD xmm1,xmm2/mem64       ; F2 0F C2 /r 02  [WILLAMETTE,SSE2] \par\sb0
CMPUNORDSD xmm1,xmm2/mem64    ; F2 0F C2 /r 03  [WILLAMETTE,SSE2] \par\sb0
CMPNEQSD xmm1,xmm2/mem64      ; F2 0F C2 /r 04  [WILLAMETTE,SSE2] \par\sb0
CMPNLTSD xmm1,xmm2/mem64      ; F2 0F C2 /r 05  [WILLAMETTE,SSE2] \par\sb0
CMPNLESD xmm1,xmm2/mem64      ; F2 0F C2 /r 06  [WILLAMETTE,SSE2] \par\sb0
CMPORDSD xmm1,xmm2/mem64      ; F2 0F C2 /r 07  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
The {\f1 CMPccSD} instructions compare the low-order double-precision FP 
values in the source and destination operands, and returns the result of 
the comparison in the destination register. The result of each comparison 
is a quadword mask of all 1s (comparison true) or all 0s (comparison 
false).
\par\sb120
The destination is an {\f1 XMM} register. The source can be either an 
{\f1 XMM} register or a 128-bit memory location.
\par\sb120
The third operand is an 8-bit immediate value, of which the low 3 bits 
define the type of comparison. For ease of programming, the 8 two-operand 
pseudo-instructions are provided, with the third operand already filled in. 
The  {\f1 Condition\'A0Predicates} are:
\par\sb120
\keep\f1\sb120
EQ     0   Equal \par\sb0
LT     1   Less-than \par\sb0
LE     2   Less-than-or-equal \par\sb0
UNORD  3   Unordered \par\sb0
NE     4   Not-equal \par\sb0
NLT    5   Not-less-than \par\sb0
NLE    6   Not-less-than-or-equal \par\sb0
ORD    7   Ordered\par\sb0
\pard\f0\sb120
For more details of the comparison predicates, and details of how to 
emulate the "greater-than" equivalents, see {\uldb section 
B.2.3}{\v section_b_2_3}
\par\sb120
\page
#{\footnote section_b_4_29}
${\footnote B.4.29. CMPccSS: Scalar Single-Precision FP Compare        }
+{\footnote browse:00249}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMPccSS;
CMPEQSS;
CMPLESS;
CMPLTSS;
CMPNEQSS;
CMPNLESS;
CMPNLTSS;
CMPORDSS;
CMPUNORDSS;
condition predicates}
\keepn\f2\b\fs30\sb60\sa60
B.4.29. {\f1 CMPccSS}: Scalar Single-Precision FP Compare        
\par\pard\plain\sb120
\keep\f1\sb120
CMPSS xmm1,xmm2/mem32,imm8    ; F3 0F C2 /r ib  [KATMAI,SSE]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMPEQSS xmm1,xmm2/mem32       ; F3 0F C2 /r 00  [KATMAI,SSE] \par\sb0
CMPLTSS xmm1,xmm2/mem32       ; F3 0F C2 /r 01  [KATMAI,SSE] \par\sb0
CMPLESS xmm1,xmm2/mem32       ; F3 0F C2 /r 02  [KATMAI,SSE] \par\sb0
CMPUNORDSS xmm1,xmm2/mem32    ; F3 0F C2 /r 03  [KATMAI,SSE] \par\sb0
CMPNEQSS xmm1,xmm2/mem32      ; F3 0F C2 /r 04  [KATMAI,SSE] \par\sb0
CMPNLTSS xmm1,xmm2/mem32      ; F3 0F C2 /r 05  [KATMAI,SSE] \par\sb0
CMPNLESS xmm1,xmm2/mem32      ; F3 0F C2 /r 06  [KATMAI,SSE] \par\sb0
CMPORDSS xmm1,xmm2/mem32      ; F3 0F C2 /r 07  [KATMAI,SSE]\par\sb0
\pard\f0\sb120
The {\f1 CMPccSS} instructions compare the low-order single-precision FP 
values in the source and destination operands, and returns the result of 
the comparison in the destination register. The result of each comparison 
is a doubleword mask of all 1s (comparison true) or all 0s (comparison 
false).
\par\sb120
The destination is an {\f1 XMM} register. The source can be either an 
{\f1 XMM} register or a 128-bit memory location.
\par\sb120
The third operand is an 8-bit immediate value, of which the low 3 bits 
define the type of comparison. For ease of programming, the 8 two-operand 
pseudo-instructions are provided, with the third operand already filled in. 
The  {\f1 Condition\'A0Predicates} are:
\par\sb120
\keep\f1\sb120
EQ     0   Equal \par\sb0
LT     1   Less-than \par\sb0
LE     2   Less-than-or-equal \par\sb0
UNORD  3   Unordered \par\sb0
NE     4   Not-equal \par\sb0
NLT    5   Not-less-than \par\sb0
NLE    6   Not-less-than-or-equal \par\sb0
ORD    7   Ordered\par\sb0
\pard\f0\sb120
For more details of the comparison predicates, and details of how to 
emulate the "greater-than" equivalents, see {\uldb section 
B.2.3}{\v section_b_2_3}
\par\sb120
\page
#{\footnote section_b_4_30}
${\footnote B.4.30. CMPXCHG, CMPXCHG486: Compare and Exchange}
+{\footnote browse:00250}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMPXCHG;
CMPXCHG486}
\keepn\f2\b\fs30\sb60\sa60
B.4.30. {\f1 CMPXCHG}, {\f1 CMPXCHG486}: Compare and Exchange
\par\pard\plain\sb120
\keep\f1\sb120
CMPXCHG r/m8,reg8             ; 0F B0 /r             [PENT] \par\sb0
CMPXCHG r/m16,reg16           ; o16 0F B1 /r         [PENT] \par\sb0
CMPXCHG r/m32,reg32           ; o32 0F B1 /r         [PENT]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
CMPXCHG486 r/m8,reg8          ; 0F A6 /r             [486,UNDOC] \par\sb0
CMPXCHG486 r/m16,reg16        ; o16 0F A7 /r         [486,UNDOC] \par\sb0
CMPXCHG486 r/m32,reg32        ; o32 0F A7 /r         [486,UNDOC]\par\sb0
\pard\f0\sb120
These two instructions perform exactly the same operation; however, 
apparently some (not all) 486 processors support it under a non-standard 
opcode, so NASM provides the undocumented {\f1 CMPXCHG486} form to generate 
the non-standard opcode.
\par\sb120
{\f1 CMPXCHG} compares its destination (first) operand to the value in 
{\f1 AL}, {\f1 AX} or {\f1 EAX} (depending on the operand size of the 
instruction). If they are equal, it copies its source (second) operand into 
the destination and sets the zero flag. Otherwise, it clears the zero flag 
and copies the destination register to AL, AX or EAX.
\par\sb120
The destination can be either a register or a memory location. The source 
is a register.
\par\sb120
{\f1 CMPXCHG} is intended to be used for atomic operations in multitasking 
or multiprocessor environments. To safely update a value in shared memory, 
for example, you might load the value into {\f1 EAX}, load the updated 
value into {\f1 EBX}, and then execute the instruction 
{\f1 LOCK\'A0CMPXCHG\'A0[value],EBX}. If {\f1 value} has not changed since 
being loaded, it is updated with your desired new value, and the zero flag 
is set to let you know it has worked. (The {\f1 LOCK} prefix prevents 
another processor doing anything in the middle of this operation: it 
guarantees atomicity.) However, if another processor has modified the value 
in between your load and your attempted store, the store does not happen, 
and you are notified of the failure by a cleared zero flag, so you can go 
round and try again.
\par\sb120
\page
#{\footnote section_b_4_31}
${\footnote B.4.31. CMPXCHG8B: Compare and Exchange Eight Bytes}
+{\footnote browse:00251}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CMPXCHG8B}
\keepn\f2\b\fs30\sb60\sa60
B.4.31. {\f1 CMPXCHG8B}: Compare and Exchange Eight Bytes
\par\pard\plain\sb120
\keep\f1\sb120
CMPXCHG8B mem                 ; 0F C7 /1             [PENT]\par\sb0
\pard\f0\sb120
This is a larger and more unwieldy version of {\f1 CMPXCHG}: it compares 
the 64-bit (eight-byte) value stored at {\f1 [mem]} with the value in 
{\f1 EDX:EAX}. If they are equal, it sets the zero flag and stores 
{\f1 ECX:EBX} into the memory area. If they are unequal, it clears the zero 
flag and stores the memory contents into {\f1 EDX:EAX}.
\par\sb120
{\f1 CMPXCHG8B} can be used with the {\f1 LOCK} prefix, to allow atomic 
execution. This is useful in multi-processor and multi-tasking 
environments.
\par\sb120
\page
#{\footnote section_b_4_32}
${\footnote B.4.32. COMISD: Scalar Ordered Double-Precision FP Compare and Set EFLAGS}
+{\footnote browse:00252}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote COMISD}
\keepn\f2\b\fs30\sb60\sa60
B.4.32. {\f1 COMISD}: Scalar Ordered Double-Precision FP Compare and Set EFLAGS
\par\pard\plain\sb120
\keep\f1\sb120
COMISD xmm1,xmm2/mem64        ; 66 0F 2F /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 COMISD} compares the low-order double-precision FP value in the two 
source operands. ZF, PF and CF are set according to the result. OF, AF and 
AF are cleared. The unordered result is returned if either source is a NaN 
(QNaN or SNaN).
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a memory location.
\par\sb120
The flags are set according to the following rules:
\par\sb120
\keep\f1\sb120
   Result          Flags        Values\par\sb0
\pard\f0\sb120
\keep\f1\sb120
   UNORDERED:      ZF,PF,CF <-- 111; \par\sb0
   GREATER_THAN:   ZF,PF,CF <-- 000; \par\sb0
   LESS_THAN:      ZF,PF,CF <-- 001; \par\sb0
   EQUAL:          ZF,PF,CF <-- 100;\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_33}
${\footnote B.4.33. COMISS: Scalar Ordered Single-Precision FP Compare and Set EFLAGS}
+{\footnote browse:00253}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote COMISS}
\keepn\f2\b\fs30\sb60\sa60
B.4.33. {\f1 COMISS}: Scalar Ordered Single-Precision FP Compare and Set EFLAGS
\par\pard\plain\sb120
\keep\f1\sb120
COMISS xmm1,xmm2/mem32        ; 66 0F 2F /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 COMISS} compares the low-order single-precision FP value in the two 
source operands. ZF, PF and CF are set according to the result. OF, AF and 
AF are cleared. The unordered result is returned if either source is a NaN 
(QNaN or SNaN).
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a memory location.
\par\sb120
The flags are set according to the following rules:
\par\sb120
\keep\f1\sb120
   Result          Flags        Values\par\sb0
\pard\f0\sb120
\keep\f1\sb120
   UNORDERED:      ZF,PF,CF <-- 111; \par\sb0
   GREATER_THAN:   ZF,PF,CF <-- 000; \par\sb0
   LESS_THAN:      ZF,PF,CF <-- 001; \par\sb0
   EQUAL:          ZF,PF,CF <-- 100;\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_34}
${\footnote B.4.34. CPUID: Get CPU Identification Code}
+{\footnote browse:00254}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CPUID}
\keepn\f2\b\fs30\sb60\sa60
B.4.34. {\f1 CPUID}: Get CPU Identification Code
\par\pard\plain\sb120
\keep\f1\sb120
CPUID                         ; 0F A2                [PENT]\par\sb0
\pard\f0\sb120
{\f1 CPUID} returns various information about the processor it is being 
executed on. It fills the four registers {\f1 EAX}, {\f1 EBX}, {\f1 ECX} 
and {\f1 EDX} with information, which varies depending on the input 
contents of {\f1 EAX}.
\par\sb120
{\f1 CPUID} also acts as a barrier to serialise instruction execution: 
executing the {\f1 CPUID} instruction guarantees that all the effects 
(memory modification, flag modification, register modification) of previous 
instructions have been completed before the next instruction gets fetched.
\par\sb120
The information returned is as follows:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If {\f1 EAX} is zero on input, {\f1 EAX} on output holds the maximum 
acceptable input value of {\f1 EAX}, and {\f1 EBX:EDX:ECX} contain the 
string {\f1 "GenuineIntel"} (or not, if you have a clone processor). That 
is to say, {\f1 EBX} contains {\f1 "Genu"} (in NASM's own sense of 
character constants, described in {\uldb section 3.4.2}{\v section_3_4_2}), 
{\f1 EDX} contains {\f1 "ineI"} and {\f1 ECX} contains {\f1 "ntel"}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If {\f1 EAX} is one on input, {\f1 EAX} on output contains version 
information about the processor, and {\f1 EDX} contains a set of feature 
flags, showing the presence and absence of various features. For example, 
bit 8 is set if the {\f1 CMPXCHG8B} instruction ({\uldb section 
B.4.31}{\v section_b_4_31}) is supported, bit 15 is set if the conditional 
move instructions ({\uldb section B.4.23}{\v section_b_4_23} and 
{\uldb section B.4.72}{\v section_b_4_72}) are supported, and bit 23 is set 
if {\f1 MMX} instructions are supported.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
If {\f1 EAX} is two on input, {\f1 EAX}, {\f1 EBX}, {\f1 ECX} and {\f1 EDX} 
all contain information about caches and TLBs (Translation Lookahead 
Buffers).
\par\pard\sb120
For more information on the data returned from {\f1 CPUID}, see the 
documentation from Intel and other processor manufacturers.
\par\sb120
\page
#{\footnote section_b_4_35}
${\footnote B.4.35. CVTDQ2PD: Packed Signed INT32 to Packed Double-Precision FP Conversion}
+{\footnote browse:00255}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTDQ2PD}
\keepn\f2\b\fs30\sb60\sa60
B.4.35. {\f1 CVTDQ2PD}: Packed Signed INT32 to Packed Double-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTDQ2PD xmm1,xmm2/mem64      ; F3 0F E6 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTDQ2PD} converts two packed signed doublewords from the source 
operand to two packed double-precision FP values in the destination 
operand.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 64-bit memory location. If the source is a 
register, the packed integers are in the low quadword.
\par\sb120
\page
#{\footnote section_b_4_36}
${\footnote B.4.36. CVTDQ2PS: Packed Signed INT32 to Packed Single-Precision FP Conversion}
+{\footnote browse:00256}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTDQ2PS}
\keepn\f2\b\fs30\sb60\sa60
B.4.36. {\f1 CVTDQ2PS}: Packed Signed INT32 to Packed Single-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTDQ2PS xmm1,xmm2/mem128     ; 0F 5B /r        [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTDQ2PS} converts four packed signed doublewords from the source 
operand to four packed single-precision FP values in the destination 
operand.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_37}
${\footnote B.4.37. CVTPD2DQ: Packed Double-Precision FP to Packed Signed INT32 Conversion}
+{\footnote browse:00257}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTPD2DQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.37. {\f1 CVTPD2DQ}: Packed Double-Precision FP to Packed Signed INT32 Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTPD2DQ xmm1,xmm2/mem128     ; F2 0F E6 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTPD2DQ} converts two packed double-precision FP values from the 
source operand to two packed signed doublewords in the low quadword of the 
destination operand. The high quadword of the destination is set to all 0s.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_38}
${\footnote B.4.38. CVTPD2PI: Packed Double-Precision FP to Packed Signed INT32 Conversion}
+{\footnote browse:00258}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTPD2PI}
\keepn\f2\b\fs30\sb60\sa60
B.4.38. {\f1 CVTPD2PI}: Packed Double-Precision FP to Packed Signed INT32 Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTPD2PI mm,xmm/mem128        ; 66 0F 2D /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTPD2PI} converts two packed double-precision FP values from the 
source operand to two packed signed doublewords in the destination operand.
\par\sb120
The destination operand is an {\f1 MMX} register. The source can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_39}
${\footnote B.4.39. CVTPD2PS: Packed Double-Precision FP to Packed Single-Precision FP Conversion}
+{\footnote browse:00259}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTPD2PS}
\keepn\f2\b\fs30\sb60\sa60
B.4.39. {\f1 CVTPD2PS}: Packed Double-Precision FP to Packed Single-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTPD2PS xmm1,xmm2/mem128     ; 66 0F 5A /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTPD2PS} converts two packed double-precision FP values from the 
source operand to two packed single-precision FP values in the low quadword 
of the destination operand. The high quadword of the destination is set to 
all 0s.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_40}
${\footnote B.4.40. CVTPI2PD: Packed Signed INT32 to Packed Double-Precision FP Conversion}
+{\footnote browse:00260}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTPI2PD}
\keepn\f2\b\fs30\sb60\sa60
B.4.40. {\f1 CVTPI2PD}: Packed Signed INT32 to Packed Double-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTPI2PD xmm,mm/mem64         ; 66 0F 2A /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTPI2PD} converts two packed signed doublewords from the source 
operand to two packed double-precision FP values in the destination 
operand.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 MMX} register or a 64-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_41}
${\footnote B.4.41. CVTPI2PS: Packed Signed INT32 to Packed Single-FP Conversion}
+{\footnote browse:00261}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTPI2PS}
\keepn\f2\b\fs30\sb60\sa60
B.4.41. {\f1 CVTPI2PS}: Packed Signed INT32 to Packed Single-FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTPI2PS xmm,mm/mem64         ; 0F 2A /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 CVTPI2PS} converts two packed signed doublewords from the source 
operand to two packed single-precision FP values in the low quadword of the 
destination operand. The high quadword of the destination remains 
unchanged.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 MMX} register or a 64-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_42}
${\footnote B.4.42. CVTPS2DQ: Packed Single-Precision FP to Packed Signed INT32 Conversion}
+{\footnote browse:00262}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTPS2DQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.42. {\f1 CVTPS2DQ}: Packed Single-Precision FP to Packed Signed INT32 Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTPS2DQ xmm1,xmm2/mem128     ; 66 0F 5B /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTPS2DQ} converts four packed single-precision FP values from the 
source operand to four packed signed doublewords in the destination 
operand.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_43}
${\footnote B.4.43. CVTPS2PD: Packed Single-Precision FP to Packed Double-Precision FP Conversion}
+{\footnote browse:00263}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTPS2PD}
\keepn\f2\b\fs30\sb60\sa60
B.4.43. {\f1 CVTPS2PD}: Packed Single-Precision FP to Packed Double-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTPS2PD xmm1,xmm2/mem64      ; 0F 5A /r        [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTPS2PD} converts two packed single-precision FP values from the 
source operand to two packed double-precision FP values in the destination 
operand.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 64-bit memory location. If the source is a 
register, the input values are in the low quadword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_44}
${\footnote B.4.44. CVTPS2PI: Packed Single-Precision FP to Packed Signed INT32 Conversion}
+{\footnote browse:00264}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTPS2PI}
\keepn\f2\b\fs30\sb60\sa60
B.4.44. {\f1 CVTPS2PI}: Packed Single-Precision FP to Packed Signed INT32 Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTPS2PI mm,xmm/mem64         ; 0F 2D /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 CVTPS2PI} converts two packed single-precision FP values from the 
source operand to two packed signed doublewords in the destination operand.
\par\sb120
The destination operand is an {\f1 MMX} register. The source can be either 
an {\f1 XMM} register or a 64-bit memory location. If the source is a 
register, the input values are in the low quadword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_45}
${\footnote B.4.45. CVTSD2SI: Scalar Double-Precision FP to Signed INT32 Conversion}
+{\footnote browse:00265}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTSD2SI}
\keepn\f2\b\fs30\sb60\sa60
B.4.45. {\f1 CVTSD2SI}: Scalar Double-Precision FP to Signed INT32 Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTSD2SI reg32,xmm/mem64      ; F2 0F 2D /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTSD2SI} converts a double-precision FP value from the source operand 
to a signed doubleword in the destination operand.
\par\sb120
The destination operand is a general purpose register. The source can be 
either an {\f1 XMM} register or a 64-bit memory location. If the source is 
a register, the input value is in the low quadword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_46}
${\footnote B.4.46. CVTSD2SS: Scalar Double-Precision FP to Scalar Single-Precision FP Conversion}
+{\footnote browse:00266}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTSD2SS}
\keepn\f2\b\fs30\sb60\sa60
B.4.46. {\f1 CVTSD2SS}: Scalar Double-Precision FP to Scalar Single-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTSD2SS xmm1,xmm2/mem64      ; F2 0F 5A /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 CVTSD2SS} converts a double-precision FP value from the source operand 
to a single-precision FP value in the low doubleword of the destination 
operand. The upper 3 doublewords are left unchanged.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 64-bit memory location. If the source is a 
register, the input value is in the low quadword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_47}
${\footnote B.4.47. CVTSI2SD: Signed INT32 to Scalar Double-Precision FP Conversion}
+{\footnote browse:00267}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTSI2SD}
\keepn\f2\b\fs30\sb60\sa60
B.4.47. {\f1 CVTSI2SD}: Signed INT32 to Scalar Double-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTSI2SD xmm,r/m32            ; F2 0F 2A /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTSI2SD} converts a signed doubleword from the source operand to a 
double-precision FP value in the low quadword of the destination operand. 
The high quadword is left unchanged.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
a general purpose register or a 32-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_48}
${\footnote B.4.48. CVTSI2SS: Signed INT32 to Scalar Single-Precision FP Conversion}
+{\footnote browse:00268}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTSI2SS}
\keepn\f2\b\fs30\sb60\sa60
B.4.48. {\f1 CVTSI2SS}: Signed INT32 to Scalar Single-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTSI2SS xmm,r/m32            ; F3 0F 2A /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 CVTSI2SS} converts a signed doubleword from the source operand to a 
single-precision FP value in the low doubleword of the destination operand. 
The upper 3 doublewords are left unchanged.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
a general purpose register or a 32-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_49}
${\footnote B.4.49. CVTSS2SD: Scalar Single-Precision FP to Scalar Double-Precision FP Conversion}
+{\footnote browse:00269}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTSS2SD}
\keepn\f2\b\fs30\sb60\sa60
B.4.49. {\f1 CVTSS2SD}: Scalar Single-Precision FP to Scalar Double-Precision FP Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTSS2SD xmm1,xmm2/mem32      ; F3 0F 5A /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTSS2SD} converts a single-precision FP value from the source operand 
to a double-precision FP value in the low quadword of the destination 
operand. The upper quadword is left unchanged.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 32-bit memory location. If the source is a 
register, the input value is contained in the low doubleword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_50}
${\footnote B.4.50. CVTSS2SI: Scalar Single-Precision FP to Signed INT32 Conversion}
+{\footnote browse:00270}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTSS2SI}
\keepn\f2\b\fs30\sb60\sa60
B.4.50. {\f1 CVTSS2SI}: Scalar Single-Precision FP to Signed INT32 Conversion
\par\pard\plain\sb120
\keep\f1\sb120
CVTSS2SI reg32,xmm/mem32      ; F3 0F 2D /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 CVTSS2SI} converts a single-precision FP value from the source operand 
to a signed doubleword in the destination operand.
\par\sb120
The destination operand is a general purpose register. The source can be 
either an {\f1 XMM} register or a 32-bit memory location. If the source is 
a register, the input value is in the low doubleword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_51}
${\footnote B.4.51. CVTTPD2DQ: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation}
+{\footnote browse:00271}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTTPD2DQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.51. {\f1 CVTTPD2DQ}: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
\par\pard\plain\sb120
\keep\f1\sb120
CVTTPD2DQ xmm1,xmm2/mem128    ; 66 0F E6 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTTPD2DQ} converts two packed double-precision FP values in the 
source operand to two packed single-precision FP values in the destination 
operand. If the result is inexact, it is truncated (rounded toward zero). 
The high quadword is set to all 0s.
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_52}
${\footnote B.4.52. CVTTPD2PI: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation}
+{\footnote browse:00272}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTTPD2PI}
\keepn\f2\b\fs30\sb60\sa60
B.4.52. {\f1 CVTTPD2PI}: Packed Double-Precision FP to Packed Signed INT32 Conversion with Truncation
\par\pard\plain\sb120
\keep\f1\sb120
CVTTPD2PI mm,xmm/mem128        ; 66 0F 2C /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTTPD2PI} converts two packed double-precision FP values in the 
source operand to two packed single-precision FP values in the destination 
operand. If the result is inexact, it is truncated (rounded toward zero).
\par\sb120
The destination operand is an {\f1 MMX} register. The source can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_53}
${\footnote B.4.53. CVTTPS2DQ: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation}
+{\footnote browse:00273}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTTPS2DQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.53. {\f1 CVTTPS2DQ}: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
\par\pard\plain\sb120
\keep\f1\sb120
CVTTPS2DQ xmm1,xmm2/mem128    ; F3 0F 5B /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTTPS2DQ} converts four packed single-precision FP values in the 
source operand to four packed signed doublewords in the destination 
operand. If the result is inexact, it is truncated (rounded toward zero).
\par\sb120
The destination operand is an {\f1 XMM} register. The source can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_54}
${\footnote B.4.54. CVTTPS2PI: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation}
+{\footnote browse:00274}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTTPS2PI}
\keepn\f2\b\fs30\sb60\sa60
B.4.54. {\f1 CVTTPS2PI}: Packed Single-Precision FP to Packed Signed INT32 Conversion with Truncation
\par\pard\plain\sb120
\keep\f1\sb120
CVTTPS2PI mm,xmm/mem64         ; 0F 2C /r       [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 CVTTPS2PI} converts two packed single-precision FP values in the 
source operand to two packed signed doublewords in the destination operand. 
If the result is inexact, it is truncated (rounded toward zero). If the 
source is a register, the input values are in the low quadword.
\par\sb120
The destination operand is an {\f1 MMX} register. The source can be either 
an {\f1 XMM} register or a 64-bit memory location. If the source is a 
register, the input value is in the low quadword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_55}
${\footnote B.4.55. CVTTSD2SI: Scalar Double-Precision FP to Signed INT32 Conversion with Truncation}
+{\footnote browse:00275}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTTSD2SI}
\keepn\f2\b\fs30\sb60\sa60
B.4.55. {\f1 CVTTSD2SI}: Scalar Double-Precision FP to Signed INT32 Conversion with Truncation
\par\pard\plain\sb120
\keep\f1\sb120
CVTTSD2SI reg32,xmm/mem64      ; F2 0F 2C /r    [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 CVTTSD2SI} converts a double-precision FP value in the source operand 
to a signed doubleword in the destination operand. If the result is 
inexact, it is truncated (rounded toward zero).
\par\sb120
The destination operand is a general purpose register. The source can be 
either an {\f1 XMM} register or a 64-bit memory location. If the source is 
a register, the input value is in the low quadword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_56}
${\footnote B.4.56. CVTTSS2SI: Scalar Single-Precision FP to Signed INT32 Conversion with Truncation}
+{\footnote browse:00276}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote CVTTSS2SI}
\keepn\f2\b\fs30\sb60\sa60
B.4.56. {\f1 CVTTSS2SI}: Scalar Single-Precision FP to Signed INT32 Conversion with Truncation
\par\pard\plain\sb120
\keep\f1\sb120
CVTTSD2SI reg32,xmm/mem32      ; F3 0F 2C /r    [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 CVTTSS2SI} converts a single-precision FP value in the source operand 
to a signed doubleword in the destination operand. If the result is 
inexact, it is truncated (rounded toward zero).
\par\sb120
The destination operand is a general purpose register. The source can be 
either an {\f1 XMM} register or a 32-bit memory location. If the source is 
a register, the input value is in the low doubleword.
\par\sb120
For more details of this instruction, see the Intel Processor manuals.
\par\sb120
\page
#{\footnote section_b_4_57}
${\footnote B.4.57. DAA, DAS: Decimal Adjustments}
+{\footnote browse:00277}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote DAA;
DAS}
\keepn\f2\b\fs30\sb60\sa60
B.4.57. {\f1 DAA}, {\f1 DAS}: Decimal Adjustments
\par\pard\plain\sb120
\keep\f1\sb120
DAA                           ; 27                   [8086] \par\sb0
DAS                           ; 2F                   [8086]\par\sb0
\pard\f0\sb120
These instructions are used in conjunction with the add and subtract 
instructions to perform binary-coded decimal arithmetic in {\i packed} (one 
BCD digit per nibble) form. For the unpacked equivalents, see 
{\uldb section B.4.1}{\v section_b_4_1}.
\par\sb120
{\f1 DAA} should be used after a one-byte {\f1 ADD} instruction whose 
destination was the {\f1 AL} register: by means of examining the value in 
the {\f1 AL} and also the auxiliary carry flag {\f1 AF}, it determines 
whether either digit of the addition has overflowed, and adjusts it (and 
sets the carry and auxiliary-carry flags) if so. You can add long BCD 
strings together by doing {\f1 ADD}/{\f1 DAA} on the low two digits, then 
doing {\f1 ADC}/{\f1 DAA} on each subsequent pair of digits.
\par\sb120
{\f1 DAS} works similarly to {\f1 DAA}, but is for use after {\f1 SUB} 
instructions rather than {\f1 ADD}.
\par\sb120
\page
#{\footnote section_b_4_58}
${\footnote B.4.58. DEC: Decrement Integer}
+{\footnote browse:00278}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote DEC}
\keepn\f2\b\fs30\sb60\sa60
B.4.58. {\f1 DEC}: Decrement Integer
\par\pard\plain\sb120
\keep\f1\sb120
DEC reg16                     ; o16 48+r             [8086] \par\sb0
DEC reg32                     ; o32 48+r             [386] \par\sb0
DEC r/m8                      ; FE /1                [8086] \par\sb0
DEC r/m16                     ; o16 FF /1            [8086] \par\sb0
DEC r/m32                     ; o32 FF /1            [386]\par\sb0
\pard\f0\sb120
{\f1 DEC} subtracts 1 from its operand. It does {\i not} affect the carry 
flag: to affect the carry flag, use {\f1 SUB\'A0something,1} (see 
{\uldb section B.4.305}{\v section_b_4_305}). {\f1 DEC} affects all the 
other flags according to the result.
\par\sb120
This instruction can be used with a {\f1 LOCK} prefix to allow atomic 
execution.
\par\sb120
See also {\f1 INC} ({\uldb section B.4.120}{\v section_b_4_120}).
\par\sb120
\page
#{\footnote section_b_4_59}
${\footnote B.4.59. DIV: Unsigned Integer Divide}
+{\footnote browse:00279}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote DIV}
\keepn\f2\b\fs30\sb60\sa60
B.4.59. {\f1 DIV}: Unsigned Integer Divide
\par\pard\plain\sb120
\keep\f1\sb120
DIV r/m8                      ; F6 /6                [8086] \par\sb0
DIV r/m16                     ; o16 F7 /6            [8086] \par\sb0
DIV r/m32                     ; o32 F7 /6            [386]\par\sb0
\pard\f0\sb120
{\f1 DIV} performs unsigned integer division. The explicit operand provided 
is the divisor; the dividend and destination operands are implicit, in the 
following way:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 DIV\'A0r/m8}, {\f1 AX} is divided by the given operand; the 
quotient is stored in {\f1 AL} and the remainder in {\f1 AH}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 DIV\'A0r/m16}, {\f1 DX:AX} is divided by the given operand; the 
quotient is stored in {\f1 AX} and the remainder in {\f1 DX}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 DIV\'A0r/m32}, {\f1 EDX:EAX} is divided by the given operand; the 
quotient is stored in {\f1 EAX} and the remainder in {\f1 EDX}.
\par\pard\sb120
Signed integer division is performed by the {\f1 IDIV} instruction: see 
{\uldb section B.4.117}{\v section_b_4_117}.
\par\sb120
\page
#{\footnote section_b_4_60}
${\footnote B.4.60. DIVPD: Packed Double-Precision FP Divide}
+{\footnote browse:00280}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote DIVPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.60. {\f1 DIVPD}: Packed Double-Precision FP Divide
\par\pard\plain\sb120
\keep\f1\sb120
DIVPD xmm1,xmm2/mem128        ; 66 0F 5E /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 DIVPD} divides the two packed double-precision FP values in the 
destination operand by the two packed double-precision FP values in the 
source operand, and stores the packed double-precision results in the 
destination register.
\par\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
\keep\f1\sb120
   dst[0-63]   := dst[0-63]   / src[0-63], \par\sb0
   dst[64-127] := dst[64-127] / src[64-127].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_61}
${\footnote B.4.61. DIVPS: Packed Single-Precision FP Divide}
+{\footnote browse:00281}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote DIVPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.61. {\f1 DIVPS}: Packed Single-Precision FP Divide
\par\pard\plain\sb120
\keep\f1\sb120
DIVPS xmm1,xmm2/mem128        ; 0F 5E /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 DIVPS} divides the four packed single-precision FP values in the 
destination operand by the four packed single-precision FP values in the 
source operand, and stores the packed single-precision results in the 
destination register.
\par\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 128-bit memory location.
\par\sb120
\keep\f1\sb120
   dst[0-31]   := dst[0-31]   / src[0-31], \par\sb0
   dst[32-63]  := dst[32-63]  / src[32-63], \par\sb0
   dst[64-95]  := dst[64-95]  / src[64-95], \par\sb0
   dst[96-127] := dst[96-127] / src[96-127].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_62}
${\footnote B.4.62. DIVSD: Scalar Double-Precision FP Divide}
+{\footnote browse:00282}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote DIVSD}
\keepn\f2\b\fs30\sb60\sa60
B.4.62. {\f1 DIVSD}: Scalar Double-Precision FP Divide
\par\pard\plain\sb120
\keep\f1\sb120
DIVSD xmm1,xmm2/mem64         ; F2 0F 5E /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 DIVSD} divides the low-order double-precision FP value in the 
destination operand by the low-order double-precision FP value in the 
source operand, and stores the double-precision result in the destination 
register.
\par\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 64-bit memory location.
\par\sb120
\keep\f1\sb120
   dst[0-63]   := dst[0-63] / src[0-63], \par\sb0
   dst[64-127] remains unchanged.\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_63}
${\footnote B.4.63. DIVSS: Scalar Single-Precision FP Divide}
+{\footnote browse:00283}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote DIVSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.63. {\f1 DIVSS}: Scalar Single-Precision FP Divide
\par\pard\plain\sb120
\keep\f1\sb120
DIVSS xmm1,xmm2/mem32         ; F3 0F 5E /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 DIVSS} divides the low-order single-precision FP value in the 
destination operand by the low-order single-precision FP value in the 
source operand, and stores the single-precision result in the destination 
register.
\par\sb120
The destination is an {\f1 XMM} register. The source operand can be either 
an {\f1 XMM} register or a 32-bit memory location.
\par\sb120
\keep\f1\sb120
   dst[0-31]   := dst[0-31] / src[0-31], \par\sb0
   dst[32-127] remains unchanged.\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_64}
${\footnote B.4.64. EMMS: Empty MMX State}
+{\footnote browse:00284}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote EMMS}
\keepn\f2\b\fs30\sb60\sa60
B.4.64. {\f1 EMMS}: Empty MMX State
\par\pard\plain\sb120
\keep\f1\sb120
EMMS                          ; 0F 77                [PENT,MMX]\par\sb0
\pard\f0\sb120
{\f1 EMMS} sets the FPU tag word (marking which floating-point registers 
are available) to all ones, meaning all registers are available for the FPU 
to use. It should be used after executing {\f1 MMX} instructions and before 
executing any subsequent floating-point operations.
\par\sb120
\page
#{\footnote section_b_4_65}
${\footnote B.4.65. ENTER: Create Stack Frame}
+{\footnote browse:00285}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ENTER;
stack\'A0frame}
\keepn\f2\b\fs30\sb60\sa60
B.4.65. {\f1 ENTER}: Create Stack Frame
\par\pard\plain\sb120
\keep\f1\sb120
ENTER imm,imm                 ; C8 iw ib             [186]\par\sb0
\pard\f0\sb120
{\f1 ENTER} constructs a {\f1 stack\'A0frame} for a high-level language 
procedure call. The first operand (the {\f1 iw} in the opcode definition 
above refers to the first operand) gives the amount of stack space to 
allocate for local variables; the second (the {\f1 ib} above) gives the 
nesting level of the procedure (for languages like Pascal, with nested 
procedures).
\par\sb120
The function of {\f1 ENTER}, with a nesting level of zero, is equivalent to
\par\sb120
\keep\f1\sb120
          PUSH EBP            ; or PUSH BP         in 16 bits \par\sb0
          MOV EBP,ESP         ; or MOV BP,SP       in 16 bits \par\sb0
          SUB ESP,operand1    ; or SUB SP,operand1 in 16 bits\par\sb0
\pard\f0\sb120
This creates a stack frame with the procedure parameters accessible upwards 
from {\f1 EBP}, and local variables accessible downwards from {\f1 EBP}.
\par\sb120
With a nesting level of one, the stack frame created is 4 (or 2) bytes 
bigger, and the value of the final frame pointer {\f1 EBP} is accessible in 
memory at {\f1 [EBP\'AD4]}.
\par\sb120
This allows {\f1 ENTER}, when called with a nesting level of two, to look 
at the stack frame described by the {\i previous} value of {\f1 EBP}, find 
the frame pointer at offset \'964 from that, and push it along with its new 
frame pointer, so that when a level-two procedure is called from within a 
level-one procedure, {\f1 [EBP\'AD4]} holds the frame pointer of the most 
recent level-one procedure call and {\f1 [EBP\'AD8]} holds that of the most 
recent level-two call. And so on, for nesting levels up to 31.
\par\sb120
Stack frames created by {\f1 ENTER} can be destroyed by the {\f1 LEAVE} 
instruction: see {\uldb section B.4.136}{\v section_b_4_136}.
\par\sb120
\page
#{\footnote section_b_4_66}
${\footnote B.4.66. F2XM1: Calculate 2**X-1}
+{\footnote browse:00286}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote F2XM1}
\keepn\f2\b\fs30\sb60\sa60
B.4.66. {\f1 F2XM1}: Calculate 2**X-1
\par\pard\plain\sb120
\keep\f1\sb120
F2XM1                         ; D9 F0                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 F2XM1} raises 2 to the power of {\f1 ST0}, subtracts one, and stores 
the result back into {\f1 ST0}. The initial contents of {\f1 ST0} must be a 
number in the range \'961.0 to +1.0.
\par\sb120
\page
#{\footnote section_b_4_67}
${\footnote B.4.67. FABS: Floating-Point Absolute Value}
+{\footnote browse:00287}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FABS}
\keepn\f2\b\fs30\sb60\sa60
B.4.67. {\f1 FABS}: Floating-Point Absolute Value
\par\pard\plain\sb120
\keep\f1\sb120
FABS                          ; D9 E1                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FABS} computes the absolute value of {\f1 ST0},by clearing the sign 
bit, and stores the result back in {\f1 ST0}.
\par\sb120
\page
#{\footnote section_b_4_68}
${\footnote B.4.68. FADD, FADDP: Floating-Point Addition}
+{\footnote browse:00288}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FADD;
FADDP}
\keepn\f2\b\fs30\sb60\sa60
B.4.68. {\f1 FADD}, {\f1 FADDP}: Floating-Point Addition
\par\pard\plain\sb120
\keep\f1\sb120
FADD mem32                    ; D8 /0                [8086,FPU] \par\sb0
FADD mem64                    ; DC /0                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FADD fpureg                   ; D8 C0+r              [8086,FPU] \par\sb0
FADD ST0,fpureg               ; D8 C0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FADD TO fpureg                ; DC C0+r              [8086,FPU] \par\sb0
FADD fpureg,ST0               ; DC C0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FADDP fpureg                  ; DE C0+r              [8086,FPU] \par\sb0
FADDP fpureg,ST0              ; DE C0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FADD}, given one operand, adds the operand to {\f1 ST0} and stores the 
result back in {\f1 ST0}. If the operand has the {\f1 TO} modifier, the 
result is stored in the register given rather than in {\f1 ST0}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FADDP} performs the same function as {\f1 FADD\'A0TO}, but pops the 
register stack after storing the result.
\par\pard\sb120
The given two-operand forms are synonyms for the one-operand forms.
\par\sb120
To add an integer value to {\f1 ST0}, use the c\{FIADD\} instruction 
({\uldb section B.4.80}{\v section_b_4_80})
\par\sb120
\page
#{\footnote section_b_4_69}
${\footnote B.4.69. FBLD, FBSTP: BCD Floating-Point Load and Store}
+{\footnote browse:00289}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FBLD;
FBSTP}
\keepn\f2\b\fs30\sb60\sa60
B.4.69. {\f1 FBLD}, {\f1 FBSTP}: BCD Floating-Point Load and Store
\par\pard\plain\sb120
\keep\f1\sb120
FBLD mem80                    ; DF /4                [8086,FPU] \par\sb0
FBSTP mem80                   ; DF /6                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FBLD} loads an 80-bit (ten-byte) packed binary-coded decimal number 
from the given memory address, converts it to a real, and pushes it on the 
register stack. {\f1 FBSTP} stores the value of {\f1 ST0}, in packed BCD, 
at the given address and then pops the register stack.
\par\sb120
\page
#{\footnote section_b_4_70}
${\footnote B.4.70. FCHS: Floating-Point Change Sign}
+{\footnote browse:00290}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FCHS}
\keepn\f2\b\fs30\sb60\sa60
B.4.70. {\f1 FCHS}: Floating-Point Change Sign
\par\pard\plain\sb120
\keep\f1\sb120
FCHS                          ; D9 E0                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FCHS} negates the number in {\f1 ST0}, by inverting the sign bit: 
negative numbers become positive, and vice versa.
\par\sb120
\page
#{\footnote section_b_4_71}
${\footnote B.4.71. FCLEX, FNCLEX: Clear Floating-Point Exceptions}
+{\footnote browse:00291}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FCLEX}
\keepn\f2\b\fs30\sb60\sa60
B.4.71. {\f1 FCLEX}, {\f1 FNCLEX}: Clear Floating-Point Exceptions
\par\pard\plain\sb120
\keep\f1\sb120
FCLEX                         ; 9B DB E2             [8086,FPU] \par\sb0
FNCLEX                        ; DB E2                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FCLEX} clears any floating-point exceptions which may be pending. 
{\f1 FNCLEX} does the same thing but doesn't wait for previous 
floating-point operations (including the {\i handling} of pending 
exceptions) to finish first.
\par\sb120
\page
#{\footnote section_b_4_72}
${\footnote B.4.72. FCMOVcc: Floating-Point Conditional Move}
+{\footnote browse:00292}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FCMOVcc}
\keepn\f2\b\fs30\sb60\sa60
B.4.72. {\f1 FCMOVcc}: Floating-Point Conditional Move
\par\pard\plain\sb120
\keep\f1\sb120
FCMOVB fpureg                 ; DA C0+r              [P6,FPU] \par\sb0
FCMOVB ST0,fpureg             ; DA C0+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCMOVE fpureg                 ; DA C8+r              [P6,FPU] \par\sb0
FCMOVE ST0,fpureg             ; DA C8+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCMOVBE fpureg                ; DA D0+r              [P6,FPU] \par\sb0
FCMOVBE ST0,fpureg            ; DA D0+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCMOVU fpureg                 ; DA D8+r              [P6,FPU] \par\sb0
FCMOVU ST0,fpureg             ; DA D8+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCMOVNB fpureg                ; DB C0+r              [P6,FPU] \par\sb0
FCMOVNB ST0,fpureg            ; DB C0+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCMOVNE fpureg                ; DB C8+r              [P6,FPU] \par\sb0
FCMOVNE ST0,fpureg            ; DB C8+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCMOVNBE fpureg               ; DB D0+r              [P6,FPU] \par\sb0
FCMOVNBE ST0,fpureg           ; DB D0+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCMOVNU fpureg                ; DB D8+r              [P6,FPU] \par\sb0
FCMOVNU ST0,fpureg            ; DB D8+r              [P6,FPU]\par\sb0
\pard\f0\sb120
The {\f1 FCMOV} instructions perform conditional move operations: each of 
them moves the contents of the given register into {\f1 ST0} if its 
condition is satisfied, and does nothing if not.
\par\sb120
The conditions are not the same as the standard condition codes used with 
conditional jump instructions. The conditions {\f1 B}, {\f1 BE}, {\f1 NB}, 
{\f1 NBE}, {\f1 E} and {\f1 NE} are exactly as normal, but none of the 
other standard ones are supported. Instead, the condition {\f1 U} and its 
counterpart {\f1 NU} are provided; the {\f1 U} condition is satisfied if 
the last two floating-point numbers compared were {\i unordered}, i.e. they 
were not equal but neither one could be said to be greater than the other, 
for example if they were NaNs. (The flag state which signals this is the 
setting of the parity flag: so the {\f1 U} condition is notionally 
equivalent to {\f1 PE}, and {\f1 NU} is equivalent to {\f1 PO}.)
\par\sb120
The {\f1 FCMOV} conditions test the main processor's status flags, not the 
FPU status flags, so using {\f1 FCMOV} directly after {\f1 FCOM} will not 
work. Instead, you should either use {\f1 FCOMI} which writes directly to 
the main CPU flags word, or use {\f1 FSTSW} to extract the FPU flags.
\par\sb120
Although the {\f1 FCMOV} instructions are flagged {\f1 P6} above, they may 
not be supported by all Pentium Pro processors; the {\f1 CPUID} instruction 
({\uldb section B.4.34}{\v section_b_4_34}) will return a bit which 
indicates whether conditional moves are supported.
\par\sb120
\page
#{\footnote section_b_4_73}
${\footnote B.4.73. FCOM, FCOMP, FCOMPP, FCOMI, FCOMIP: Floating-Point Compare}
+{\footnote browse:00293}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FCOM;
FCOMI;
FCOMIP;
FCOMP;
FCOMPP}
\keepn\f2\b\fs30\sb60\sa60
B.4.73. {\f1 FCOM}, {\f1 FCOMP}, {\f1 FCOMPP}, {\f1 FCOMI}, {\f1 FCOMIP}: Floating-Point Compare
\par\pard\plain\sb120
\keep\f1\sb120
FCOM mem32                    ; D8 /2                [8086,FPU] \par\sb0
FCOM mem64                    ; DC /2                [8086,FPU] \par\sb0
FCOM fpureg                   ; D8 D0+r              [8086,FPU] \par\sb0
FCOM ST0,fpureg               ; D8 D0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCOMP mem32                   ; D8 /3                [8086,FPU] \par\sb0
FCOMP mem64                   ; DC /3                [8086,FPU] \par\sb0
FCOMP fpureg                  ; D8 D8+r              [8086,FPU] \par\sb0
FCOMP ST0,fpureg              ; D8 D8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCOMPP                        ; DE D9                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCOMI fpureg                  ; DB F0+r              [P6,FPU] \par\sb0
FCOMI ST0,fpureg              ; DB F0+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FCOMIP fpureg                 ; DF F0+r              [P6,FPU] \par\sb0
FCOMIP ST0,fpureg             ; DF F0+r              [P6,FPU]\par\sb0
\pard\f0\sb120
{\f1 FCOM} compares {\f1 ST0} with the given operand, and sets the FPU 
flags accordingly. {\f1 ST0} is treated as the left-hand side of the 
comparison, so that the carry flag is set (for a `less-than' result) if 
{\f1 ST0} is less than the given operand.
\par\sb120
{\f1 FCOMP} does the same as {\f1 FCOM}, but pops the register stack 
afterwards. {\f1 FCOMPP} compares {\f1 ST0} with {\f1 ST1} and then pops 
the register stack twice.
\par\sb120
{\f1 FCOMI} and {\f1 FCOMIP} work like the corresponding forms of 
{\f1 FCOM} and {\f1 FCOMP}, but write their results directly to the CPU 
flags register rather than the FPU status word, so they can be immediately 
followed by conditional jump or conditional move instructions.
\par\sb120
The {\f1 FCOM} instructions differ from the {\f1 FUCOM} instructions 
({\uldb section B.4.108}{\v section_b_4_108}) only in the way they handle 
quiet NaNs: {\f1 FUCOM} will handle them silently and set the condition 
code flags to an `unordered' result, whereas {\f1 FCOM} will generate an 
exception.
\par\sb120
\page
#{\footnote section_b_4_74}
${\footnote B.4.74. FCOS: Cosine}
+{\footnote browse:00294}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FCOS}
\keepn\f2\b\fs30\sb60\sa60
B.4.74. {\f1 FCOS}: Cosine
\par\pard\plain\sb120
\keep\f1\sb120
FCOS                          ; D9 FF                [386,FPU]\par\sb0
\pard\f0\sb120
{\f1 FCOS} computes the cosine of {\f1 ST0} (in radians), and stores the 
result in {\f1 ST0}. The absolute value of {\f1 ST0} must be less than 
2**63.
\par\sb120
See also {\f1 FSINCOS} ({\uldb section B.4.100}{\v section_b_4_100}).
\par\sb120
\page
#{\footnote section_b_4_75}
${\footnote B.4.75. FDECSTP: Decrement Floating-Point Stack Pointer}
+{\footnote browse:00295}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FDECSTP}
\keepn\f2\b\fs30\sb60\sa60
B.4.75. {\f1 FDECSTP}: Decrement Floating-Point Stack Pointer
\par\pard\plain\sb120
\keep\f1\sb120
FDECSTP                       ; D9 F6                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FDECSTP} decrements the `top' field in the floating-point status word. 
This has the effect of rotating the FPU register stack by one, as if the 
contents of {\f1 ST7} had been pushed on the stack. See also {\f1 FINCSTP} 
({\uldb section B.4.85}{\v section_b_4_85}).
\par\sb120
\page
#{\footnote section_b_4_76}
${\footnote B.4.76. FxDISI, FxENI: Disable and Enable Floating-Point Interrupts}
+{\footnote browse:00296}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FxDISI;
FxENI}
\keepn\f2\b\fs30\sb60\sa60
B.4.76. {\f1 FxDISI}, {\f1 FxENI}: Disable and Enable Floating-Point Interrupts
\par\pard\plain\sb120
\keep\f1\sb120
FDISI                         ; 9B DB E1             [8086,FPU] \par\sb0
FNDISI                        ; DB E1                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FENI                          ; 9B DB E0             [8086,FPU] \par\sb0
FNENI                         ; DB E0                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FDISI} and {\f1 FENI} disable and enable floating-point interrupts. 
These instructions are only meaningful on original 8087 processors: the 287 
and above treat them as no-operation instructions.
\par\sb120
{\f1 FNDISI} and {\f1 FNENI} do the same thing as {\f1 FDISI} and 
{\f1 FENI} respectively, but without waiting for the floating-point 
processor to finish what it was doing first.
\par\sb120
\page
#{\footnote section_b_4_77}
${\footnote B.4.77. FDIV, FDIVP, FDIVR, FDIVRP: Floating-Point Division}
+{\footnote browse:00297}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FDIV;
FDIVP;
FDIVR;
FDIVRP}
\keepn\f2\b\fs30\sb60\sa60
B.4.77. {\f1 FDIV}, {\f1 FDIVP}, {\f1 FDIVR}, {\f1 FDIVRP}: Floating-Point Division
\par\pard\plain\sb120
\keep\f1\sb120
FDIV mem32                    ; D8 /6                [8086,FPU] \par\sb0
FDIV mem64                    ; DC /6                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FDIV fpureg                   ; D8 F0+r              [8086,FPU] \par\sb0
FDIV ST0,fpureg               ; D8 F0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FDIV TO fpureg                ; DC F8+r              [8086,FPU] \par\sb0
FDIV fpureg,ST0               ; DC F8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FDIVR mem32                   ; D8 /0                [8086,FPU] \par\sb0
FDIVR mem64                   ; DC /0                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FDIVR fpureg                  ; D8 F8+r              [8086,FPU] \par\sb0
FDIVR ST0,fpureg              ; D8 F8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FDIVR TO fpureg               ; DC F0+r              [8086,FPU] \par\sb0
FDIVR fpureg,ST0              ; DC F0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FDIVP fpureg                  ; DE F8+r              [8086,FPU] \par\sb0
FDIVP fpureg,ST0              ; DE F8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FDIVRP fpureg                 ; DE F0+r              [8086,FPU] \par\sb0
FDIVRP fpureg,ST0             ; DE F0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FDIV} divides {\f1 ST0} by the given operand and stores the result 
back in {\f1 ST0}, unless the {\f1 TO} qualifier is given, in which case it 
divides the given operand by {\f1 ST0} and stores the result in the 
operand.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FDIVR} does the same thing, but does the division the other way up: so 
if {\f1 TO} is not given, it divides the given operand by {\f1 ST0} and 
stores the result in {\f1 ST0}, whereas if {\f1 TO} is given it divides 
{\f1 ST0} by its operand and stores the result in the operand.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FDIVP} operates like {\f1 FDIV\'A0TO}, but pops the register stack 
once it has finished.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FDIVRP} operates like {\f1 FDIVR\'A0TO}, but pops the register stack 
once it has finished.
\par\pard\sb120
For FP/Integer divisions, see {\f1 FIDIV} ({\uldb section 
B.4.82}{\v section_b_4_82}).
\par\sb120
\page
#{\footnote section_b_4_78}
${\footnote B.4.78. FEMMS: Faster Enter/Exit of the MMX or floating-point state}
+{\footnote browse:00298}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FEMMS}
\keepn\f2\b\fs30\sb60\sa60
B.4.78. {\f1 FEMMS}: Faster Enter/Exit of the MMX or floating-point state
\par\pard\plain\sb120
\keep\f1\sb120
FEMMS                         ; 0F 0E           [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 FEMMS} can be used in place of the {\f1 EMMS} instruction on 
processors which support the 3DNow! instruction set. Following execution of 
{\f1 FEMMS}, the state of the {\f1 MMX/FP} registers is undefined, and this 
allows a faster context switch between {\f1 FP} and {\f1 MMX} instructions. 
The {\f1 FEMMS} instruction can also be used {\i before} executing 
{\f1 MMX} instructions
\par\sb120
\page
#{\footnote section_b_4_79}
${\footnote B.4.79. FFREE: Flag Floating-Point Register as Unused}
+{\footnote browse:00299}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FFREE}
\keepn\f2\b\fs30\sb60\sa60
B.4.79. {\f1 FFREE}: Flag Floating-Point Register as Unused
\par\pard\plain\sb120
\keep\f1\sb120
FFREE fpureg                  ; DD C0+r              [8086,FPU] \par\sb0
FFREEP fpureg                 ; DF C0+r              [286,FPU,UNDOC]\par\sb0
\pard\f0\sb120
{\f1 FFREE} marks the given register as being empty.
\par\sb120
{\f1 FFREEP} marks the given register as being empty, and then pops the 
register stack.
\par\sb120
\page
#{\footnote section_b_4_80}
${\footnote B.4.80. FIADD: Floating-Point/Integer Addition}
+{\footnote browse:00300}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FIADD}
\keepn\f2\b\fs30\sb60\sa60
B.4.80. {\f1 FIADD}: Floating-Point/Integer Addition
\par\pard\plain\sb120
\keep\f1\sb120
FIADD mem16                   ; DE /0                [8086,FPU] \par\sb0
FIADD mem32                   ; DA /0                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FIADD} adds the 16-bit or 32-bit integer stored in the given memory 
location to {\f1 ST0}, storing the result in {\f1 ST0}.
\par\sb120
\page
#{\footnote section_b_4_81}
${\footnote B.4.81. FICOM, FICOMP: Floating-Point/Integer Compare}
+{\footnote browse:00301}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FICOM;
FICOMP}
\keepn\f2\b\fs30\sb60\sa60
B.4.81. {\f1 FICOM}, {\f1 FICOMP}: Floating-Point/Integer Compare
\par\pard\plain\sb120
\keep\f1\sb120
FICOM mem16                   ; DE /2                [8086,FPU] \par\sb0
FICOM mem32                   ; DA /2                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FICOMP mem16                  ; DE /3                [8086,FPU] \par\sb0
FICOMP mem32                  ; DA /3                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FICOM} compares {\f1 ST0} with the 16-bit or 32-bit integer stored in 
the given memory location, and sets the FPU flags accordingly. {\f1 FICOMP} 
does the same, but pops the register stack afterwards.
\par\sb120
\page
#{\footnote section_b_4_82}
${\footnote B.4.82. FIDIV, FIDIVR: Floating-Point/Integer Division}
+{\footnote browse:00302}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FIDIV;
FIDIVR}
\keepn\f2\b\fs30\sb60\sa60
B.4.82. {\f1 FIDIV}, {\f1 FIDIVR}: Floating-Point/Integer Division
\par\pard\plain\sb120
\keep\f1\sb120
FIDIV mem16                   ; DE /6                [8086,FPU] \par\sb0
FIDIV mem32                   ; DA /6                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FIDIVR mem16                  ; DE /7                [8086,FPU] \par\sb0
FIDIVR mem32                  ; DA /7                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FIDIV} divides {\f1 ST0} by the 16-bit or 32-bit integer stored in the 
given memory location, and stores the result in {\f1 ST0}. {\f1 FIDIVR} 
does the division the other way up: it divides the integer by {\f1 ST0}, 
but still stores the result in {\f1 ST0}.
\par\sb120
\page
#{\footnote section_b_4_83}
${\footnote B.4.83. FILD, FIST, FISTP: Floating-Point/Integer Conversion}
+{\footnote browse:00303}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FILD;
FIST;
FISTP}
\keepn\f2\b\fs30\sb60\sa60
B.4.83. {\f1 FILD}, {\f1 FIST}, {\f1 FISTP}: Floating-Point/Integer Conversion
\par\pard\plain\sb120
\keep\f1\sb120
FILD mem16                    ; DF /0                [8086,FPU] \par\sb0
FILD mem32                    ; DB /0                [8086,FPU] \par\sb0
FILD mem64                    ; DF /5                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FIST mem16                    ; DF /2                [8086,FPU] \par\sb0
FIST mem32                    ; DB /2                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FISTP mem16                   ; DF /3                [8086,FPU] \par\sb0
FISTP mem32                   ; DB /3                [8086,FPU] \par\sb0
FISTP mem64                   ; DF /7                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FILD} loads an integer out of a memory location, converts it to a 
real, and pushes it on the FPU register stack. {\f1 FIST} converts 
{\f1 ST0} to an integer and stores that in memory; {\f1 FISTP} does the 
same as {\f1 FIST}, but pops the register stack afterwards.
\par\sb120
\page
#{\footnote section_b_4_84}
${\footnote B.4.84. FIMUL: Floating-Point/Integer Multiplication}
+{\footnote browse:00304}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FIMUL}
\keepn\f2\b\fs30\sb60\sa60
B.4.84. {\f1 FIMUL}: Floating-Point/Integer Multiplication
\par\pard\plain\sb120
\keep\f1\sb120
FIMUL mem16                   ; DE /1                [8086,FPU] \par\sb0
FIMUL mem32                   ; DA /1                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FIMUL} multiplies {\f1 ST0} by the 16-bit or 32-bit integer stored in 
the given memory location, and stores the result in {\f1 ST0}.
\par\sb120
\page
#{\footnote section_b_4_85}
${\footnote B.4.85. FINCSTP: Increment Floating-Point Stack Pointer}
+{\footnote browse:00305}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FINCSTP}
\keepn\f2\b\fs30\sb60\sa60
B.4.85. {\f1 FINCSTP}: Increment Floating-Point Stack Pointer
\par\pard\plain\sb120
\keep\f1\sb120
FINCSTP                       ; D9 F7                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FINCSTP} increments the `top' field in the floating-point status word. 
This has the effect of rotating the FPU register stack by one, as if the 
register stack had been popped; however, unlike the popping of the stack 
performed by many FPU instructions, it does not flag the new {\f1 ST7} 
(previously {\f1 ST0}) as empty. See also {\f1 FDECSTP} ({\uldb section 
B.4.75}{\v section_b_4_75}).
\par\sb120
\page
#{\footnote section_b_4_86}
${\footnote B.4.86. FINIT, FNINIT: Initialise Floating-Point Unit}
+{\footnote browse:00306}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FINIT;
FNINIT}
\keepn\f2\b\fs30\sb60\sa60
B.4.86. {\f1 FINIT}, {\f1 FNINIT}: Initialise Floating-Point Unit
\par\pard\plain\sb120
\keep\f1\sb120
FINIT                         ; 9B DB E3             [8086,FPU] \par\sb0
FNINIT                        ; DB E3                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FINIT} initialises the FPU to its default state. It flags all 
registers as empty, without actually change their values, clears the top of 
stack pointer. {\f1 FNINIT} does the same, without first waiting for 
pending exceptions to clear.
\par\sb120
\page
#{\footnote section_b_4_87}
${\footnote B.4.87. FISUB: Floating-Point/Integer Subtraction}
+{\footnote browse:00307}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FISUB}
\keepn\f2\b\fs30\sb60\sa60
B.4.87. {\f1 FISUB}: Floating-Point/Integer Subtraction
\par\pard\plain\sb120
\keep\f1\sb120
FISUB mem16                   ; DE /4                [8086,FPU] \par\sb0
FISUB mem32                   ; DA /4                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FISUBR mem16                  ; DE /5                [8086,FPU] \par\sb0
FISUBR mem32                  ; DA /5                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FISUB} subtracts the 16-bit or 32-bit integer stored in the given 
memory location from {\f1 ST0}, and stores the result in {\f1 ST0}. 
{\f1 FISUBR} does the subtraction the other way round, i.e. it subtracts 
{\f1 ST0} from the given integer, but still stores the result in {\f1 ST0}.
\par\sb120
\page
#{\footnote section_b_4_88}
${\footnote B.4.88. FLD: Floating-Point Load}
+{\footnote browse:00308}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FLD}
\keepn\f2\b\fs30\sb60\sa60
B.4.88. {\f1 FLD}: Floating-Point Load
\par\pard\plain\sb120
\keep\f1\sb120
FLD mem32                     ; D9 /0                [8086,FPU] \par\sb0
FLD mem64                     ; DD /0                [8086,FPU] \par\sb0
FLD mem80                     ; DB /5                [8086,FPU] \par\sb0
FLD fpureg                    ; D9 C0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FLD} loads a floating-point value out of the given register or memory 
location, and pushes it on the FPU register stack.
\par\sb120
\page
#{\footnote section_b_4_89}
${\footnote B.4.89. FLDxx: Floating-Point Load Constants}
+{\footnote browse:00309}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FLDxx}
\keepn\f2\b\fs30\sb60\sa60
B.4.89. {\f1 FLDxx}: Floating-Point Load Constants
\par\pard\plain\sb120
\keep\f1\sb120
FLD1                          ; D9 E8                [8086,FPU] \par\sb0
FLDL2E                        ; D9 EA                [8086,FPU] \par\sb0
FLDL2T                        ; D9 E9                [8086,FPU] \par\sb0
FLDLG2                        ; D9 EC                [8086,FPU] \par\sb0
FLDLN2                        ; D9 ED                [8086,FPU] \par\sb0
FLDPI                         ; D9 EB                [8086,FPU] \par\sb0
FLDZ                          ; D9 EE                [8086,FPU]\par\sb0
\pard\f0\sb120
These instructions push specific standard constants on the FPU register 
stack.
\par\sb120
\keep\f1\sb120
 Instruction    Constant pushed\par\sb0
\pard\f0\sb120
\keep\f1\sb120
 FLD1           1 \par\sb0
 FLDL2E         base-2 logarithm of e \par\sb0
 FLDL2T         base-2 log of 10 \par\sb0
 FLDLG2         base-10 log of 2 \par\sb0
 FLDLN2         base-e log of 2 \par\sb0
 FLDPI          pi \par\sb0
 FLDZ           zero\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_90}
${\footnote B.4.90. FLDCW: Load Floating-Point Control Word}
+{\footnote browse:00310}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FLDCW}
\keepn\f2\b\fs30\sb60\sa60
B.4.90. {\f1 FLDCW}: Load Floating-Point Control Word
\par\pard\plain\sb120
\keep\f1\sb120
FLDCW mem16                   ; D9 /5                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FLDCW} loads a 16-bit value out of memory and stores it into the FPU 
control word (governing things like the rounding mode, the precision, and 
the exception masks). See also {\f1 FSTCW} ({\uldb section 
B.4.103}{\v section_b_4_103}). If exceptions are enabled and you don't want 
to generate one, use {\f1 FCLEX} or {\f1 FNCLEX} ({\uldb section 
B.4.71}{\v section_b_4_71}) before loading the new control word.
\par\sb120
\page
#{\footnote section_b_4_91}
${\footnote B.4.91. FLDENV: Load Floating-Point Environment}
+{\footnote browse:00311}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FLDENV}
\keepn\f2\b\fs30\sb60\sa60
B.4.91. {\f1 FLDENV}: Load Floating-Point Environment
\par\pard\plain\sb120
\keep\f1\sb120
FLDENV mem                    ; D9 /4                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FLDENV} loads the FPU operating environment (control word, status 
word, tag word, instruction pointer, data pointer and last opcode) from 
memory. The memory area is 14 or 28 bytes long, depending on the CPU mode 
at the time. See also {\f1 FSTENV} ({\uldb section 
B.4.104}{\v section_b_4_104}).
\par\sb120
\page
#{\footnote section_b_4_92}
${\footnote B.4.92. FMUL, FMULP: Floating-Point Multiply}
+{\footnote browse:00312}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FMUL;
FMULP}
\keepn\f2\b\fs30\sb60\sa60
B.4.92. {\f1 FMUL}, {\f1 FMULP}: Floating-Point Multiply
\par\pard\plain\sb120
\keep\f1\sb120
FMUL mem32                    ; D8 /1                [8086,FPU] \par\sb0
FMUL mem64                    ; DC /1                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FMUL fpureg                   ; D8 C8+r              [8086,FPU] \par\sb0
FMUL ST0,fpureg               ; D8 C8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FMUL TO fpureg                ; DC C8+r              [8086,FPU] \par\sb0
FMUL fpureg,ST0               ; DC C8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FMULP fpureg                  ; DE C8+r              [8086,FPU] \par\sb0
FMULP fpureg,ST0              ; DE C8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FMUL} multiplies {\f1 ST0} by the given operand, and stores the result 
in {\f1 ST0}, unless the {\f1 TO} qualifier is used in which case it stores 
the result in the operand. {\f1 FMULP} performs the same operation as 
{\f1 FMUL\'A0TO}, and then pops the register stack.
\par\sb120
\page
#{\footnote section_b_4_93}
${\footnote B.4.93. FNOP: Floating-Point No Operation}
+{\footnote browse:00313}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FNOP}
\keepn\f2\b\fs30\sb60\sa60
B.4.93. {\f1 FNOP}: Floating-Point No Operation
\par\pard\plain\sb120
\keep\f1\sb120
FNOP                          ; D9 D0                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FNOP} does nothing.
\par\sb120
\page
#{\footnote section_b_4_94}
${\footnote B.4.94. FPATAN, FPTAN: Arctangent and Tangent}
+{\footnote browse:00314}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FPATAN;
FPTAN}
\keepn\f2\b\fs30\sb60\sa60
B.4.94. {\f1 FPATAN}, {\f1 FPTAN}: Arctangent and Tangent
\par\pard\plain\sb120
\keep\f1\sb120
FPATAN                        ; D9 F3                [8086,FPU] \par\sb0
FPTAN                         ; D9 F2                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FPATAN} computes the arctangent, in radians, of the result of dividing 
{\f1 ST1} by {\f1 ST0}, stores the result in {\f1 ST1}, and pops the 
register stack. It works like the C {\f1 atan2} function, in that changing 
the sign of both {\f1 ST0} and {\f1 ST1} changes the output value by pi (so 
it performs true rectangular-to-polar coordinate conversion, with {\f1 ST1} 
being the Y coordinate and {\f1 ST0} being the X coordinate, not merely an 
arctangent).
\par\sb120
{\f1 FPTAN} computes the tangent of the value in {\f1 ST0} (in radians), 
and stores the result back into {\f1 ST0}.
\par\sb120
The absolute value of {\f1 ST0} must be less than 2**63.
\par\sb120
\page
#{\footnote section_b_4_95}
${\footnote B.4.95. FPREM, FPREM1: Floating-Point Partial Remainder}
+{\footnote browse:00315}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FPREM;
FPREM1}
\keepn\f2\b\fs30\sb60\sa60
B.4.95. {\f1 FPREM}, {\f1 FPREM1}: Floating-Point Partial Remainder
\par\pard\plain\sb120
\keep\f1\sb120
FPREM                         ; D9 F8                [8086,FPU] \par\sb0
FPREM1                        ; D9 F5                [386,FPU]\par\sb0
\pard\f0\sb120
These instructions both produce the remainder obtained by dividing 
{\f1 ST0} by {\f1 ST1}. This is calculated, notionally, by dividing 
{\f1 ST0} by {\f1 ST1}, rounding the result to an integer, multiplying by 
{\f1 ST1} again, and computing the value which would need to be added back 
on to the result to get back to the original value in {\f1 ST0}.
\par\sb120
The two instructions differ in the way the notional round-to-integer 
operation is performed. {\f1 FPREM} does it by rounding towards zero, so 
that the remainder it returns always has the same sign as the original 
value in {\f1 ST0}; {\f1 FPREM1} does it by rounding to the nearest 
integer, so that the remainder always has at most half the magnitude of 
{\f1 ST1}.
\par\sb120
Both instructions calculate {\i partial} remainders, meaning that they may 
not manage to provide the final result, but might leave intermediate 
results in {\f1 ST0} instead. If this happens, they will set the C2 flag in 
the FPU status word; therefore, to calculate a remainder, you should 
repeatedly execute {\f1 FPREM} or {\f1 FPREM1} until C2 becomes clear.
\par\sb120
\page
#{\footnote section_b_4_96}
${\footnote B.4.96. FRNDINT: Floating-Point Round to Integer}
+{\footnote browse:00316}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FRNDINT}
\keepn\f2\b\fs30\sb60\sa60
B.4.96. {\f1 FRNDINT}: Floating-Point Round to Integer
\par\pard\plain\sb120
\keep\f1\sb120
FRNDINT                       ; D9 FC                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FRNDINT} rounds the contents of {\f1 ST0} to an integer, according to 
the current rounding mode set in the FPU control word, and stores the 
result back in {\f1 ST0}.
\par\sb120
\page
#{\footnote section_b_4_97}
${\footnote B.4.97. FSAVE, FRSTOR: Save/Restore Floating-Point State}
+{\footnote browse:00317}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FRSTOR;
FSAVE}
\keepn\f2\b\fs30\sb60\sa60
B.4.97. {\f1 FSAVE}, {\f1 FRSTOR}: Save/Restore Floating-Point State
\par\pard\plain\sb120
\keep\f1\sb120
FSAVE mem                     ; 9B DD /6             [8086,FPU] \par\sb0
FNSAVE mem                    ; DD /6                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FRSTOR mem                    ; DD /4                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FSAVE} saves the entire floating-point unit state, including all the 
information saved by {\f1 FSTENV} ({\uldb section 
B.4.104}{\v section_b_4_104}) plus the contents of all the registers, to a 
94 or 108 byte area of memory (depending on the CPU mode). {\f1 FRSTOR} 
restores the floating-point state from the same area of memory.
\par\sb120
{\f1 FNSAVE} does the same as {\f1 FSAVE}, without first waiting for 
pending floating-point exceptions to clear.
\par\sb120
\page
#{\footnote section_b_4_98}
${\footnote B.4.98. FSCALE: Scale Floating-Point Value by Power of Two}
+{\footnote browse:00318}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FSCALE}
\keepn\f2\b\fs30\sb60\sa60
B.4.98. {\f1 FSCALE}: Scale Floating-Point Value by Power of Two
\par\pard\plain\sb120
\keep\f1\sb120
FSCALE                        ; D9 FD                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FSCALE} scales a number by a power of two: it rounds {\f1 ST1} towards 
zero to obtain an integer, then multiplies {\f1 ST0} by two to the power of 
that integer, and stores the result in {\f1 ST0}.
\par\sb120
\page
#{\footnote section_b_4_99}
${\footnote B.4.99. FSETPM: Set Protected Mode}
+{\footnote browse:00319}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FSETPM}
\keepn\f2\b\fs30\sb60\sa60
B.4.99. {\f1 FSETPM}: Set Protected Mode
\par\pard\plain\sb120
\keep\f1\sb120
FSETPM                        ; DB E4                [286,FPU]\par\sb0
\pard\f0\sb120
This instruction initialises protected mode on the 287 floating-point 
coprocessor. It is only meaningful on that processor: the 387 and above 
treat the instruction as a no-operation.
\par\sb120
\page
#{\footnote section_b_4_100}
${\footnote B.4.100. FSIN, FSINCOS: Sine and Cosine}
+{\footnote browse:00320}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FSIN;
FSINCOS}
\keepn\f2\b\fs30\sb60\sa60
B.4.100. {\f1 FSIN}, {\f1 FSINCOS}: Sine and Cosine
\par\pard\plain\sb120
\keep\f1\sb120
FSIN                          ; D9 FE                [386,FPU] \par\sb0
FSINCOS                       ; D9 FB                [386,FPU]\par\sb0
\pard\f0\sb120
{\f1 FSIN} calculates the sine of {\f1 ST0} (in radians) and stores the 
result in {\f1 ST0}. {\f1 FSINCOS} does the same, but then pushes the 
cosine of the same value on the register stack, so that the sine ends up in 
{\f1 ST1} and the cosine in {\f1 ST0}. {\f1 FSINCOS} is faster than 
executing {\f1 FSIN} and {\f1 FCOS} (see {\uldb section 
B.4.74}{\v section_b_4_74}) in succession.
\par\sb120
The absolute value of {\f1 ST0} must be less than 2**63.
\par\sb120
\page
#{\footnote section_b_4_101}
${\footnote B.4.101. FSQRT: Floating-Point Square Root}
+{\footnote browse:00321}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FSQRT}
\keepn\f2\b\fs30\sb60\sa60
B.4.101. {\f1 FSQRT}: Floating-Point Square Root
\par\pard\plain\sb120
\keep\f1\sb120
FSQRT                         ; D9 FA                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FSQRT} calculates the square root of {\f1 ST0} and stores the result 
in {\f1 ST0}.
\par\sb120
\page
#{\footnote section_b_4_102}
${\footnote B.4.102. FST, FSTP: Floating-Point Store}
+{\footnote browse:00322}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FST;
FSTP}
\keepn\f2\b\fs30\sb60\sa60
B.4.102. {\f1 FST}, {\f1 FSTP}: Floating-Point Store
\par\pard\plain\sb120
\keep\f1\sb120
FST mem32                     ; D9 /2                [8086,FPU] \par\sb0
FST mem64                     ; DD /2                [8086,FPU] \par\sb0
FST fpureg                    ; DD D0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FSTP mem32                    ; D9 /3                [8086,FPU] \par\sb0
FSTP mem64                    ; DD /3                [8086,FPU] \par\sb0
FSTP mem80                    ; DB /7                [8086,FPU] \par\sb0
FSTP fpureg                   ; DD D8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FST} stores the value in {\f1 ST0} into the given memory location or 
other FPU register. {\f1 FSTP} does the same, but then pops the register 
stack.
\par\sb120
\page
#{\footnote section_b_4_103}
${\footnote B.4.103. FSTCW: Store Floating-Point Control Word}
+{\footnote browse:00323}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FSTCW}
\keepn\f2\b\fs30\sb60\sa60
B.4.103. {\f1 FSTCW}: Store Floating-Point Control Word
\par\pard\plain\sb120
\keep\f1\sb120
FSTCW mem16                   ; 9B D9 /7             [8086,FPU] \par\sb0
FNSTCW mem16                  ; D9 /7                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FSTCW} stores the {\f1 FPU} control word (governing things like the 
rounding mode, the precision, and the exception masks) into a 2-byte memory 
area. See also {\f1 FLDCW} ({\uldb section B.4.90}{\v section_b_4_90}).
\par\sb120
{\f1 FNSTCW} does the same thing as {\f1 FSTCW}, without first waiting for 
pending floating-point exceptions to clear.
\par\sb120
\page
#{\footnote section_b_4_104}
${\footnote B.4.104. FSTENV: Store Floating-Point Environment}
+{\footnote browse:00324}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FSTENV}
\keepn\f2\b\fs30\sb60\sa60
B.4.104. {\f1 FSTENV}: Store Floating-Point Environment
\par\pard\plain\sb120
\keep\f1\sb120
FSTENV mem                    ; 9B D9 /6             [8086,FPU] \par\sb0
FNSTENV mem                   ; D9 /6                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FSTENV} stores the {\f1 FPU} operating environment (control word, 
status word, tag word, instruction pointer, data pointer and last opcode) 
into memory. The memory area is 14 or 28 bytes long, depending on the CPU 
mode at the time. See also {\f1 FLDENV} ({\uldb section 
B.4.91}{\v section_b_4_91}).
\par\sb120
{\f1 FNSTENV} does the same thing as {\f1 FSTENV}, without first waiting 
for pending floating-point exceptions to clear.
\par\sb120
\page
#{\footnote section_b_4_105}
${\footnote B.4.105. FSTSW: Store Floating-Point Status Word}
+{\footnote browse:00325}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FSTSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.105. {\f1 FSTSW}: Store Floating-Point Status Word
\par\pard\plain\sb120
\keep\f1\sb120
FSTSW mem16                   ; 9B DD /7             [8086,FPU] \par\sb0
FSTSW AX                      ; 9B DF E0             [286,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FNSTSW mem16                  ; DD /7                [8086,FPU] \par\sb0
FNSTSW AX                     ; DF E0                [286,FPU]\par\sb0
\pard\f0\sb120
{\f1 FSTSW} stores the {\f1 FPU} status word into {\f1 AX} or into a 2-byte 
memory area.
\par\sb120
{\f1 FNSTSW} does the same thing as {\f1 FSTSW}, without first waiting for 
pending floating-point exceptions to clear.
\par\sb120
\page
#{\footnote section_b_4_106}
${\footnote B.4.106. FSUB, FSUBP, FSUBR, FSUBRP: Floating-Point Subtract}
+{\footnote browse:00326}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FSUB;
FSUBP;
FSUBR;
FSUBRP}
\keepn\f2\b\fs30\sb60\sa60
B.4.106. {\f1 FSUB}, {\f1 FSUBP}, {\f1 FSUBR}, {\f1 FSUBRP}: Floating-Point Subtract
\par\pard\plain\sb120
\keep\f1\sb120
FSUB mem32                    ; D8 /4                [8086,FPU] \par\sb0
FSUB mem64                    ; DC /4                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FSUB fpureg                   ; D8 E0+r              [8086,FPU] \par\sb0
FSUB ST0,fpureg               ; D8 E0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FSUB TO fpureg                ; DC E8+r              [8086,FPU] \par\sb0
FSUB fpureg,ST0               ; DC E8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FSUBR mem32                   ; D8 /5                [8086,FPU] \par\sb0
FSUBR mem64                   ; DC /5                [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FSUBR fpureg                  ; D8 E8+r              [8086,FPU] \par\sb0
FSUBR ST0,fpureg              ; D8 E8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FSUBR TO fpureg               ; DC E0+r              [8086,FPU] \par\sb0
FSUBR fpureg,ST0              ; DC E0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FSUBP fpureg                  ; DE E8+r              [8086,FPU] \par\sb0
FSUBP fpureg,ST0              ; DE E8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FSUBRP fpureg                 ; DE E0+r              [8086,FPU] \par\sb0
FSUBRP fpureg,ST0             ; DE E0+r              [8086,FPU]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FSUB} subtracts the given operand from {\f1 ST0} and stores the result 
back in {\f1 ST0}, unless the {\f1 TO} qualifier is given, in which case it 
subtracts {\f1 ST0} from the given operand and stores the result in the 
operand.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FSUBR} does the same thing, but does the subtraction the other way up: 
so if {\f1 TO} is not given, it subtracts {\f1 ST0} from the given operand 
and stores the result in {\f1 ST0}, whereas if {\f1 TO} is given it 
subtracts its operand from {\f1 ST0} and stores the result in the operand.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FSUBP} operates like {\f1 FSUB\'A0TO}, but pops the register stack 
once it has finished.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FSUBRP} operates like {\f1 FSUBR\'A0TO}, but pops the register stack 
once it has finished.
\par\pard\sb120
\page
#{\footnote section_b_4_107}
${\footnote B.4.107. FTST: Test ST0 Against Zero}
+{\footnote browse:00327}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FTST}
\keepn\f2\b\fs30\sb60\sa60
B.4.107. {\f1 FTST}: Test {\f1 ST0} Against Zero
\par\pard\plain\sb120
\keep\f1\sb120
FTST                          ; D9 E4                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FTST} compares {\f1 ST0} with zero and sets the FPU flags accordingly. 
{\f1 ST0} is treated as the left-hand side of the comparison, so that a 
`less-than' result is generated if {\f1 ST0} is negative.
\par\sb120
\page
#{\footnote section_b_4_108}
${\footnote B.4.108. FUCOMxx: Floating-Point Unordered Compare}
+{\footnote browse:00328}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FUCOMxx}
\keepn\f2\b\fs30\sb60\sa60
B.4.108. {\f1 FUCOMxx}: Floating-Point Unordered Compare
\par\pard\plain\sb120
\keep\f1\sb120
FUCOM fpureg                  ; DD E0+r              [386,FPU] \par\sb0
FUCOM ST0,fpureg              ; DD E0+r              [386,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FUCOMP fpureg                 ; DD E8+r              [386,FPU] \par\sb0
FUCOMP ST0,fpureg             ; DD E8+r              [386,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FUCOMPP                       ; DA E9                [386,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FUCOMI fpureg                 ; DB E8+r              [P6,FPU] \par\sb0
FUCOMI ST0,fpureg             ; DB E8+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
FUCOMIP fpureg                ; DF E8+r              [P6,FPU] \par\sb0
FUCOMIP ST0,fpureg            ; DF E8+r              [P6,FPU]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FUCOM} compares {\f1 ST0} with the given operand, and sets the FPU 
flags accordingly. {\f1 ST0} is treated as the left-hand side of the 
comparison, so that the carry flag is set (for a `less-than' result) if 
{\f1 ST0} is less than the given operand.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FUCOMP} does the same as {\f1 FUCOM}, but pops the register stack 
afterwards. {\f1 FUCOMPP} compares {\f1 ST0} with {\f1 ST1} and then pops 
the register stack twice.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 FUCOMI} and {\f1 FUCOMIP} work like the corresponding forms of 
{\f1 FUCOM} and {\f1 FUCOMP}, but write their results directly to the CPU 
flags register rather than the FPU status word, so they can be immediately 
followed by conditional jump or conditional move instructions.
\par\pard\sb120
The {\f1 FUCOM} instructions differ from the {\f1 FCOM} instructions 
({\uldb section B.4.73}{\v section_b_4_73}) only in the way they handle 
quiet NaNs: {\f1 FUCOM} will handle them silently and set the condition 
code flags to an `unordered' result, whereas {\f1 FCOM} will generate an 
exception.
\par\sb120
\page
#{\footnote section_b_4_109}
${\footnote B.4.109. FXAM: Examine Class of Value in ST0}
+{\footnote browse:00329}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FXAM}
\keepn\f2\b\fs30\sb60\sa60
B.4.109. {\f1 FXAM}: Examine Class of Value in {\f1 ST0}
\par\pard\plain\sb120
\keep\f1\sb120
FXAM                          ; D9 E5                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FXAM} sets the FPU flags {\f1 C3}, {\f1 C2} and {\f1 C0} depending on 
the type of value stored in {\f1 ST0}:
\par\sb120
\keep\f1\sb120
 Register contents     Flags\par\sb0
\pard\f0\sb120
\keep\f1\sb120
 Unsupported format    000 \par\sb0
 NaN                   001 \par\sb0
 Finite number         010 \par\sb0
 Infinity              011 \par\sb0
 Zero                  100 \par\sb0
 Empty register        101 \par\sb0
 Denormal              110\par\sb0
\pard\f0\sb120
Additionally, the {\f1 C1} flag is set to the sign of the number.
\par\sb120
\page
#{\footnote section_b_4_110}
${\footnote B.4.110. FXCH: Floating-Point Exchange}
+{\footnote browse:00330}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FXCH}
\keepn\f2\b\fs30\sb60\sa60
B.4.110. {\f1 FXCH}: Floating-Point Exchange
\par\pard\plain\sb120
\keep\f1\sb120
FXCH                          ; D9 C9                [8086,FPU] \par\sb0
FXCH fpureg                   ; D9 C8+r              [8086,FPU] \par\sb0
FXCH fpureg,ST0               ; D9 C8+r              [8086,FPU] \par\sb0
FXCH ST0,fpureg               ; D9 C8+r              [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FXCH} exchanges {\f1 ST0} with a given FPU register. The no-operand 
form exchanges {\f1 ST0} with {\f1 ST1}.
\par\sb120
\page
#{\footnote section_b_4_111}
${\footnote B.4.111. FXRSTOR: Restore FP, MMX and SSE State}
+{\footnote browse:00331}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FXRSTOR}
\keepn\f2\b\fs30\sb60\sa60
B.4.111. {\f1 FXRSTOR}: Restore {\f1 FP}, {\f1 MMX} and {\f1 SSE} State
\par\pard\plain\sb120
\keep\f1\sb120
FXRSTOR memory                ; 0F AE /1               [P6,SSE,FPU]\par\sb0
\pard\f0\sb120
The {\f1 FXRSTOR} instruction reloads the {\f1 FPU}, {\f1 MMX} and 
{\f1 SSE} state (environment and registers), from the 512 byte memory area 
defined by the source operand. This data should have been written by a 
previous {\f1 FXSAVE}.
\par\sb120
\page
#{\footnote section_b_4_112}
${\footnote B.4.112. FXSAVE: Store FP, MMX and SSE State}
+{\footnote browse:00332}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FXSAVE}
\keepn\f2\b\fs30\sb60\sa60
B.4.112. {\f1 FXSAVE}: Store {\f1 FP}, {\f1 MMX} and {\f1 SSE} State
\par\pard\plain\sb120
\keep\f1\sb120
FXSAVE memory                 ; 0F AE /0         [P6,SSE,FPU]\par\sb0
\pard\f0\sb120
{\f1 FXSAVE}The FXSAVE instruction writes the current {\f1 FPU}, {\f1 MMX} 
and {\f1 SSE} technology states (environment and registers), to the 512 
byte memory area defined by the destination operand. It does this without 
checking for pending unmasked floating-point exceptions (similar to the 
operation of {\f1 FNSAVE}).
\par\sb120
Unlike the {\f1 FSAVE/FNSAVE} instructions, the processor retains the 
contents of the {\f1 FPU}, {\f1 MMX} and {\f1 SSE} state in the processor 
after the state has been saved. This instruction has been optimised to 
maximize floating-point save performance.
\par\sb120
\page
#{\footnote section_b_4_113}
${\footnote B.4.113. FXTRACT: Extract Exponent and Significand}
+{\footnote browse:00333}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FXTRACT}
\keepn\f2\b\fs30\sb60\sa60
B.4.113. {\f1 FXTRACT}: Extract Exponent and Significand
\par\pard\plain\sb120
\keep\f1\sb120
FXTRACT                       ; D9 F4                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FXTRACT} separates the number in {\f1 ST0} into its exponent and 
significand (mantissa), stores the exponent back into {\f1 ST0}, and then 
pushes the significand on the register stack (so that the significand ends 
up in {\f1 ST0}, and the exponent in {\f1 ST1}).
\par\sb120
\page
#{\footnote section_b_4_114}
${\footnote B.4.114. FYL2X, FYL2XP1: Compute Y times Log2(X) or Log2(X+1)}
+{\footnote browse:00334}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote FYL2X;
FYL2XP1}
\keepn\f2\b\fs30\sb60\sa60
B.4.114. {\f1 FYL2X}, {\f1 FYL2XP1}: Compute Y times Log2(X) or Log2(X+1)
\par\pard\plain\sb120
\keep\f1\sb120
FYL2X                         ; D9 F1                [8086,FPU] \par\sb0
FYL2XP1                       ; D9 F9                [8086,FPU]\par\sb0
\pard\f0\sb120
{\f1 FYL2X} multiplies {\f1 ST1} by the base-2 logarithm of {\f1 ST0}, 
stores the result in {\f1 ST1}, and pops the register stack (so that the 
result ends up in {\f1 ST0}). {\f1 ST0} must be non-zero and positive.
\par\sb120
{\f1 FYL2XP1} works the same way, but replacing the base-2 log of {\f1 ST0} 
with that of {\f1 ST0} plus one. This time, {\f1 ST0} must have magnitude 
no greater than 1 minus half the square root of two.
\par\sb120
\page
#{\footnote section_b_4_115}
${\footnote B.4.115. HLT: Halt Processor}
+{\footnote browse:00335}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote HLT}
\keepn\f2\b\fs30\sb60\sa60
B.4.115. {\f1 HLT}: Halt Processor
\par\pard\plain\sb120
\keep\f1\sb120
HLT                           ; F4                   [8086,PRIV]\par\sb0
\pard\f0\sb120
{\f1 HLT} puts the processor into a halted state, where it will perform no 
more operations until restarted by an interrupt or a reset.
\par\sb120
On the 286 and later processors, this is a privileged instruction.
\par\sb120
\page
#{\footnote section_b_4_116}
${\footnote B.4.116. IBTS: Insert Bit String}
+{\footnote browse:00336}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote IBTS}
\keepn\f2\b\fs30\sb60\sa60
B.4.116. {\f1 IBTS}: Insert Bit String
\par\pard\plain\sb120
\keep\f1\sb120
IBTS r/m16,reg16              ; o16 0F A7 /r         [386,UNDOC] \par\sb0
IBTS r/m32,reg32              ; o32 0F A7 /r         [386,UNDOC]\par\sb0
\pard\f0\sb120
The implied operation of this instruction is:
\par\sb120
\keep\f1\sb120
IBTS r/m16,AX,CL,reg16 \par\sb0
IBTS r/m32,EAX,CL,reg32\par\sb0
\pard\f0\sb120
Writes a bit string from the source operand to the destination. {\f1 CL} 
indicates the number of bits to be copied, from the low bits of the source. 
{\f1 (E)AX} indicates the low order bit offset in the destination that is 
written to. For example, if {\f1 CL} is set to 4 and {\f1 AX} (for 16-bit 
code) is set to 5, bits 0-3 of {\f1 src} will be copied to bits 5-8 of 
{\f1 dst}. This instruction is very poorly documented, and I have been 
unable to find any official source of documentation on it.
\par\sb120
{\f1 IBTS} is supported only on the early Intel 386s, and conflicts with 
the opcodes for {\f1 CMPXCHG486} (on early Intel 486s). NASM supports it 
only for completeness. Its counterpart is {\f1 XBTS} (see {\uldb section 
B.4.332}{\v section_b_4_332}).
\par\sb120
\page
#{\footnote section_b_4_117}
${\footnote B.4.117. IDIV: Signed Integer Divide}
+{\footnote browse:00337}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote IDIV}
\keepn\f2\b\fs30\sb60\sa60
B.4.117. {\f1 IDIV}: Signed Integer Divide
\par\pard\plain\sb120
\keep\f1\sb120
IDIV r/m8                     ; F6 /7                [8086] \par\sb0
IDIV r/m16                    ; o16 F7 /7            [8086] \par\sb0
IDIV r/m32                    ; o32 F7 /7            [386]\par\sb0
\pard\f0\sb120
{\f1 IDIV} performs signed integer division. The explicit operand provided 
is the divisor; the dividend and destination operands are implicit, in the 
following way:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 IDIV\'A0r/m8}, {\f1 AX} is divided by the given operand; the 
quotient is stored in {\f1 AL} and the remainder in {\f1 AH}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 IDIV\'A0r/m16}, {\f1 DX:AX} is divided by the given operand; the 
quotient is stored in {\f1 AX} and the remainder in {\f1 DX}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 IDIV\'A0r/m32}, {\f1 EDX:EAX} is divided by the given operand; the 
quotient is stored in {\f1 EAX} and the remainder in {\f1 EDX}.
\par\pard\sb120
Unsigned integer division is performed by the {\f1 DIV} instruction: see 
{\uldb section B.4.59}{\v section_b_4_59}.
\par\sb120
\page
#{\footnote section_b_4_118}
${\footnote B.4.118. IMUL: Signed Integer Multiply}
+{\footnote browse:00338}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote IMUL}
\keepn\f2\b\fs30\sb60\sa60
B.4.118. {\f1 IMUL}: Signed Integer Multiply
\par\pard\plain\sb120
\keep\f1\sb120
IMUL r/m8                     ; F6 /5                [8086] \par\sb0
IMUL r/m16                    ; o16 F7 /5            [8086] \par\sb0
IMUL r/m32                    ; o32 F7 /5            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
IMUL reg16,r/m16              ; o16 0F AF /r         [386] \par\sb0
IMUL reg32,r/m32              ; o32 0F AF /r         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
IMUL reg16,imm8               ; o16 6B /r ib         [186] \par\sb0
IMUL reg16,imm16              ; o16 69 /r iw         [186] \par\sb0
IMUL reg32,imm8               ; o32 6B /r ib         [386] \par\sb0
IMUL reg32,imm32              ; o32 69 /r id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
IMUL reg16,r/m16,imm8         ; o16 6B /r ib         [186] \par\sb0
IMUL reg16,r/m16,imm16        ; o16 69 /r iw         [186] \par\sb0
IMUL reg32,r/m32,imm8         ; o32 6B /r ib         [386] \par\sb0
IMUL reg32,r/m32,imm32        ; o32 69 /r id         [386]\par\sb0
\pard\f0\sb120
{\f1 IMUL} performs signed integer multiplication. For the single-operand 
form, the other operand and destination are implicit, in the following way:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 IMUL\'A0r/m8}, {\f1 AL} is multiplied by the given operand; the 
product is stored in {\f1 AX}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 IMUL\'A0r/m16}, {\f1 AX} is multiplied by the given operand; the 
product is stored in {\f1 DX:AX}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 IMUL\'A0r/m32}, {\f1 EAX} is multiplied by the given operand; the 
product is stored in {\f1 EDX:EAX}.
\par\pard\sb120
The two-operand form multiplies its two operands and stores the result in 
the destination (first) operand. The three-operand form multiplies its last 
two operands and stores the result in the first operand.
\par\sb120
The two-operand form with an immediate second operand is in fact a 
shorthand for the three-operand form, as can be seen by examining the 
opcode descriptions: in the two-operand form, the code {\f1 /r} takes both 
its register and {\f1 r/m} parts from the same operand (the first one).
\par\sb120
In the forms with an 8-bit immediate operand and another longer source 
operand, the immediate operand is considered to be signed, and is 
sign-extended to the length of the other source operand. In these cases, 
the {\f1 BYTE} qualifier is necessary to force NASM to generate this form 
of the instruction.
\par\sb120
Unsigned integer multiplication is performed by the {\f1 MUL} instruction: 
see {\uldb section B.4.184}{\v section_b_4_184}.
\par\sb120
\page
#{\footnote section_b_4_119}
${\footnote B.4.119. IN: Input from I/O Port}
+{\footnote browse:00339}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote IN}
\keepn\f2\b\fs30\sb60\sa60
B.4.119. {\f1 IN}: Input from I/O Port
\par\pard\plain\sb120
\keep\f1\sb120
IN AL,imm8                    ; E4 ib                [8086] \par\sb0
IN AX,imm8                    ; o16 E5 ib            [8086] \par\sb0
IN EAX,imm8                   ; o32 E5 ib            [386] \par\sb0
IN AL,DX                      ; EC                   [8086] \par\sb0
IN AX,DX                      ; o16 ED               [8086] \par\sb0
IN EAX,DX                     ; o32 ED               [386]\par\sb0
\pard\f0\sb120
{\f1 IN} reads a byte, word or doubleword from the specified I/O port, and 
stores it in the given destination register. The port number may be 
specified as an immediate value if it is between 0 and 255, and otherwise 
must be stored in {\f1 DX}. See also {\f1 OUT} ({\uldb section 
B.4.194}{\v section_b_4_194}).
\par\sb120
\page
#{\footnote section_b_4_120}
${\footnote B.4.120. INC: Increment Integer}
+{\footnote browse:00340}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote INC}
\keepn\f2\b\fs30\sb60\sa60
B.4.120. {\f1 INC}: Increment Integer
\par\pard\plain\sb120
\keep\f1\sb120
INC reg16                     ; o16 40+r             [8086] \par\sb0
INC reg32                     ; o32 40+r             [386] \par\sb0
INC r/m8                      ; FE /0                [8086] \par\sb0
INC r/m16                     ; o16 FF /0            [8086] \par\sb0
INC r/m32                     ; o32 FF /0            [386]\par\sb0
\pard\f0\sb120
{\f1 INC} adds 1 to its operand. It does {\i not} affect the carry flag: to 
affect the carry flag, use {\f1 ADD\'A0something,1} (see {\uldb section 
B.4.3}{\v section_b_4_3}). {\f1 INC} affects all the other flags according 
to the result.
\par\sb120
This instruction can be used with a {\f1 LOCK} prefix to allow atomic 
execution.
\par\sb120
See also {\f1 DEC} ({\uldb section B.4.58}{\v section_b_4_58}).
\par\sb120
\page
#{\footnote section_b_4_121}
${\footnote B.4.121. INSB, INSW, INSD: Input String from I/O Port}
+{\footnote browse:00341}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
INSB;
INSD;
INSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.121. {\f1 INSB}, {\f1 INSW}, {\f1 INSD}: Input String from I/O Port
\par\pard\plain\sb120
\keep\f1\sb120
INSB                          ; 6C                   [186] \par\sb0
INSW                          ; o16 6D               [186] \par\sb0
INSD                          ; o32 6D               [386]\par\sb0
\pard\f0\sb120
{\f1 INSB} inputs a byte from the I/O port specified in {\f1 DX} and stores 
it at {\f1 [ES:DI]} or {\f1 [ES:EDI]}. It then increments or decrements 
(depending on the direction flag: increments if the flag is clear, 
decrements if it is set) {\f1 DI} or {\f1 EDI}.
\par\sb120
The register used is {\f1 DI} if the address size is 16 bits, and {\f1 EDI} 
if it is 32 bits. If you need to use an address size not equal to the 
current {\f1 BITS} setting, you can use an explicit {\f1 a16} or {\f1 a32} 
prefix.
\par\sb120
Segment override prefixes have no effect for this instruction: the use of 
{\f1 ES} for the load from {\f1 [DI]} or {\f1 [EDI]} cannot be overridden.
\par\sb120
{\f1 INSW} and {\f1 INSD} work in the same way, but they input a word or a 
doubleword instead of a byte, and increment or decrement the addressing 
register by 2 or 4 instead of 1.
\par\sb120
The {\f1 REP} prefix may be used to repeat the instruction {\f1 CX} (or 
{\f1 ECX} \'96 again, the address size chooses which) times.
\par\sb120
See also {\f1 OUTSB}, {\f1 OUTSW} and {\f1 OUTSD} ({\uldb section 
B.4.195}{\v section_b_4_195}).
\par\sb120
\page
#{\footnote section_b_4_122}
${\footnote B.4.122. INT: Software Interrupt}
+{\footnote browse:00342}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote INT}
\keepn\f2\b\fs30\sb60\sa60
B.4.122. {\f1 INT}: Software Interrupt
\par\pard\plain\sb120
\keep\f1\sb120
INT imm8                      ; CD ib                [8086]\par\sb0
\pard\f0\sb120
{\f1 INT} causes a software interrupt through a specified vector number 
from 0 to 255.
\par\sb120
The code generated by the {\f1 INT} instruction is always two bytes long: 
although there are short forms for some {\f1 INT} instructions, NASM does 
not generate them when it sees the {\f1 INT} mnemonic. In order to generate 
single-byte breakpoint instructions, use the {\f1 INT3} or {\f1 INT1} 
instructions (see {\uldb section B.4.123}{\v section_b_4_123}) instead.
\par\sb120
\page
#{\footnote section_b_4_123}
${\footnote B.4.123. INT3, INT1, ICEBP, INT01: Breakpoints}
+{\footnote browse:00343}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ICEBP;
INT01;
INT1;
INT3}
\keepn\f2\b\fs30\sb60\sa60
B.4.123. {\f1 INT3}, {\f1 INT1}, {\f1 ICEBP}, {\f1 INT01}: Breakpoints
\par\pard\plain\sb120
\keep\f1\sb120
INT1                          ; F1                   [P6] \par\sb0
ICEBP                         ; F1                   [P6] \par\sb0
INT01                         ; F1                   [P6]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
INT3                          ; CC                   [8086] \par\sb0
INT03                         ; CC                   [8086]\par\sb0
\pard\f0\sb120
{\f1 INT1} and {\f1 INT3} are short one-byte forms of the instructions 
{\f1 INT\'A01} and {\f1 INT\'A03} (see {\uldb section 
B.4.122}{\v section_b_4_122}). They perform a similar function to their 
longer counterparts, but take up less code space. They are used as 
breakpoints by debuggers.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 INT1}, and its alternative synonyms {\f1 INT01} and {\f1 ICEBP}, is an 
instruction used by in-circuit emulators (ICEs). It is present, though not 
documented, on some processors down to the 286, but is only documented for 
the Pentium Pro. {\f1 INT3} is the instruction normally used as a 
breakpoint by debuggers.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 INT3}, and its synonym {\f1 INT03}, is not precisely equivalent to 
{\f1 INT\'A03}: the short form, since it is designed to be used as a 
breakpoint, bypasses the normal {\f1 IOPL} checks in virtual-8086 mode, and 
also does not go through interrupt redirection.
\par\pard\sb120
\page
#{\footnote section_b_4_124}
${\footnote B.4.124. INTO: Interrupt if Overflow}
+{\footnote browse:00344}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote INTO}
\keepn\f2\b\fs30\sb60\sa60
B.4.124. {\f1 INTO}: Interrupt if Overflow
\par\pard\plain\sb120
\keep\f1\sb120
INTO                          ; CE                   [8086]\par\sb0
\pard\f0\sb120
{\f1 INTO} performs an {\f1 INT\'A04} software interrupt (see 
{\uldb section B.4.122}{\v section_b_4_122}) if and only if the overflow 
flag is set.
\par\sb120
\page
#{\footnote section_b_4_125}
${\footnote B.4.125. INVD: Invalidate Internal Caches}
+{\footnote browse:00345}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote INVD}
\keepn\f2\b\fs30\sb60\sa60
B.4.125. {\f1 INVD}: Invalidate Internal Caches
\par\pard\plain\sb120
\keep\f1\sb120
INVD                          ; 0F 08                [486]\par\sb0
\pard\f0\sb120
{\f1 INVD} invalidates and empties the processor's internal caches, and 
causes the processor to instruct external caches to do the same. It does 
not write the contents of the caches back to memory first: any modified 
data held in the caches will be lost. To write the data back first, use 
{\f1 WBINVD} ({\uldb section B.4.328}{\v section_b_4_328}).
\par\sb120
\page
#{\footnote section_b_4_126}
${\footnote B.4.126. INVLPG: Invalidate TLB Entry}
+{\footnote browse:00346}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote INVLPG}
\keepn\f2\b\fs30\sb60\sa60
B.4.126. {\f1 INVLPG}: Invalidate TLB Entry
\par\pard\plain\sb120
\keep\f1\sb120
INVLPG mem                    ; 0F 01 /7             [486]\par\sb0
\pard\f0\sb120
{\f1 INVLPG} invalidates the translation lookahead buffer (TLB) entry 
associated with the supplied memory address.
\par\sb120
\page
#{\footnote section_b_4_127}
${\footnote B.4.127. IRET, IRETW, IRETD: Return from Interrupt}
+{\footnote browse:00347}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote IRET;
IRETD;
IRETW}
\keepn\f2\b\fs30\sb60\sa60
B.4.127. {\f1 IRET}, {\f1 IRETW}, {\f1 IRETD}: Return from Interrupt
\par\pard\plain\sb120
\keep\f1\sb120
IRET                          ; CF                   [8086] \par\sb0
IRETW                         ; o16 CF               [8086] \par\sb0
IRETD                         ; o32 CF               [386]\par\sb0
\pard\f0\sb120
{\f1 IRET} returns from an interrupt (hardware or software) by means of 
popping {\f1 IP} (or {\f1 EIP}), {\f1 CS} and the flags off the stack and 
then continuing execution from the new {\f1 CS:IP}.
\par\sb120
{\f1 IRETW} pops {\f1 IP}, {\f1 CS} and the flags as 2 bytes each, taking 6 
bytes off the stack in total. {\f1 IRETD} pops {\f1 EIP} as 4 bytes, pops a 
further 4 bytes of which the top two are discarded and the bottom two go 
into {\f1 CS}, and pops the flags as 4 bytes as well, taking 12 bytes off 
the stack.
\par\sb120
{\f1 IRET} is a shorthand for either {\f1 IRETW} or {\f1 IRETD}, depending 
on the default {\f1 BITS} setting at the time.
\par\sb120
\page
#{\footnote section_b_4_128}
${\footnote B.4.128. Jcc: Conditional Branch}
+{\footnote browse:00348}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote conditional jump;
Jcc}
\keepn\f2\b\fs30\sb60\sa60
B.4.128. {\f1 Jcc}: Conditional Branch
\par\pard\plain\sb120
\keep\f1\sb120
Jcc imm                       ; 70+cc rb             [8086] \par\sb0
Jcc NEAR imm                  ; 0F 80+cc rw/rd       [386]\par\sb0
\pard\f0\sb120
The conditional jump instructions execute a near (same segment) jump if and 
only if their conditions are satisfied. For example, {\f1 JNZ} jumps only 
if the zero flag is not set.
\par\sb120
The ordinary form of the instructions has only a 128-byte range; the 
{\f1 NEAR} form is a 386 extension to the instruction set, and can span the 
full size of a segment. NASM will not override your choice of jump 
instruction: if you want {\f1 Jcc\'A0NEAR}, you have to use the {\f1 NEAR} 
keyword.
\par\sb120
The {\f1 SHORT} keyword is allowed on the first form of the instruction, 
for clarity, but is not necessary.
\par\sb120
For details of the condition codes, see {\uldb section 
B.2.2}{\v section_b_2_2}.
\par\sb120
\page
#{\footnote section_b_4_129}
${\footnote B.4.129. JCXZ, JECXZ: Jump if CX/ECX Zero}
+{\footnote browse:00349}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote JCXZ;
JECXZ}
\keepn\f2\b\fs30\sb60\sa60
B.4.129. {\f1 JCXZ}, {\f1 JECXZ}: Jump if CX/ECX Zero
\par\pard\plain\sb120
\keep\f1\sb120
JCXZ imm                      ; a16 E3 rb            [8086] \par\sb0
JECXZ imm                     ; a32 E3 rb            [386]\par\sb0
\pard\f0\sb120
{\f1 JCXZ} performs a short jump (with maximum range 128 bytes) if and only 
if the contents of the {\f1 CX} register is 0. {\f1 JECXZ} does the same 
thing, but with {\f1 ECX}.
\par\sb120
\page
#{\footnote section_b_4_130}
${\footnote B.4.130. JMP: Jump}
+{\footnote browse:00350}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote far jump;
JMP;
near jump}
\keepn\f2\b\fs30\sb60\sa60
B.4.130. {\f1 JMP}: Jump
\par\pard\plain\sb120
\keep\f1\sb120
JMP imm                       ; E9 rw/rd             [8086] \par\sb0
JMP SHORT imm                 ; EB rb                [8086] \par\sb0
JMP imm:imm16                 ; o16 EA iw iw         [8086] \par\sb0
JMP imm:imm32                 ; o32 EA id iw         [386] \par\sb0
JMP FAR mem                   ; o16 FF /5            [8086] \par\sb0
JMP FAR mem32                 ; o32 FF /5            [386] \par\sb0
JMP r/m16                     ; o16 FF /4            [8086] \par\sb0
JMP r/m32                     ; o32 FF /4            [386]\par\sb0
\pard\f0\sb120
{\f1 JMP} jumps to a given address. The address may be specified as an 
absolute segment and offset, or as a relative jump within the current 
segment.
\par\sb120
{\f1 JMP\'A0SHORT\'A0imm} has a maximum range of 128 bytes, since the 
displacement is specified as only 8 bits, but takes up less code space. 
NASM does not choose when to generate {\f1 JMP\'A0SHORT} for you: you must 
explicitly code {\f1 SHORT} every time you want a short jump.
\par\sb120
You can choose between the two immediate far jump forms 
({\f1 JMP\'A0imm:imm}) by the use of the {\f1 WORD} and {\f1 DWORD} 
keywords: {\f1 JMP\'A0WORD\'A00x1234:0x5678}) or 
{\f1 JMP\'A0DWORD\'A00x1234:0x56789abc}.
\par\sb120
The {\f1 JMP\'A0FAR\'A0mem} forms execute a far jump by loading the 
destination address out of memory. The address loaded consists of 16 or 32 
bits of offset (depending on the operand size), and 16 bits of segment. The 
operand size may be overridden using {\f1 JMP\'A0WORD\'A0FAR\'A0mem} or 
{\f1 JMP\'A0DWORD\'A0FAR\'A0mem}.
\par\sb120
The {\f1 JMP\'A0r/m} forms execute a near jump (within the same segment), 
loading the destination address out of memory or out of a register. The 
keyword {\f1 NEAR} may be specified, for clarity, in these forms, but is 
not necessary. Again, operand size can be overridden using 
{\f1 JMP\'A0WORD\'A0mem} or {\f1 JMP\'A0DWORD\'A0mem}.
\par\sb120
As a convenience, NASM does not require you to jump to a far symbol by 
coding the cumbersome {\f1 JMP\'A0SEG\'A0routine:routine}, but instead 
allows the easier synonym {\f1 JMP\'A0FAR\'A0routine}.
\par\sb120
The {\f1 CALL\'A0r/m} forms given above are near calls; NASM will accept 
the {\f1 NEAR} keyword (e.g. {\f1 CALL\'A0NEAR\'A0[address]}), even though 
it is not strictly necessary.
\par\sb120
\page
#{\footnote section_b_4_131}
${\footnote B.4.131. LAHF: Load AH from Flags}
+{\footnote browse:00351}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LAHF}
\keepn\f2\b\fs30\sb60\sa60
B.4.131. {\f1 LAHF}: Load AH from Flags
\par\pard\plain\sb120
\keep\f1\sb120
LAHF                          ; 9F                   [8086]\par\sb0
\pard\f0\sb120
{\f1 LAHF} sets the {\f1 AH} register according to the contents of the low 
byte of the flags word.
\par\sb120
The operation of {\f1 LAHF} is:
\par\sb120
\keep\f1\sb120
 AH <-- SF:ZF:0:AF:0:PF:1:CF\par\sb0
\pard\f0\sb120
See also {\f1 SAHF} ({\uldb section B.4.282}{\v section_b_4_282}).
\par\sb120
\page
#{\footnote section_b_4_132}
${\footnote B.4.132. LAR: Load Access Rights}
+{\footnote browse:00352}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LAR}
\keepn\f2\b\fs30\sb60\sa60
B.4.132. {\f1 LAR}: Load Access Rights
\par\pard\plain\sb120
\keep\f1\sb120
LAR reg16,r/m16               ; o16 0F 02 /r         [286,PRIV] \par\sb0
LAR reg32,r/m32               ; o32 0F 02 /r         [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 LAR} takes the segment selector specified by its source (second) 
operand, finds the corresponding segment descriptor in the GDT or LDT, and 
loads the access-rights byte of the descriptor into its destination (first) 
operand.
\par\sb120
\page
#{\footnote section_b_4_133}
${\footnote B.4.133. LDMXCSR: Load Streaming SIMD Extension Control/Status}
+{\footnote browse:00353}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LDMXCSR}
\keepn\f2\b\fs30\sb60\sa60
B.4.133. {\f1 LDMXCSR}: Load Streaming SIMD Extension Control/Status
\par\pard\plain\sb120
\keep\f1\sb120
LDMXCSR mem32                 ; 0F AE /2        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 LDMXCSR} loads 32-bits of data from the specified memory location into 
the {\f1 MXCSR} control/status register. {\f1 MXCSR} is used to enable 
masked/unmasked exception handling, to set rounding modes, to set 
flush-to-zero mode, and to view exception status flags.
\par\sb120
For details of the {\f1 MXCSR} register, see the Intel processor docs.
\par\sb120
See also {\f1 STMXCSR} ({\uldb section B.4.302}{\v section_b_4_302}
\par\sb120
\page
#{\footnote section_b_4_134}
${\footnote B.4.134. LDS, LES, LFS, LGS, LSS: Load Far Pointer}
+{\footnote browse:00354}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LDS;
LES;
LFS;
LGS;
LSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.134. {\f1 LDS}, {\f1 LES}, {\f1 LFS}, {\f1 LGS}, {\f1 LSS}: Load Far Pointer
\par\pard\plain\sb120
\keep\f1\sb120
LDS reg16,mem                 ; o16 C5 /r            [8086] \par\sb0
LDS reg32,mem                 ; o32 C5 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
LES reg16,mem                 ; o16 C4 /r            [8086] \par\sb0
LES reg32,mem                 ; o32 C4 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
LFS reg16,mem                 ; o16 0F B4 /r         [386] \par\sb0
LFS reg32,mem                 ; o32 0F B4 /r         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
LGS reg16,mem                 ; o16 0F B5 /r         [386] \par\sb0
LGS reg32,mem                 ; o32 0F B5 /r         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
LSS reg16,mem                 ; o16 0F B2 /r         [386] \par\sb0
LSS reg32,mem                 ; o32 0F B2 /r         [386]\par\sb0
\pard\f0\sb120
These instructions load an entire far pointer (16 or 32 bits of offset, 
plus 16 bits of segment) out of memory in one go. {\f1 LDS}, for example, 
loads 16 or 32 bits from the given memory address into the given register 
(depending on the size of the register), then loads the {\i next} 16 bits 
from memory into {\f1 DS}. {\f1 LES}, {\f1 LFS}, {\f1 LGS} and {\f1 LSS} 
work in the same way but use the other segment registers.
\par\sb120
\page
#{\footnote section_b_4_135}
${\footnote B.4.135. LEA: Load Effective Address}
+{\footnote browse:00355}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LEA}
\keepn\f2\b\fs30\sb60\sa60
B.4.135. {\f1 LEA}: Load Effective Address
\par\pard\plain\sb120
\keep\f1\sb120
LEA reg16,mem                 ; o16 8D /r            [8086] \par\sb0
LEA reg32,mem                 ; o32 8D /r            [386]\par\sb0
\pard\f0\sb120
{\f1 LEA}, despite its syntax, does not access memory. It calculates the 
effective address specified by its second operand as if it were going to 
load or store data from it, but instead it stores the calculated address 
into the register specified by its first operand. This can be used to 
perform quite complex calculations (e.g. {\f1 LEA\'A0EAX,[EBX+ECX*4+100]}) 
in one instruction.
\par\sb120
{\f1 LEA}, despite being a purely arithmetic instruction which accesses no 
memory, still requires square brackets around its second operand, as if it 
were a memory reference.
\par\sb120
The size of the calculation is the current {\i address} size, and the size 
that the result is stored as is the current {\i operand} size. If the 
address and operand size are not the same, then if the addressing mode was 
32-bits, the low 16-bits are stored, and if the address was 16-bits, it is 
zero-extended to 32-bits before storing.
\par\sb120
\page
#{\footnote section_b_4_136}
${\footnote B.4.136. LEAVE: Destroy Stack Frame}
+{\footnote browse:00356}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LEAVE}
\keepn\f2\b\fs30\sb60\sa60
B.4.136. {\f1 LEAVE}: Destroy Stack Frame
\par\pard\plain\sb120
\keep\f1\sb120
LEAVE                         ; C9                   [186]\par\sb0
\pard\f0\sb120
{\f1 LEAVE} destroys a stack frame of the form created by the {\f1 ENTER} 
instruction (see {\uldb section B.4.65}{\v section_b_4_65}). It is 
functionally equivalent to {\f1 MOV\'A0ESP,EBP} followed by 
{\f1 POP\'A0EBP} (or {\f1 MOV\'A0SP,BP} followed by {\f1 POP\'A0BP} in 
16-bit mode).
\par\sb120
\page
#{\footnote section_b_4_137}
${\footnote B.4.137. LFENCE: Load Fence}
+{\footnote browse:00357}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LFENCE}
\keepn\f2\b\fs30\sb60\sa60
B.4.137. {\f1 LFENCE}: Load Fence
\par\pard\plain\sb120
\keep\f1\sb120
LFENCE                        ; 0F AE /5        [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 LFENCE} performs a serialising operation on all loads from memory that 
were issued before the {\f1 LFENCE} instruction. This guarantees that all 
memory reads before the {\f1 LFENCE} instruction are visible before any 
reads after the {\f1 LFENCE} instruction.
\par\sb120
{\f1 LFENCE} is ordered respective to other {\f1 LFENCE} instruction, 
{\f1 MFENCE}, any memory read and any other serialising instruction (such 
as {\f1 CPUID}).
\par\sb120
Weakly ordered memory types can be used to achieve higher processor 
performance through such techniques as out-of-order issue and speculative 
reads. The degree to which a consumer of data recognizes or knows that the 
data is weakly ordered varies among applications and may be unknown to the 
producer of this data. The {\f1 LFENCE} instruction provides a 
performance-efficient way of ensuring load ordering between routines that 
produce weakly-ordered results and routines that consume that data.
\par\sb120
{\f1 LFENCE} uses the following ModRM encoding:
\par\sb120
\keep\f1\sb120
          Mod (7:6)        = 11B \par\sb0
          Reg/Opcode (5:3) = 101B \par\sb0
          R/M (2:0)        = 000B\par\sb0
\pard\f0\sb120
All other ModRM encodings are defined to be reserved, and use of these 
encodings risks incompatibility with future processors.
\par\sb120
See also {\f1 SFENCE} ({\uldb section B.4.288}{\v section_b_4_288}) and 
{\f1 MFENCE} ({\uldb section B.4.151}{\v section_b_4_151}).
\par\sb120
\page
#{\footnote section_b_4_138}
${\footnote B.4.138. LGDT, LIDT, LLDT: Load Descriptor Tables}
+{\footnote browse:00358}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LGDT;
LIDT;
LLDT}
\keepn\f2\b\fs30\sb60\sa60
B.4.138. {\f1 LGDT}, {\f1 LIDT}, {\f1 LLDT}: Load Descriptor Tables
\par\pard\plain\sb120
\keep\f1\sb120
LGDT mem                      ; 0F 01 /2             [286,PRIV] \par\sb0
LIDT mem                      ; 0F 01 /3             [286,PRIV] \par\sb0
LLDT r/m16                    ; 0F 00 /2             [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 LGDT} and {\f1 LIDT} both take a 6-byte memory area as an operand: 
they load a 32-bit linear address and a 16-bit size limit from that area 
(in the opposite order) into the {\f1 GDTR} (global descriptor table 
register) or {\f1 IDTR} (interrupt descriptor table register). These are 
the only instructions which directly use {\i linear} addresses, rather than 
segment/offset pairs.
\par\sb120
{\f1 LLDT} takes a segment selector as an operand. The processor looks up 
that selector in the GDT and stores the limit and base address given there 
into the {\f1 LDTR} (local descriptor table register).
\par\sb120
See also {\f1 SGDT}, {\f1 SIDT} and {\f1 SLDT} ({\uldb section 
B.4.289}{\v section_b_4_289}).
\par\sb120
\page
#{\footnote section_b_4_139}
${\footnote B.4.139. LMSW: Load/Store Machine Status Word}
+{\footnote browse:00359}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LMSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.139. {\f1 LMSW}: Load/Store Machine Status Word
\par\pard\plain\sb120
\keep\f1\sb120
LMSW r/m16                    ; 0F 01 /6             [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 LMSW} loads the bottom four bits of the source operand into the bottom 
four bits of the {\f1 CR0} control register (or the Machine Status Word, on 
286 processors). See also {\f1 SMSW} ({\uldb section 
B.4.296}{\v section_b_4_296}).
\par\sb120
\page
#{\footnote section_b_4_140}
${\footnote B.4.140. LOADALL, LOADALL286: Load Processor State}
+{\footnote browse:00360}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LOADALL;
LOADALL286}
\keepn\f2\b\fs30\sb60\sa60
B.4.140. {\f1 LOADALL}, {\f1 LOADALL286}: Load Processor State
\par\pard\plain\sb120
\keep\f1\sb120
LOADALL                       ; 0F 07                [386,UNDOC] \par\sb0
LOADALL286                    ; 0F 05                [286,UNDOC]\par\sb0
\pard\f0\sb120
This instruction, in its two different-opcode forms, is apparently 
supported on most 286 processors, some 386 and possibly some 486. The 
opcode differs between the 286 and the 386.
\par\sb120
The function of the instruction is to load all information relating to the 
state of the processor out of a block of memory: on the 286, this block is 
located implicitly at absolute address {\f1 0x800}, and on the 386 and 486 
it is at {\f1 [ES:EDI]}.
\par\sb120
\page
#{\footnote section_b_4_141}
${\footnote B.4.141. LODSB, LODSW, LODSD: Load from String}
+{\footnote browse:00361}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
LODSB;
LODSD;
LODSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.141. {\f1 LODSB}, {\f1 LODSW}, {\f1 LODSD}: Load from String
\par\pard\plain\sb120
\keep\f1\sb120
LODSB                         ; AC                   [8086] \par\sb0
LODSW                         ; o16 AD               [8086] \par\sb0
LODSD                         ; o32 AD               [386]\par\sb0
\pard\f0\sb120
{\f1 LODSB} loads a byte from {\f1 [DS:SI]} or {\f1 [DS:ESI]} into 
{\f1 AL}. It then increments or decrements (depending on the direction 
flag: increments if the flag is clear, decrements if it is set) {\f1 SI} or 
{\f1 ESI}.
\par\sb120
The register used is {\f1 SI} if the address size is 16 bits, and {\f1 ESI} 
if it is 32 bits. If you need to use an address size not equal to the 
current {\f1 BITS} setting, you can use an explicit {\f1 a16} or {\f1 a32} 
prefix.
\par\sb120
The segment register used to load from {\f1 [SI]} or {\f1 [ESI]} can be 
overridden by using a segment register name as a prefix (for example, 
{\f1 ES\'A0LODSB}).
\par\sb120
{\f1 LODSW} and {\f1 LODSD} work in the same way, but they load a word or a 
doubleword instead of a byte, and increment or decrement the addressing 
registers by 2 or 4 instead of 1.
\par\sb120
\page
#{\footnote section_b_4_142}
${\footnote B.4.142. LOOP, LOOPE, LOOPZ, LOOPNE, LOOPNZ: Loop with Counter}
+{\footnote browse:00362}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LOOP;
LOOPE;
LOOPNE;
LOOPNZ;
LOOPZ}
\keepn\f2\b\fs30\sb60\sa60
B.4.142. {\f1 LOOP}, {\f1 LOOPE}, {\f1 LOOPZ}, {\f1 LOOPNE}, {\f1 LOOPNZ}: Loop with Counter
\par\pard\plain\sb120
\keep\f1\sb120
LOOP imm                      ; E2 rb                [8086] \par\sb0
LOOP imm,CX                   ; a16 E2 rb            [8086] \par\sb0
LOOP imm,ECX                  ; a32 E2 rb            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
LOOPE imm                     ; E1 rb                [8086] \par\sb0
LOOPE imm,CX                  ; a16 E1 rb            [8086] \par\sb0
LOOPE imm,ECX                 ; a32 E1 rb            [386] \par\sb0
LOOPZ imm                     ; E1 rb                [8086] \par\sb0
LOOPZ imm,CX                  ; a16 E1 rb            [8086] \par\sb0
LOOPZ imm,ECX                 ; a32 E1 rb            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
LOOPNE imm                    ; E0 rb                [8086] \par\sb0
LOOPNE imm,CX                 ; a16 E0 rb            [8086] \par\sb0
LOOPNE imm,ECX                ; a32 E0 rb            [386] \par\sb0
LOOPNZ imm                    ; E0 rb                [8086] \par\sb0
LOOPNZ imm,CX                 ; a16 E0 rb            [8086] \par\sb0
LOOPNZ imm,ECX                ; a32 E0 rb            [386]\par\sb0
\pard\f0\sb120
{\f1 LOOP} decrements its counter register (either {\f1 CX} or {\f1 ECX} 
\'96 if one is not specified explicitly, the {\f1 BITS} setting dictates 
which is used) by one, and if the counter does not become zero as a result 
of this operation, it jumps to the given label. The jump has a range of 128 
bytes.
\par\sb120
{\f1 LOOPE} (or its synonym {\f1 LOOPZ}) adds the additional condition that 
it only jumps if the counter is nonzero {\i and} the zero flag is set. 
Similarly, {\f1 LOOPNE} (and {\f1 LOOPNZ}) jumps only if the counter is 
nonzero and the zero flag is clear.
\par\sb120
\page
#{\footnote section_b_4_143}
${\footnote B.4.143. LSL: Load Segment Limit}
+{\footnote browse:00363}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LSL}
\keepn\f2\b\fs30\sb60\sa60
B.4.143. {\f1 LSL}: Load Segment Limit
\par\pard\plain\sb120
\keep\f1\sb120
LSL reg16,r/m16               ; o16 0F 03 /r         [286,PRIV] \par\sb0
LSL reg32,r/m32               ; o32 0F 03 /r         [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 LSL} is given a segment selector in its source (second) operand; it 
computes the segment limit value by loading the segment limit field from 
the associated segment descriptor in the {\f1 GDT} or {\f1 LDT}. (This 
involves shifting left by 12 bits if the segment limit is page-granular, 
and not if it is byte-granular; so you end up with a byte limit in either 
case.) The segment limit obtained is then loaded into the destination 
(first) operand.
\par\sb120
\page
#{\footnote section_b_4_144}
${\footnote B.4.144. LTR: Load Task Register}
+{\footnote browse:00364}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote LTR}
\keepn\f2\b\fs30\sb60\sa60
B.4.144. {\f1 LTR}: Load Task Register
\par\pard\plain\sb120
\keep\f1\sb120
LTR r/m16                     ; 0F 00 /3             [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 LTR} looks up the segment base and limit in the GDT or LDT descriptor 
specified by the segment selector given as its operand, and loads them into 
the Task Register.
\par\sb120
\page
#{\footnote section_b_4_145}
${\footnote B.4.145. MASKMOVDQU: Byte Mask Write}
+{\footnote browse:00365}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MASKMOVDQU}
\keepn\f2\b\fs30\sb60\sa60
B.4.145. {\f1 MASKMOVDQU}: Byte Mask Write
\par\pard\plain\sb120
\keep\f1\sb120
MASKMOVDQU xmm1,xmm2          ; 66 0F F7 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MASKMOVDQU} stores data from xmm1 to the location specified by 
{\f1 ES:(E)DI}. The size of the store depends on the address-size 
attribute. The most significant bit in each byte of the mask register xmm2 
is used to selectively write the data (0 = no write, 1 = write) on a 
per-byte basis.
\par\sb120
\page
#{\footnote section_b_4_146}
${\footnote B.4.146. MASKMOVQ: Byte Mask Write}
+{\footnote browse:00366}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MASKMOVQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.146. {\f1 MASKMOVQ}: Byte Mask Write
\par\pard\plain\sb120
\keep\f1\sb120
MASKMOVQ mm1,mm2              ; 0F F7 /r        [KATMAI,MMX]\par\sb0
\pard\f0\sb120
{\f1 MASKMOVQ} stores data from mm1 to the location specified by 
{\f1 ES:(E)DI}. The size of the store depends on the address-size 
attribute. The most significant bit in each byte of the mask register mm2 
is used to selectively write the data (0 = no write, 1 = write) on a 
per-byte basis.
\par\sb120
\page
#{\footnote section_b_4_147}
${\footnote B.4.147. MAXPD: Return Packed Double-Precision FP Maximum}
+{\footnote browse:00367}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MAXPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.147. {\f1 MAXPD}: Return Packed Double-Precision FP Maximum
\par\pard\plain\sb120
\keep\f1\sb120
MAXPD xmm1,xmm2/m128          ; 66 0F 5F /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MAXPD} performs a SIMD compare of the packed double-precision FP 
numbers from xmm1 and xmm2/mem, and stores the maximum values of each pair 
of values in xmm1. If the values being compared are both zeroes, source2 
(xmm2/m128) would be returned. If source2 (xmm2/m128) is an SNaN, this SNaN 
is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN 
is not returned).
\par\sb120
\page
#{\footnote section_b_4_148}
${\footnote B.4.148. MAXPS: Return Packed Single-Precision FP Maximum}
+{\footnote browse:00368}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MAXPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.148. {\f1 MAXPS}: Return Packed Single-Precision FP Maximum
\par\pard\plain\sb120
\keep\f1\sb120
MAXPS xmm1,xmm2/m128          ; 0F 5F /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MAXPS} performs a SIMD compare of the packed single-precision FP 
numbers from xmm1 and xmm2/mem, and stores the maximum values of each pair 
of values in xmm1. If the values being compared are both zeroes, source2 
(xmm2/m128) would be returned. If source2 (xmm2/m128) is an SNaN, this SNaN 
is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN 
is not returned).
\par\sb120
\page
#{\footnote section_b_4_149}
${\footnote B.4.149. MAXSD: Return Scalar Double-Precision FP Maximum}
+{\footnote browse:00369}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MAXSD}
\keepn\f2\b\fs30\sb60\sa60
B.4.149. {\f1 MAXSD}: Return Scalar Double-Precision FP Maximum
\par\pard\plain\sb120
\keep\f1\sb120
MAXSD xmm1,xmm2/m64           ; F2 0F 5F /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MAXSD} compares the low-order double-precision FP numbers from xmm1 
and xmm2/mem, and stores the maximum value in xmm1. If the values being 
compared are both zeroes, source2 (xmm2/m64) would be returned. If source2 
(xmm2/m64) is an SNaN, this SNaN is forwarded unchanged to the destination 
(i.e., a QNaN version of the SNaN is not returned). The high quadword of 
the destination is left unchanged.
\par\sb120
\page
#{\footnote section_b_4_150}
${\footnote B.4.150. MAXSS: Return Scalar Single-Precision FP Maximum}
+{\footnote browse:00370}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MAXSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.150. {\f1 MAXSS}: Return Scalar Single-Precision FP Maximum
\par\pard\plain\sb120
\keep\f1\sb120
MAXSS xmm1,xmm2/m32           ; F3 0F 5F /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MAXSS} compares the low-order single-precision FP numbers from xmm1 
and xmm2/mem, and stores the maximum value in xmm1. If the values being 
compared are both zeroes, source2 (xmm2/m32) would be returned. If source2 
(xmm2/m32) is an SNaN, this SNaN is forwarded unchanged to the destination 
(i.e., a QNaN version of the SNaN is not returned). The high three 
doublewords of the destination are left unchanged.
\par\sb120
\page
#{\footnote section_b_4_151}
${\footnote B.4.151. MFENCE: Memory Fence}
+{\footnote browse:00371}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MFENCE}
\keepn\f2\b\fs30\sb60\sa60
B.4.151. {\f1 MFENCE}: Memory Fence
\par\pard\plain\sb120
\keep\f1\sb120
MFENCE                        ; 0F AE /6        [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MFENCE} performs a serialising operation on all loads from memory and 
writes to memory that were issued before the {\f1 MFENCE} instruction. This 
guarantees that all memory reads and writes before the {\f1 MFENCE} 
instruction are completed before any reads and writes after the 
{\f1 MFENCE} instruction.
\par\sb120
{\f1 MFENCE} is ordered respective to other {\f1 MFENCE} instructions, 
{\f1 LFENCE}, {\f1 SFENCE}, any memory read and any other serialising 
instruction (such as {\f1 CPUID}).
\par\sb120
Weakly ordered memory types can be used to achieve higher processor 
performance through such techniques as out-of-order issue, speculative 
reads, write-combining, and write-collapsing. The degree to which a 
consumer of data recognizes or knows that the data is weakly ordered varies 
among applications and may be unknown to the producer of this data. The 
{\f1 MFENCE} instruction provides a performance-efficient way of ensuring 
load and store ordering between routines that produce weakly-ordered 
results and routines that consume that data.
\par\sb120
{\f1 MFENCE} uses the following ModRM encoding:
\par\sb120
\keep\f1\sb120
          Mod (7:6)        = 11B \par\sb0
          Reg/Opcode (5:3) = 110B \par\sb0
          R/M (2:0)        = 000B\par\sb0
\pard\f0\sb120
All other ModRM encodings are defined to be reserved, and use of these 
encodings risks incompatibility with future processors.
\par\sb120
See also {\f1 LFENCE} ({\uldb section B.4.137}{\v section_b_4_137}) and 
{\f1 SFENCE} ({\uldb section B.4.288}{\v section_b_4_288}).
\par\sb120
\page
#{\footnote section_b_4_152}
${\footnote B.4.152. MINPD: Return Packed Double-Precision FP Minimum}
+{\footnote browse:00372}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MINPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.152. {\f1 MINPD}: Return Packed Double-Precision FP Minimum
\par\pard\plain\sb120
\keep\f1\sb120
MINPD xmm1,xmm2/m128          ; 66 0F 5D /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MINPD} performs a SIMD compare of the packed double-precision FP 
numbers from xmm1 and xmm2/mem, and stores the minimum values of each pair 
of values in xmm1. If the values being compared are both zeroes, source2 
(xmm2/m128) would be returned. If source2 (xmm2/m128) is an SNaN, this SNaN 
is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN 
is not returned).
\par\sb120
\page
#{\footnote section_b_4_153}
${\footnote B.4.153. MINPS: Return Packed Single-Precision FP Minimum}
+{\footnote browse:00373}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MINPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.153. {\f1 MINPS}: Return Packed Single-Precision FP Minimum
\par\pard\plain\sb120
\keep\f1\sb120
MINPS xmm1,xmm2/m128          ; 0F 5D /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MINPS} performs a SIMD compare of the packed single-precision FP 
numbers from xmm1 and xmm2/mem, and stores the minimum values of each pair 
of values in xmm1. If the values being compared are both zeroes, source2 
(xmm2/m128) would be returned. If source2 (xmm2/m128) is an SNaN, this SNaN 
is forwarded unchanged to the destination (i.e., a QNaN version of the SNaN 
is not returned).
\par\sb120
\page
#{\footnote section_b_4_154}
${\footnote B.4.154. MINSD: Return Scalar Double-Precision FP Minimum}
+{\footnote browse:00374}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MINSD}
\keepn\f2\b\fs30\sb60\sa60
B.4.154. {\f1 MINSD}: Return Scalar Double-Precision FP Minimum
\par\pard\plain\sb120
\keep\f1\sb120
MINSD xmm1,xmm2/m64           ; F2 0F 5D /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MINSD} compares the low-order double-precision FP numbers from xmm1 
and xmm2/mem, and stores the minimum value in xmm1. If the values being 
compared are both zeroes, source2 (xmm2/m64) would be returned. If source2 
(xmm2/m64) is an SNaN, this SNaN is forwarded unchanged to the destination 
(i.e., a QNaN version of the SNaN is not returned). The high quadword of 
the destination is left unchanged.
\par\sb120
\page
#{\footnote section_b_4_155}
${\footnote B.4.155. MINSS: Return Scalar Single-Precision FP Minimum}
+{\footnote browse:00375}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MINSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.155. {\f1 MINSS}: Return Scalar Single-Precision FP Minimum
\par\pard\plain\sb120
\keep\f1\sb120
MINSS xmm1,xmm2/m32           ; F3 0F 5D /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MINSS} compares the low-order single-precision FP numbers from xmm1 
and xmm2/mem, and stores the minimum value in xmm1. If the values being 
compared are both zeroes, source2 (xmm2/m32) would be returned. If source2 
(xmm2/m32) is an SNaN, this SNaN is forwarded unchanged to the destination 
(i.e., a QNaN version of the SNaN is not returned). The high three 
doublewords of the destination are left unchanged.
\par\sb120
\page
#{\footnote section_b_4_156}
${\footnote B.4.156. MOV: Move Data}
+{\footnote browse:00376}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOV}
\keepn\f2\b\fs30\sb60\sa60
B.4.156. {\f1 MOV}: Move Data
\par\pard\plain\sb120
\keep\f1\sb120
MOV r/m8,reg8                 ; 88 /r                [8086] \par\sb0
MOV r/m16,reg16               ; o16 89 /r            [8086] \par\sb0
MOV r/m32,reg32               ; o32 89 /r            [386] \par\sb0
MOV reg8,r/m8                 ; 8A /r                [8086] \par\sb0
MOV reg16,r/m16               ; o16 8B /r            [8086] \par\sb0
MOV reg32,r/m32               ; o32 8B /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
MOV reg8,imm8                 ; B0+r ib              [8086] \par\sb0
MOV reg16,imm16               ; o16 B8+r iw          [8086] \par\sb0
MOV reg32,imm32               ; o32 B8+r id          [386] \par\sb0
MOV r/m8,imm8                 ; C6 /0 ib             [8086] \par\sb0
MOV r/m16,imm16               ; o16 C7 /0 iw         [8086] \par\sb0
MOV r/m32,imm32               ; o32 C7 /0 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
MOV AL,memoffs8               ; A0 ow/od             [8086] \par\sb0
MOV AX,memoffs16              ; o16 A1 ow/od         [8086] \par\sb0
MOV EAX,memoffs32             ; o32 A1 ow/od         [386] \par\sb0
MOV memoffs8,AL               ; A2 ow/od             [8086] \par\sb0
MOV memoffs16,AX              ; o16 A3 ow/od         [8086] \par\sb0
MOV memoffs32,EAX             ; o32 A3 ow/od         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
MOV r/m16,segreg              ; o16 8C /r            [8086] \par\sb0
MOV r/m32,segreg              ; o32 8C /r            [386] \par\sb0
MOV segreg,r/m16              ; o16 8E /r            [8086] \par\sb0
MOV segreg,r/m32              ; o32 8E /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
MOV reg32,CR0/2/3/4           ; 0F 20 /r             [386] \par\sb0
MOV reg32,DR0/1/2/3/6/7       ; 0F 21 /r             [386] \par\sb0
MOV reg32,TR3/4/5/6/7         ; 0F 24 /r             [386] \par\sb0
MOV CR0/2/3/4,reg32           ; 0F 22 /r             [386] \par\sb0
MOV DR0/1/2/3/6/7,reg32       ; 0F 23 /r             [386] \par\sb0
MOV TR3/4/5/6/7,reg32         ; 0F 26 /r             [386]\par\sb0
\pard\f0\sb120
{\f1 MOV} copies the contents of its source (second) operand into its 
destination (first) operand.
\par\sb120
In all forms of the {\f1 MOV} instruction, the two operands are the same 
size, except for moving between a segment register and an {\f1 r/m32} 
operand. These instructions are treated exactly like the corresponding 
16-bit equivalent (so that, for example, {\f1 MOV\'A0DS,EAX} functions 
identically to {\f1 MOV\'A0DS,AX} but saves a prefix when in 32-bit mode), 
except that when a segment register is moved into a 32-bit destination, the 
top two bytes of the result are undefined.
\par\sb120
{\f1 MOV} may not use {\f1 CS} as a destination.
\par\sb120
{\f1 CR4} is only a supported register on the Pentium and above.
\par\sb120
Test registers are supported on 386/486 processors and on some non-Intel 
Pentium class processors.
\par\sb120
\page
#{\footnote section_b_4_157}
${\footnote B.4.157. MOVAPD: Move Aligned Packed Double-Precision FP Values}
+{\footnote browse:00377}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVAPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.157. {\f1 MOVAPD}: Move Aligned Packed Double-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
MOVAPD xmm1,xmm2/mem128       ; 66 0F 28 /r     [WILLAMETTE,SSE2] \par\sb0
MOVAPD xmm1/mem128,xmm2       ; 66 0F 29 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVAPD} moves a double quadword containing 2 packed double-precision 
FP values from the source operand to the destination. When the source or 
destination operand is a memory location, it must be aligned on a 16-byte 
boundary.
\par\sb120
To move data in and out of memory locations that are not known to be on 
16-byte boundaries, use the {\f1 MOVUPD} instruction ({\uldb section 
B.4.182}{\v section_b_4_182}).
\par\sb120
\page
#{\footnote section_b_4_158}
${\footnote B.4.158. MOVAPS: Move Aligned Packed Single-Precision FP Values}
+{\footnote browse:00378}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVAPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.158. {\f1 MOVAPS}: Move Aligned Packed Single-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
MOVAPS xmm1,xmm2/mem128       ; 0F 28 /r        [KATMAI,SSE] \par\sb0
MOVAPS xmm1/mem128,xmm2       ; 0F 29 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVAPS} moves a double quadword containing 4 packed single-precision 
FP values from the source operand to the destination. When the source or 
destination operand is a memory location, it must be aligned on a 16-byte 
boundary.
\par\sb120
To move data in and out of memory locations that are not known to be on 
16-byte boundaries, use the {\f1 MOVUPS} instruction ({\uldb section 
B.4.183}{\v section_b_4_183}).
\par\sb120
\page
#{\footnote section_b_4_159}
${\footnote B.4.159. MOVD: Move Doubleword to/from MMX Register}
+{\footnote browse:00379}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVD}
\keepn\f2\b\fs30\sb60\sa60
B.4.159. {\f1 MOVD}: Move Doubleword to/from MMX Register
\par\pard\plain\sb120
\keep\f1\sb120
MOVD mm,r/m32                 ; 0F 6E /r             [PENT,MMX] \par\sb0
MOVD r/m32,mm                 ; 0F 7E /r             [PENT,MMX] \par\sb0
MOVD xmm,r/m32                ; 66 0F 6E /r     [WILLAMETTE,SSE2] \par\sb0
MOVD r/m32,xmm                ; 66 0F 7E /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVD} copies 32 bits from its source (second) operand into its 
destination (first) operand. When the destination is a 64-bit {\f1 MMX} 
register or a 128-bit {\f1 XMM} register, the input value is zero-extended 
to fill the destination register.
\par\sb120
\page
#{\footnote section_b_4_160}
${\footnote B.4.160. MOVDQ2Q: Move Quadword from XMM to MMX register.}
+{\footnote browse:00380}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVDQ2Q}
\keepn\f2\b\fs30\sb60\sa60
B.4.160. {\f1 MOVDQ2Q}: Move Quadword from XMM to MMX register.
\par\pard\plain\sb120
\keep\f1\sb120
MOVDQ2Q mm,xmm                ; F2 OF D6 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVDQ2Q} moves the low quadword from the source operand to the 
destination operand.
\par\sb120
\page
#{\footnote section_b_4_161}
${\footnote B.4.161. MOVDQA: Move Aligned Double Quadword}
+{\footnote browse:00381}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVDQA}
\keepn\f2\b\fs30\sb60\sa60
B.4.161. {\f1 MOVDQA}: Move Aligned Double Quadword
\par\pard\plain\sb120
\keep\f1\sb120
MOVDQA xmm1,xmm2/m128         ; 66 OF 6F /r     [WILLAMETTE,SSE2] \par\sb0
MOVDQA xmm1/m128,xmm2         ; 66 OF 7F /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVDQA} moves a double quadword from the source operand to the 
destination operand. When the source or destination operand is a memory 
location, it must be aligned to a 16-byte boundary.
\par\sb120
To move a double quadword to or from unaligned memory locations, use the 
{\f1 MOVDQU} instruction ({\uldb section B.4.162}{\v section_b_4_162}).
\par\sb120
\page
#{\footnote section_b_4_162}
${\footnote B.4.162. MOVDQU: Move Unaligned Double Quadword}
+{\footnote browse:00382}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVDQU}
\keepn\f2\b\fs30\sb60\sa60
B.4.162. {\f1 MOVDQU}: Move Unaligned Double Quadword
\par\pard\plain\sb120
\keep\f1\sb120
MOVDQU xmm1,xmm2/m128         ; F3 OF 6F /r     [WILLAMETTE,SSE2] \par\sb0
MOVDQU xmm1/m128,xmm2         ; F3 OF 7F /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVDQU} moves a double quadword from the source operand to the 
destination operand. When the source or destination operand is a memory 
location, the memory may be unaligned.
\par\sb120
To move a double quadword to or from known aligned memory locations, use 
the {\f1 MOVDQA} instruction ({\uldb section B.4.161}{\v section_b_4_161}).
\par\sb120
\page
#{\footnote section_b_4_163}
${\footnote B.4.163. MOVHLPS: Move Packed Single-Precision FP High to Low}
+{\footnote browse:00383}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVHLPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.163. {\f1 MOVHLPS}: Move Packed Single-Precision FP High to Low
\par\pard\plain\sb120
\keep\f1\sb120
MOVHLPS xmm1,xmm2             ; OF 12 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVHLPS} moves the two packed single-precision FP values from the high 
quadword of the source register xmm2 to the low quadword of the destination 
register, xmm2. The upper quadword of xmm1 is left unchanged.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[0-63]   := src[64-127], \par\sb0
   dst[64-127] remains unchanged.\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_164}
${\footnote B.4.164. MOVHPD: Move High Packed Double-Precision FP}
+{\footnote browse:00384}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVHPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.164. {\f1 MOVHPD}: Move High Packed Double-Precision FP
\par\pard\plain\sb120
\keep\f1\sb120
MOVHPD xmm,m64               ; 66 OF 16 /r      [WILLAMETTE,SSE2] \par\sb0
MOVHPD m64,xmm               ; 66 OF 17 /r      [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVHPD} moves a double-precision FP value between the source and 
destination operands. One of the operands is a 64-bit memory location, the 
other is the high quadword of an {\f1 XMM} register.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   mem[0-63]   := xmm[64-127];\par\sb0
\pard\f0\sb120
or
\par\sb120
\keep\f1\sb120
   xmm[0-63]   remains unchanged; \par\sb0
   xmm[64-127] := mem[0-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_165}
${\footnote B.4.165. MOVHPS: Move High Packed Single-Precision FP}
+{\footnote browse:00385}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVHPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.165. {\f1 MOVHPS}: Move High Packed Single-Precision FP
\par\pard\plain\sb120
\keep\f1\sb120
MOVHPS xmm,m64               ; 0F 16 /r         [KATMAI,SSE] \par\sb0
MOVHPS m64,xmm               ; 0F 17 /r         [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVHPS} moves two packed single-precision FP values between the source 
and destination operands. One of the operands is a 64-bit memory location, 
the other is the high quadword of an {\f1 XMM} register.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   mem[0-63]   := xmm[64-127];\par\sb0
\pard\f0\sb120
or
\par\sb120
\keep\f1\sb120
   xmm[0-63]   remains unchanged; \par\sb0
   xmm[64-127] := mem[0-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_166}
${\footnote B.4.166. MOVLHPS: Move Packed Single-Precision FP Low to High}
+{\footnote browse:00386}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVLHPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.166. {\f1 MOVLHPS}: Move Packed Single-Precision FP Low to High
\par\pard\plain\sb120
\keep\f1\sb120
MOVLHPS xmm1,xmm2             ; OF 16 /r         [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVLHPS} moves the two packed single-precision FP values from the low 
quadword of the source register xmm2 to the high quadword of the 
destination register, xmm2. The low quadword of xmm1 is left unchanged.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[0-63]   remains unchanged; \par\sb0
   dst[64-127] := src[0-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_167}
${\footnote B.4.167. MOVLPD: Move Low Packed Double-Precision FP}
+{\footnote browse:00387}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVLPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.167. {\f1 MOVLPD}: Move Low Packed Double-Precision FP
\par\pard\plain\sb120
\keep\f1\sb120
MOVLPD xmm,m64                ; 66 OF 12 /r     [WILLAMETTE,SSE2] \par\sb0
MOVLPD m64,xmm                ; 66 OF 13 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVLPD} moves a double-precision FP value between the source and 
destination operands. One of the operands is a 64-bit memory location, the 
other is the low quadword of an {\f1 XMM} register.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   mem(0-63)   := xmm(0-63);\par\sb0
\pard\f0\sb120
or
\par\sb120
\keep\f1\sb120
   xmm(0-63)   := mem(0-63); \par\sb0
   xmm(64-127) remains unchanged.\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_168}
${\footnote B.4.168. MOVLPS: Move Low Packed Single-Precision FP}
+{\footnote browse:00388}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVLPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.168. {\f1 MOVLPS}: Move Low Packed Single-Precision FP
\par\pard\plain\sb120
\keep\f1\sb120
MOVLPS xmm,m64                ; OF 12 /r        [KATMAI,SSE] \par\sb0
MOVLPS m64,xmm                ; OF 13 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVLPS} moves two packed single-precision FP values between the source 
and destination operands. One of the operands is a 64-bit memory location, 
the other is the low quadword of an {\f1 XMM} register.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   mem(0-63)   := xmm(0-63);\par\sb0
\pard\f0\sb120
or
\par\sb120
\keep\f1\sb120
   xmm(0-63)   := mem(0-63); \par\sb0
   xmm(64-127) remains unchanged.\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_169}
${\footnote B.4.169. MOVMSKPD: Extract Packed Double-Precision FP Sign Mask}
+{\footnote browse:00389}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVMSKPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.169. {\f1 MOVMSKPD}: Extract Packed Double-Precision FP Sign Mask
\par\pard\plain\sb120
\keep\f1\sb120
MOVMSKPD reg32,xmm              ; 66 0F 50 /r   [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVMSKPD} inserts a 2-bit mask in r32, formed of the most significant 
bits of each double-precision FP number of the source operand.
\par\sb120
\page
#{\footnote section_b_4_170}
${\footnote B.4.170. MOVMSKPS: Extract Packed Single-Precision FP Sign Mask}
+{\footnote browse:00390}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVMSKPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.170. {\f1 MOVMSKPS}: Extract Packed Single-Precision FP Sign Mask
\par\pard\plain\sb120
\keep\f1\sb120
MOVMSKPS reg32,xmm              ; 0F 50 /r      [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVMSKPS} inserts a 4-bit mask in r32, formed of the most significant 
bits of each single-precision FP number of the source operand.
\par\sb120
\page
#{\footnote section_b_4_171}
${\footnote B.4.171. MOVNTDQ: Move Double Quadword Non Temporal}
+{\footnote browse:00391}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVNTDQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.171. {\f1 MOVNTDQ}: Move Double Quadword Non Temporal
\par\pard\plain\sb120
\keep\f1\sb120
MOVNTDQ m128,xmm              ; 66 0F E7 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVNTDQ} moves the double quadword from the {\f1 XMM} source register 
to the destination memory location, using a non-temporal hint. This store 
instruction minimizes cache pollution.
\par\sb120
\page
#{\footnote section_b_4_172}
${\footnote B.4.172. MOVNTI: Move Doubleword Non Temporal}
+{\footnote browse:00392}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVNTI}
\keepn\f2\b\fs30\sb60\sa60
B.4.172. {\f1 MOVNTI}: Move Doubleword Non Temporal
\par\pard\plain\sb120
\keep\f1\sb120
MOVNTI m32,reg32              ; 0F C3 /r        [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVNTI} moves the doubleword in the source register to the destination 
memory location, using a non-temporal hint. This store instruction 
minimizes cache pollution.
\par\sb120
\page
#{\footnote section_b_4_173}
${\footnote B.4.173. MOVNTPD: Move Aligned Four Packed Single-Precision FP Values Non Temporal}
+{\footnote browse:00393}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVNTPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.173. {\f1 MOVNTPD}: Move Aligned Four Packed Single-Precision FP Values Non Temporal
\par\pard\plain\sb120
\keep\f1\sb120
MOVNTPD m128,xmm              ; 66 0F 2B /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVNTPD} moves the double quadword from the {\f1 XMM} source register 
to the destination memory location, using a non-temporal hint. This store 
instruction minimizes cache pollution. The memory location must be aligned 
to a 16-byte boundary.
\par\sb120
\page
#{\footnote section_b_4_174}
${\footnote B.4.174. MOVNTPS: Move Aligned Four Packed Single-Precision FP Values Non Temporal}
+{\footnote browse:00394}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVNTPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.174. {\f1 MOVNTPS}: Move Aligned Four Packed Single-Precision FP Values Non Temporal
\par\pard\plain\sb120
\keep\f1\sb120
MOVNTPS m128,xmm              ; 0F 2B /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVNTPS} moves the double quadword from the {\f1 XMM} source register 
to the destination memory location, using a non-temporal hint. This store 
instruction minimizes cache pollution. The memory location must be aligned 
to a 16-byte boundary.
\par\sb120
\page
#{\footnote section_b_4_175}
${\footnote B.4.175. MOVNTQ: Move Quadword Non Temporal}
+{\footnote browse:00395}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVNTQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.175. {\f1 MOVNTQ}: Move Quadword Non Temporal
\par\pard\plain\sb120
\keep\f1\sb120
MOVNTQ m64,mm                 ; 0F E7 /r        [KATMAI,MMX]\par\sb0
\pard\f0\sb120
{\f1 MOVNTQ} moves the quadword in the {\f1 MMX} source register to the 
destination memory location, using a non-temporal hint. This store 
instruction minimizes cache pollution.
\par\sb120
\page
#{\footnote section_b_4_176}
${\footnote B.4.176. MOVQ: Move Quadword to/from MMX Register}
+{\footnote browse:00396}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.176. {\f1 MOVQ}: Move Quadword to/from MMX Register
\par\pard\plain\sb120
\keep\f1\sb120
MOVQ mm1,mm2/m64               ; 0F 6F /r             [PENT,MMX] \par\sb0
MOVQ mm1/m64,mm2               ; 0F 7F /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
MOVQ xmm1,xmm2/m64             ; F3 0F 7E /r    [WILLAMETTE,SSE2] \par\sb0
MOVQ xmm1/m64,xmm2             ; 66 0F D6 /r    [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVQ} copies 64 bits from its source (second) operand into its 
destination (first) operand. When the source is an {\f1 XMM} register, the 
low quadword is moved. When the destination is an {\f1 XMM} register, the 
destination is the low quadword, and the high quadword is cleared.
\par\sb120
\page
#{\footnote section_b_4_177}
${\footnote B.4.177. MOVQ2DQ: Move Quadword from MMX to XMM register.}
+{\footnote browse:00397}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVQ2DQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.177. {\f1 MOVQ2DQ}: Move Quadword from MMX to XMM register.
\par\pard\plain\sb120
\keep\f1\sb120
MOVQ2DQ xmm,mm                ; F3 OF D6 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVQ2DQ} moves the quadword from the source operand to the low 
quadword of the destination operand, and clears the high quadword.
\par\sb120
\page
#{\footnote section_b_4_178}
${\footnote B.4.178. MOVSB, MOVSW, MOVSD: Move String}
+{\footnote browse:00398}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
MOVSB;
MOVSD;
MOVSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.178. {\f1 MOVSB}, {\f1 MOVSW}, {\f1 MOVSD}: Move String
\par\pard\plain\sb120
\keep\f1\sb120
MOVSB                         ; A4                   [8086] \par\sb0
MOVSW                         ; o16 A5               [8086] \par\sb0
MOVSD                         ; o32 A5               [386]\par\sb0
\pard\f0\sb120
{\f1 MOVSB} copies the byte at {\f1 [DS:SI]} or {\f1 [DS:ESI]} to 
{\f1 [ES:DI]} or {\f1 [ES:EDI]}. It then increments or decrements 
(depending on the direction flag: increments if the flag is clear, 
decrements if it is set) {\f1 SI} and {\f1 DI} (or {\f1 ESI} and 
{\f1 EDI}).
\par\sb120
The registers used are {\f1 SI} and {\f1 DI} if the address size is 16 
bits, and {\f1 ESI} and {\f1 EDI} if it is 32 bits. If you need to use an 
address size not equal to the current {\f1 BITS} setting, you can use an 
explicit {\f1 a16} or {\f1 a32} prefix.
\par\sb120
The segment register used to load from {\f1 [SI]} or {\f1 [ESI]} can be 
overridden by using a segment register name as a prefix (for example, 
{\f1 es\'A0movsb}). The use of {\f1 ES} for the store to {\f1 [DI]} or 
{\f1 [EDI]} cannot be overridden.
\par\sb120
{\f1 MOVSW} and {\f1 MOVSD} work in the same way, but they copy a word or a 
doubleword instead of a byte, and increment or decrement the addressing 
registers by 2 or 4 instead of 1.
\par\sb120
The {\f1 REP} prefix may be used to repeat the instruction {\f1 CX} (or 
{\f1 ECX} \'96 again, the address size chooses which) times.
\par\sb120
\page
#{\footnote section_b_4_179}
${\footnote B.4.179. MOVSD: Move Scalar Double-Precision FP Value}
+{\footnote browse:00399}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVSD}
\keepn\f2\b\fs30\sb60\sa60
B.4.179. {\f1 MOVSD}: Move Scalar Double-Precision FP Value
\par\pard\plain\sb120
\keep\f1\sb120
MOVSD xmm1,xmm2/m64           ; F2 0F 10 /r     [WILLAMETTE,SSE2] \par\sb0
MOVSD xmm1/m64,xmm2           ; F2 0F 11 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVSD} moves a double-precision FP value from the source operand to 
the destination operand. When the source or destination is a register, the 
low-order FP value is read or written.
\par\sb120
\page
#{\footnote section_b_4_180}
${\footnote B.4.180. MOVSS: Move Scalar Single-Precision FP Value}
+{\footnote browse:00400}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.180. {\f1 MOVSS}: Move Scalar Single-Precision FP Value
\par\pard\plain\sb120
\keep\f1\sb120
MOVSS xmm1,xmm2/m32           ; F3 0F 10 /r     [KATMAI,SSE] \par\sb0
MOVSS xmm1/m32,xmm2           ; F3 0F 11 /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVSS} moves a single-precision FP value from the source operand to 
the destination operand. When the source or destination is a register, the 
low-order FP value is read or written.
\par\sb120
\page
#{\footnote section_b_4_181}
${\footnote B.4.181. MOVSX, MOVZX: Move Data with Sign or Zero Extend}
+{\footnote browse:00401}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVSX;
MOVZX}
\keepn\f2\b\fs30\sb60\sa60
B.4.181. {\f1 MOVSX}, {\f1 MOVZX}: Move Data with Sign or Zero Extend
\par\pard\plain\sb120
\keep\f1\sb120
MOVSX reg16,r/m8              ; o16 0F BE /r         [386] \par\sb0
MOVSX reg32,r/m8              ; o32 0F BE /r         [386] \par\sb0
MOVSX reg32,r/m16             ; o32 0F BF /r         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
MOVZX reg16,r/m8              ; o16 0F B6 /r         [386] \par\sb0
MOVZX reg32,r/m8              ; o32 0F B6 /r         [386] \par\sb0
MOVZX reg32,r/m16             ; o32 0F B7 /r         [386]\par\sb0
\pard\f0\sb120
{\f1 MOVSX} sign-extends its source (second) operand to the length of its 
destination (first) operand, and copies the result into the destination 
operand. {\f1 MOVZX} does the same, but zero-extends rather than 
sign-extending.
\par\sb120
\page
#{\footnote section_b_4_182}
${\footnote B.4.182. MOVUPD: Move Unaligned Packed Double-Precision FP Values}
+{\footnote browse:00402}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVUPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.182. {\f1 MOVUPD}: Move Unaligned Packed Double-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
MOVUPD xmm1,xmm2/mem128       ; 66 0F 10 /r     [WILLAMETTE,SSE2] \par\sb0
MOVUPD xmm1/mem128,xmm2       ; 66 0F 11 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MOVUPD} moves a double quadword containing 2 packed double-precision 
FP values from the source operand to the destination. This instruction 
makes no assumptions about alignment of memory operands.
\par\sb120
To move data in and out of memory locations that are known to be on 16-byte 
boundaries, use the {\f1 MOVAPD} instruction ({\uldb section 
B.4.157}{\v section_b_4_157}).
\par\sb120
\page
#{\footnote section_b_4_183}
${\footnote B.4.183. MOVUPS: Move Unaligned Packed Single-Precision FP Values}
+{\footnote browse:00403}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MOVUPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.183. {\f1 MOVUPS}: Move Unaligned Packed Single-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
MOVUPS xmm1,xmm2/mem128       ; 0F 10 /r        [KATMAI,SSE] \par\sb0
MOVUPS xmm1/mem128,xmm2       ; 0F 11 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MOVUPS} moves a double quadword containing 4 packed single-precision 
FP values from the source operand to the destination. This instruction 
makes no assumptions about alignment of memory operands.
\par\sb120
To move data in and out of memory locations that are known to be on 16-byte 
boundaries, use the {\f1 MOVAPS} instruction ({\uldb section 
B.4.158}{\v section_b_4_158}).
\par\sb120
\page
#{\footnote section_b_4_184}
${\footnote B.4.184. MUL: Unsigned Integer Multiply}
+{\footnote browse:00404}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MUL}
\keepn\f2\b\fs30\sb60\sa60
B.4.184. {\f1 MUL}: Unsigned Integer Multiply
\par\pard\plain\sb120
\keep\f1\sb120
MUL r/m8                      ; F6 /4                [8086] \par\sb0
MUL r/m16                     ; o16 F7 /4            [8086] \par\sb0
MUL r/m32                     ; o32 F7 /4            [386]\par\sb0
\pard\f0\sb120
{\f1 MUL} performs unsigned integer multiplication. The other operand to 
the multiplication, and the destination operand, are implicit, in the 
following way:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 MUL\'A0r/m8}, {\f1 AL} is multiplied by the given operand; the 
product is stored in {\f1 AX}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 MUL\'A0r/m16}, {\f1 AX} is multiplied by the given operand; the 
product is stored in {\f1 DX:AX}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 MUL\'A0r/m32}, {\f1 EAX} is multiplied by the given operand; the 
product is stored in {\f1 EDX:EAX}.
\par\pard\sb120
Signed integer multiplication is performed by the {\f1 IMUL} instruction: 
see {\uldb section B.4.118}{\v section_b_4_118}.
\par\sb120
\page
#{\footnote section_b_4_185}
${\footnote B.4.185. MULPD: Packed Single-FP Multiply}
+{\footnote browse:00405}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MULPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.185. {\f1 MULPD}: Packed Single-FP Multiply
\par\pard\plain\sb120
\keep\f1\sb120
MULPD xmm1,xmm2/mem128        ; 66 0F 59 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MULPD} performs a SIMD multiply of the packed double-precision FP 
values in both operands, and stores the results in the destination 
register.
\par\sb120
\page
#{\footnote section_b_4_186}
${\footnote B.4.186. MULPS: Packed Single-FP Multiply}
+{\footnote browse:00406}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MULPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.186. {\f1 MULPS}: Packed Single-FP Multiply
\par\pard\plain\sb120
\keep\f1\sb120
MULPS xmm1,xmm2/mem128        ; 0F 59 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MULPS} performs a SIMD multiply of the packed single-precision FP 
values in both operands, and stores the results in the destination 
register.
\par\sb120
\page
#{\footnote section_b_4_187}
${\footnote B.4.187. MULSD: Scalar Single-FP Multiply}
+{\footnote browse:00407}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MULSD}
\keepn\f2\b\fs30\sb60\sa60
B.4.187. {\f1 MULSD}: Scalar Single-FP Multiply
\par\pard\plain\sb120
\keep\f1\sb120
MULSD xmm1,xmm2/mem32         ; F2 0F 59 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 MULSD} multiplies the lowest double-precision FP values of both 
operands, and stores the result in the low quadword of xmm1.
\par\sb120
\page
#{\footnote section_b_4_188}
${\footnote B.4.188. MULSS: Scalar Single-FP Multiply}
+{\footnote browse:00408}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote MULSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.188. {\f1 MULSS}: Scalar Single-FP Multiply
\par\pard\plain\sb120
\keep\f1\sb120
MULSS xmm1,xmm2/mem32         ; F3 0F 59 /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 MULSS} multiplies the lowest single-precision FP values of both 
operands, and stores the result in the low doubleword of xmm1.
\par\sb120
\page
#{\footnote section_b_4_189}
${\footnote B.4.189. NEG, NOT: Two's and One's Complement}
+{\footnote browse:00409}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote NEG;
NOT}
\keepn\f2\b\fs30\sb60\sa60
B.4.189. {\f1 NEG}, {\f1 NOT}: Two's and One's Complement
\par\pard\plain\sb120
\keep\f1\sb120
NEG r/m8                      ; F6 /3                [8086] \par\sb0
NEG r/m16                     ; o16 F7 /3            [8086] \par\sb0
NEG r/m32                     ; o32 F7 /3            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
NOT r/m8                      ; F6 /2                [8086] \par\sb0
NOT r/m16                     ; o16 F7 /2            [8086] \par\sb0
NOT r/m32                     ; o32 F7 /2            [386]\par\sb0
\pard\f0\sb120
{\f1 NEG} replaces the contents of its operand by the two's complement 
negation (invert all the bits and then add one) of the original value. 
{\f1 NOT}, similarly, performs one's complement (inverts all the bits).
\par\sb120
\page
#{\footnote section_b_4_190}
${\footnote B.4.190. NOP: No Operation}
+{\footnote browse:00410}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote NOP}
\keepn\f2\b\fs30\sb60\sa60
B.4.190. {\f1 NOP}: No Operation
\par\pard\plain\sb120
\keep\f1\sb120
NOP                           ; 90                   [8086]\par\sb0
\pard\f0\sb120
{\f1 NOP} performs no operation. Its opcode is the same as that generated 
by {\f1 XCHG\'A0AX,AX} or {\f1 XCHG\'A0EAX,EAX} (depending on the processor 
mode; see {\uldb section B.4.333}{\v section_b_4_333}).
\par\sb120
\page
#{\footnote section_b_4_191}
${\footnote B.4.191. OR: Bitwise OR}
+{\footnote browse:00411}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote OR}
\keepn\f2\b\fs30\sb60\sa60
B.4.191. {\f1 OR}: Bitwise OR
\par\pard\plain\sb120
\keep\f1\sb120
OR r/m8,reg8                  ; 08 /r                [8086] \par\sb0
OR r/m16,reg16                ; o16 09 /r            [8086] \par\sb0
OR r/m32,reg32                ; o32 09 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
OR reg8,r/m8                  ; 0A /r                [8086] \par\sb0
OR reg16,r/m16                ; o16 0B /r            [8086] \par\sb0
OR reg32,r/m32                ; o32 0B /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
OR r/m8,imm8                  ; 80 /1 ib             [8086] \par\sb0
OR r/m16,imm16                ; o16 81 /1 iw         [8086] \par\sb0
OR r/m32,imm32                ; o32 81 /1 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
OR r/m16,imm8                 ; o16 83 /1 ib         [8086] \par\sb0
OR r/m32,imm8                 ; o32 83 /1 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
OR AL,imm8                    ; 0C ib                [8086] \par\sb0
OR AX,imm16                   ; o16 0D iw            [8086] \par\sb0
OR EAX,imm32                  ; o32 0D id            [386]\par\sb0
\pard\f0\sb120
{\f1 OR} performs a bitwise OR operation between its two operands (i.e. 
each bit of the result is 1 if and only if at least one of the 
corresponding bits of the two inputs was 1), and stores the result in the 
destination (first) operand.
\par\sb120
In the forms with an 8-bit immediate second operand and a longer first 
operand, the second operand is considered to be signed, and is 
sign-extended to the length of the first operand. In these cases, the 
{\f1 BYTE} qualifier is necessary to force NASM to generate this form of 
the instruction.
\par\sb120
The MMX instruction {\f1 POR} (see {\uldb section 
B.4.247}{\v section_b_4_247}) performs the same operation on the 64-bit MMX 
registers.
\par\sb120
\page
#{\footnote section_b_4_192}
${\footnote B.4.192. ORPD: Bit-wise Logical OR of Double-Precision FP Data}
+{\footnote browse:00412}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ORPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.192. {\f1 ORPD}: Bit-wise Logical OR of Double-Precision FP Data
\par\pard\plain\sb120
\keep\f1\sb120
ORPD xmm1,xmm2/m128           ; 66 0F 56 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 ORPD} return a bit-wise logical OR between xmm1 and xmm2/mem, and 
stores the result in xmm1. If the source operand is a memory location, it 
must be aligned to a 16-byte boundary.
\par\sb120
\page
#{\footnote section_b_4_193}
${\footnote B.4.193. ORPS: Bit-wise Logical OR of Single-Precision FP Data}
+{\footnote browse:00413}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ORPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.193. {\f1 ORPS}: Bit-wise Logical OR of Single-Precision FP Data
\par\pard\plain\sb120
\keep\f1\sb120
ORPS xmm1,xmm2/m128           ; 0F 56 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 ORPS} return a bit-wise logical OR between xmm1 and xmm2/mem, and 
stores the result in xmm1. If the source operand is a memory location, it 
must be aligned to a 16-byte boundary.
\par\sb120
\page
#{\footnote section_b_4_194}
${\footnote B.4.194. OUT: Output Data to I/O Port}
+{\footnote browse:00414}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote OUT}
\keepn\f2\b\fs30\sb60\sa60
B.4.194. {\f1 OUT}: Output Data to I/O Port
\par\pard\plain\sb120
\keep\f1\sb120
OUT imm8,AL                   ; E6 ib                [8086] \par\sb0
OUT imm8,AX                   ; o16 E7 ib            [8086] \par\sb0
OUT imm8,EAX                  ; o32 E7 ib            [386] \par\sb0
OUT DX,AL                     ; EE                   [8086] \par\sb0
OUT DX,AX                     ; o16 EF               [8086] \par\sb0
OUT DX,EAX                    ; o32 EF               [386]\par\sb0
\pard\f0\sb120
{\f1 OUT} writes the contents of the given source register to the specified 
I/O port. The port number may be specified as an immediate value if it is 
between 0 and 255, and otherwise must be stored in {\f1 DX}. See also 
{\f1 IN} ({\uldb section B.4.119}{\v section_b_4_119}).
\par\sb120
\page
#{\footnote section_b_4_195}
${\footnote B.4.195. OUTSB, OUTSW, OUTSD: Output String to I/O Port}
+{\footnote browse:00415}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
OUTSB;
OUTSD;
OUTSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.195. {\f1 OUTSB}, {\f1 OUTSW}, {\f1 OUTSD}: Output String to I/O Port
\par\pard\plain\sb120
\keep\f1\sb120
OUTSB                         ; 6E                   [186] \par\sb0
OUTSW                         ; o16 6F               [186] \par\sb0
OUTSD                         ; o32 6F               [386]\par\sb0
\pard\f0\sb120
{\f1 OUTSB} loads a byte from {\f1 [DS:SI]} or {\f1 [DS:ESI]} and writes it 
to the I/O port specified in {\f1 DX}. It then increments or decrements 
(depending on the direction flag: increments if the flag is clear, 
decrements if it is set) {\f1 SI} or {\f1 ESI}.
\par\sb120
The register used is {\f1 SI} if the address size is 16 bits, and {\f1 ESI} 
if it is 32 bits. If you need to use an address size not equal to the 
current {\f1 BITS} setting, you can use an explicit {\f1 a16} or {\f1 a32} 
prefix.
\par\sb120
The segment register used to load from {\f1 [SI]} or {\f1 [ESI]} can be 
overridden by using a segment register name as a prefix (for example, 
{\f1 es\'A0outsb}).
\par\sb120
{\f1 OUTSW} and {\f1 OUTSD} work in the same way, but they output a word or 
a doubleword instead of a byte, and increment or decrement the addressing 
registers by 2 or 4 instead of 1.
\par\sb120
The {\f1 REP} prefix may be used to repeat the instruction {\f1 CX} (or 
{\f1 ECX} \'96 again, the address size chooses which) times.
\par\sb120
\page
#{\footnote section_b_4_196}
${\footnote B.4.196. PACKSSDW, PACKSSWB, PACKUSWB: Pack Data}
+{\footnote browse:00416}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PACKSSDW;
PACKSSWB;
PACKUSWB}
\keepn\f2\b\fs30\sb60\sa60
B.4.196. {\f1 PACKSSDW}, {\f1 PACKSSWB}, {\f1 PACKUSWB}: Pack Data
\par\pard\plain\sb120
\keep\f1\sb120
PACKSSDW mm1,mm2/m64          ; 0F 6B /r             [PENT,MMX] \par\sb0
PACKSSWB mm1,mm2/m64          ; 0F 63 /r             [PENT,MMX] \par\sb0
PACKUSWB mm1,mm2/m64          ; 0F 67 /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PACKSSDW xmm1,xmm2/m128       ; 66 0F 6B /r     [WILLAMETTE,SSE2] \par\sb0
PACKSSWB xmm1,xmm2/m128       ; 66 0F 63 /r     [WILLAMETTE,SSE2] \par\sb0
PACKUSWB xmm1,xmm2/m128       ; 66 0F 67 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
All these instructions start by combining the source and destination 
operands, and then splitting the result in smaller sections which it then 
packs into the destination register. The {\f1 MMX} versions pack two 64-bit 
operands into one 64-bit register, while the {\f1 SSE} versions pack two 
128-bit operands into one 128-bit register.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PACKSSWB} splits the combined value into words, and then reduces the 
words to bytes, using signed saturation. It then packs the bytes into the 
destination register in the same order the words were in.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PACKSSDW} performs the same operation as {\f1 PACKSSWB}, except that 
it reduces doublewords to words, then packs them into the destination 
register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PACKUSWB} performs the same operation as {\f1 PACKSSWB}, except that 
it uses unsigned saturation when reducing the size of the elements.
\par\pard\sb120
To perform signed saturation on a number, it is replaced by the largest 
signed number ({\f1 7FFFh} or {\f1 7Fh}) that {\i will} fit, and if it is 
too small it is replaced by the smallest signed number ({\f1 8000h} or 
{\f1 80h}) that will fit. To perform unsigned saturation, the input is 
treated as unsigned, and the input is replaced by the largest unsigned 
number that will fit.
\par\sb120
\page
#{\footnote section_b_4_197}
${\footnote B.4.197. PADDB, PADDW, PADDD: Add Packed Integers}
+{\footnote browse:00417}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PADDB;
PADDD;
PADDW}
\keepn\f2\b\fs30\sb60\sa60
B.4.197. {\f1 PADDB}, {\f1 PADDW}, {\f1 PADDD}: Add Packed Integers
\par\pard\plain\sb120
\keep\f1\sb120
PADDB mm1,mm2/m64             ; 0F FC /r             [PENT,MMX] \par\sb0
PADDW mm1,mm2/m64             ; 0F FD /r             [PENT,MMX] \par\sb0
PADDD mm1,mm2/m64             ; 0F FE /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PADDB xmm1,xmm2/m128          ; 66 0F FC /r     [WILLAMETTE,SSE2] \par\sb0
PADDW xmm1,xmm2/m128          ; 66 0F FD /r     [WILLAMETTE,SSE2] \par\sb0
PADDD xmm1,xmm2/m128          ; 66 0F FE /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PADDx} performs packed addition of the two operands, storing the 
result in the destination (first) operand.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PADDB} treats the operands as packed bytes, and adds each byte 
individually;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PADDW} treats the operands as packed words;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PADDD} treats its operands as packed doublewords.
\par\pard\sb120
When an individual result is too large to fit in its destination, it is 
wrapped around and the low bits are stored, with the carry bit discarded.
\par\sb120
\page
#{\footnote section_b_4_198}
${\footnote B.4.198. PADDQ: Add Packed Quadword Integers}
+{\footnote browse:00418}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PADDQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.198. {\f1 PADDQ}: Add Packed Quadword Integers
\par\pard\plain\sb120
\keep\f1\sb120
PADDQ mm1,mm2/m64             ; 0F D4 /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PADDQ xmm1,xmm2/m128          ; 66 0F D4 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PADDQ} adds the quadwords in the source and destination operands, and 
stores the result in the destination register.
\par\sb120
When an individual result is too large to fit in its destination, it is 
wrapped around and the low bits are stored, with the carry bit discarded.
\par\sb120
\page
#{\footnote section_b_4_199}
${\footnote B.4.199. PADDSB, PADDSW: Add Packed Signed Integers With Saturation}
+{\footnote browse:00419}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PADDSB;
PADDSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.199. {\f1 PADDSB}, {\f1 PADDSW}: Add Packed Signed Integers With Saturation
\par\pard\plain\sb120
\keep\f1\sb120
PADDSB mm1,mm2/m64            ; 0F EC /r             [PENT,MMX] \par\sb0
PADDSW mm1,mm2/m64            ; 0F ED /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PADDSB xmm1,xmm2/m128         ; 66 0F EC /r     [WILLAMETTE,SSE2] \par\sb0
PADDSW xmm1,xmm2/m128         ; 66 0F ED /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PADDSx} performs packed addition of the two operands, storing the 
result in the destination (first) operand. {\f1 PADDSB} treats the operands 
as packed bytes, and adds each byte individually; and {\f1 PADDSW} treats 
the operands as packed words.
\par\sb120
When an individual result is too large to fit in its destination, a 
saturated value is stored. The resulting value is the value with the 
largest magnitude of the same sign as the result which will fit in the 
available space.
\par\sb120
\page
#{\footnote section_b_4_200}
${\footnote B.4.200. PADDSIW: MMX Packed Addition to Implicit Destination}
+{\footnote browse:00420}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PADDSIW}
\keepn\f2\b\fs30\sb60\sa60
B.4.200. {\f1 PADDSIW}: MMX Packed Addition to Implicit Destination
\par\pard\plain\sb120
\keep\f1\sb120
PADDSIW mmxreg,r/m64          ; 0F 51 /r             [CYRIX,MMX]\par\sb0
\pard\f0\sb120
{\f1 PADDSIW}, specific to the Cyrix extensions to the MMX instruction set, 
performs the same function as {\f1 PADDSW}, except that the result is 
placed in an implied register.
\par\sb120
To work out the implied register, invert the lowest bit in the register 
number. So {\f1 PADDSIW\'A0MM0,MM2} would put the result in {\f1 MM1}, but 
{\f1 PADDSIW\'A0MM1,MM2} would put the result in {\f1 MM0}.
\par\sb120
\page
#{\footnote section_b_4_201}
${\footnote B.4.201. PADDUSB, PADDUSW: Add Packed Unsigned Integers With Saturation}
+{\footnote browse:00421}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PADDUSB;
PADDUSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.201. {\f1 PADDUSB}, {\f1 PADDUSW}: Add Packed Unsigned Integers With Saturation
\par\pard\plain\sb120
\keep\f1\sb120
PADDUSB mm1,mm2/m64           ; 0F DC /r             [PENT,MMX] \par\sb0
PADDUSW mm1,mm2/m64           ; 0F DD /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PADDUSB xmm1,xmm2/m128         ; 66 0F DC /r    [WILLAMETTE,SSE2] \par\sb0
PADDUSW xmm1,xmm2/m128         ; 66 0F DD /r    [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PADDUSx} performs packed addition of the two operands, storing the 
result in the destination (first) operand. {\f1 PADDUSB} treats the 
operands as packed bytes, and adds each byte individually; and 
{\f1 PADDUSW} treats the operands as packed words.
\par\sb120
When an individual result is too large to fit in its destination, a 
saturated value is stored. The resulting value is the maximum value that 
will fit in the available space.
\par\sb120
\page
#{\footnote section_b_4_202}
${\footnote B.4.202. PAND, PANDN: MMX Bitwise AND and AND-NOT}
+{\footnote browse:00422}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PAND;
PANDN}
\keepn\f2\b\fs30\sb60\sa60
B.4.202. {\f1 PAND}, {\f1 PANDN}: MMX Bitwise AND and AND-NOT
\par\pard\plain\sb120
\keep\f1\sb120
PAND mm1,mm2/m64              ; 0F DB /r             [PENT,MMX] \par\sb0
PANDN mm1,mm2/m64             ; 0F DF /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PAND xmm1,xmm2/m128           ; 66 0F DB /r     [WILLAMETTE,SSE2] \par\sb0
PANDN xmm1,xmm2/m128          ; 66 0F DF /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PAND} performs a bitwise AND operation between its two operands (i.e. 
each bit of the result is 1 if and only if the corresponding bits of the 
two inputs were both 1), and stores the result in the destination (first) 
operand.
\par\sb120
{\f1 PANDN} performs the same operation, but performs a one's complement 
operation on the destination (first) operand first.
\par\sb120
\page
#{\footnote section_b_4_203}
${\footnote B.4.203. PAUSE: Spin Loop Hint}
+{\footnote browse:00423}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PAUSE}
\keepn\f2\b\fs30\sb60\sa60
B.4.203. {\f1 PAUSE}: Spin Loop Hint
\par\pard\plain\sb120
\keep\f1\sb120
PAUSE                         ; F3 90           [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PAUSE} provides a hint to the processor that the following code is a 
spin loop. This improves processor performance by bypassing possible memory 
order violations. On older processors, this instruction operates as a 
{\f1 NOP}.
\par\sb120
\page
#{\footnote section_b_4_204}
${\footnote B.4.204. PAVEB: MMX Packed Average}
+{\footnote browse:00424}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PAVEB}
\keepn\f2\b\fs30\sb60\sa60
B.4.204. {\f1 PAVEB}: MMX Packed Average
\par\pard\plain\sb120
\keep\f1\sb120
PAVEB mmxreg,r/m64            ; 0F 50 /r             [CYRIX,MMX]\par\sb0
\pard\f0\sb120
{\f1 PAVEB}, specific to the Cyrix MMX extensions, treats its two operands 
as vectors of eight unsigned bytes, and calculates the average of the 
corresponding bytes in the operands. The resulting vector of eight averages 
is stored in the first operand.
\par\sb120
This opcode maps to {\f1 MOVMSKPS\'A0r32,\'A0xmm} on processors that 
support the SSE instruction set.
\par\sb120
\page
#{\footnote section_b_4_205}
${\footnote B.4.205. PAVGB PAVGW: Average Packed Integers}
+{\footnote browse:00425}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PAVGB;
PAVGW}
\keepn\f2\b\fs30\sb60\sa60
B.4.205. {\f1 PAVGB} {\f1 PAVGW}: Average Packed Integers
\par\pard\plain\sb120
\keep\f1\sb120
PAVGB mm1,mm2/m64             ; 0F E0 /r        [KATMAI,MMX] \par\sb0
PAVGW mm1,mm2/m64             ; 0F E3 /r        [KATMAI,MMX,SM]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PAVGB xmm1,xmm2/m128          ; 66 0F E0 /r     [WILLAMETTE,SSE2] \par\sb0
PAVGW xmm1,xmm2/m128          ; 66 0F E3 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PAVGB} and {\f1 PAVGW} add the unsigned data elements of the source 
operand to the unsigned data elements of the destination register, then 
adds 1 to the temporary results. The results of the add are then each 
independently right-shifted by one bit position. The high order bits of 
each element are filled with the carry bits of the corresponding sum.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PAVGB} operates on packed unsigned bytes, and
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PAVGW} operates on packed unsigned words.
\par\pard\sb120
\page
#{\footnote section_b_4_206}
${\footnote B.4.206. PAVGUSB: Average of unsigned packed 8-bit values}
+{\footnote browse:00426}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PAVGUSB}
\keepn\f2\b\fs30\sb60\sa60
B.4.206. {\f1 PAVGUSB}: Average of unsigned packed 8-bit values
\par\pard\plain\sb120
\keep\f1\sb120
PAVGUSB mm1,mm2/m64           ; 0F 0F /r BF          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PAVGUSB} adds the unsigned data elements of the source operand to the 
unsigned data elements of the destination register, then adds 1 to the 
temporary results. The results of the add are then each independently 
right-shifted by one bit position. The high order bits of each element are 
filled with the carry bits of the corresponding sum.
\par\sb120
This instruction performs exactly the same operations as the {\f1 PAVGB} 
{\f1 MMX} instruction ({\uldb section B.4.205}{\v section_b_4_205}).
\par\sb120
\page
#{\footnote section_b_4_207}
${\footnote B.4.207. PCMPxx: Compare Packed Integers.}
+{\footnote browse:00427}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PCMPxx}
\keepn\f2\b\fs30\sb60\sa60
B.4.207. {\f1 PCMPxx}: Compare Packed Integers.
\par\pard\plain\sb120
\keep\f1\sb120
PCMPEQB mm1,mm2/m64           ; 0F 74 /r             [PENT,MMX] \par\sb0
PCMPEQW mm1,mm2/m64           ; 0F 75 /r             [PENT,MMX] \par\sb0
PCMPEQD mm1,mm2/m64           ; 0F 76 /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PCMPGTB mm1,mm2/m64           ; 0F 64 /r             [PENT,MMX] \par\sb0
PCMPGTW mm1,mm2/m64           ; 0F 65 /r             [PENT,MMX] \par\sb0
PCMPGTD mm1,mm2/m64           ; 0F 66 /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PCMPEQB xmm1,xmm2/m128        ; 66 0F 74 /r     [WILLAMETTE,SSE2] \par\sb0
PCMPEQW xmm1,xmm2/m128        ; 66 0F 75 /r     [WILLAMETTE,SSE2] \par\sb0
PCMPEQD xmm1,xmm2/m128        ; 66 0F 76 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PCMPGTB xmm1,xmm2/m128        ; 66 0F 64 /r     [WILLAMETTE,SSE2] \par\sb0
PCMPGTW xmm1,xmm2/m128        ; 66 0F 65 /r     [WILLAMETTE,SSE2] \par\sb0
PCMPGTD xmm1,xmm2/m128        ; 66 0F 66 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
The {\f1 PCMPxx} instructions all treat their operands as vectors of bytes, 
words, or doublewords; corresponding elements of the source and destination 
are compared, and the corresponding element of the destination (first) 
operand is set to all zeros or all ones depending on the result of the 
comparison.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PCMPxxB} treats the operands as vectors of bytes;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PCMPxxW} treats the operands as vectors of words;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PCMPxxD} treats the operands as vectors of doublewords;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PCMPEQx} sets the corresponding element of the destination operand to 
all ones if the two elements compared are equal;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PCMPGTx} sets the destination element to all ones if the element of 
the first (destination) operand is greater (treated as a signed integer) 
than that of the second (source) operand.
\par\pard\sb120
\page
#{\footnote section_b_4_208}
${\footnote B.4.208. PDISTIB: MMX Packed Distance and Accumulate with Implied Register}
+{\footnote browse:00428}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PDISTIB}
\keepn\f2\b\fs30\sb60\sa60
B.4.208. {\f1 PDISTIB}: MMX Packed Distance and Accumulate with Implied Register
\par\pard\plain\sb120
\keep\f1\sb120
PDISTIB mm,m64                ; 0F 54 /r             [CYRIX,MMX]\par\sb0
\pard\f0\sb120
{\f1 PDISTIB}, specific to the Cyrix MMX extensions, treats its two input 
operands as vectors of eight unsigned bytes. For each byte position, it 
finds the absolute difference between the bytes in that position in the two 
input operands, and adds that value to the byte in the same position in the 
implied output register. The addition is saturated to an unsigned byte in 
the same way as {\f1 PADDUSB}.
\par\sb120
To work out the implied register, invert the lowest bit in the register 
number. So {\f1 PDISTIB\'A0MM0,M64} would put the result in {\f1 MM1}, but 
{\f1 PDISTIB\'A0MM1,M64} would put the result in {\f1 MM0}.
\par\sb120
Note that {\f1 PDISTIB} cannot take a register as its second source 
operand.
\par\sb120
Operation:
\par\sb120
\keep\f1\sb120
   dstI[0-7]     := dstI[0-7]   + ABS(src0[0-7] - src1[0-7]), \par\sb0
   dstI[8-15]    := dstI[8-15]  + ABS(src0[8-15] - src1[8-15]), \par\sb0
   ....... \par\sb0
   ....... \par\sb0
   dstI[56-63]   := dstI[56-63] + ABS(src0[56-63] - src1[56-63]).\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_209}
${\footnote B.4.209. PEXTRW: Extract Word}
+{\footnote browse:00429}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PEXTRW}
\keepn\f2\b\fs30\sb60\sa60
B.4.209. {\f1 PEXTRW}: Extract Word
\par\pard\plain\sb120
\keep\f1\sb120
PEXTRW reg32,mm,imm8          ; 0F C5 /r ib     [KATMAI,MMX] \par\sb0
PEXTRW reg32,xmm,imm8         ; 66 0F C5 /r ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PEXTRW} moves the word in the source register (second operand) that is 
pointed to by the count operand (third operand), into the lower half of a 
32-bit general purpose register. The upper half of the register is cleared 
to all 0s.
\par\sb120
When the source operand is an {\f1 MMX} register, the two least significant 
bits of the count specify the source word. When it is an {\f1 SSE} 
register, the three least significant bits specify the word location.
\par\sb120
\page
#{\footnote section_b_4_210}
${\footnote B.4.210. PF2ID: Packed Single-Precision FP to Integer Convert}
+{\footnote browse:00430}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PF2ID}
\keepn\f2\b\fs30\sb60\sa60
B.4.210. {\f1 PF2ID}: Packed Single-Precision FP to Integer Convert
\par\pard\plain\sb120
\keep\f1\sb120
PF2ID mm1,mm2/m64             ; 0F 0F /r 1D          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PF2ID} converts two single-precision FP values in the source operand 
to signed 32-bit integers, using truncation, and stores them in the 
destination operand. Source values that are outside the range supported by 
the destination are saturated to the largest absolute value of the same 
sign.
\par\sb120
\page
#{\footnote section_b_4_211}
${\footnote B.4.211. PF2IW: Packed Single-Precision FP to Integer Word Convert}
+{\footnote browse:00431}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PF2IW}
\keepn\f2\b\fs30\sb60\sa60
B.4.211. {\f1 PF2IW}: Packed Single-Precision FP to Integer Word Convert
\par\pard\plain\sb120
\keep\f1\sb120
PF2IW mm1,mm2/m64             ; 0F 0F /r 1C          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PF2IW} converts two single-precision FP values in the source operand 
to signed 16-bit integers, using truncation, and stores them in the 
destination operand. Source values that are outside the range supported by 
the destination are saturated to the largest absolute value of the same 
sign.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
In the K6-2 and K6-III, the 16-bit value is zero-extended to 32-bits before 
storing.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
In the K6-2+, K6-III+ and Athlon processors, the value is sign-extended to 
32-bits before storing.
\par\pard\sb120
\page
#{\footnote section_b_4_212}
${\footnote B.4.212. PFACC: Packed Single-Precision FP Accumulate}
+{\footnote browse:00432}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFACC}
\keepn\f2\b\fs30\sb60\sa60
B.4.212. {\f1 PFACC}: Packed Single-Precision FP Accumulate
\par\pard\plain\sb120
\keep\f1\sb120
PFACC mm1,mm2/m64             ; 0F 0F /r AE          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFACC} adds the two single-precision FP values from the destination 
operand together, then adds the two single-precision FP values from the 
source operand, and places the results in the low and high doublewords of 
the destination operand.
\par\sb120
The operation is:
\par\sb120
\keep\f1\sb120
   dst[0-31]   := dst[0-31] + dst[32-63], \par\sb0
   dst[32-63]  := src[0-31] + src[32-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_213}
${\footnote B.4.213. PFADD: Packed Single-Precision FP Addition}
+{\footnote browse:00433}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFADD}
\keepn\f2\b\fs30\sb60\sa60
B.4.213. {\f1 PFADD}: Packed Single-Precision FP Addition
\par\pard\plain\sb120
\keep\f1\sb120
PFADD mm1,mm2/m64             ; 0F 0F /r 9E          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFADD} performs addition on each of two packed single-precision FP 
value pairs.
\par\sb120
\keep\f1\sb120
   dst[0-31]   := dst[0-31]  + src[0-31], \par\sb0
   dst[32-63]  := dst[32-63] + src[32-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_214}
${\footnote B.4.214. PFCMPxx: Packed Single-Precision FP Compare   }
+{\footnote browse:00434}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFCMPEQ;
PFCMPGE;
PFCMPGT;
PFCMPxx}
\keepn\f2\b\fs30\sb60\sa60
B.4.214. {\f1 PFCMPxx}: Packed Single-Precision FP Compare   
\par\pard\plain\sb120
\keep\f1\sb120
PFCMPEQ mm1,mm2/m64           ; 0F 0F /r B0          [PENT,3DNOW] \par\sb0
PFCMPGE mm1,mm2/m64           ; 0F 0F /r 90          [PENT,3DNOW] \par\sb0
PFCMPGT mm1,mm2/m64           ; 0F 0F /r A0          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
The {\f1 PFCMPxx} instructions compare the packed single-point FP values in 
the source and destination operands, and set the destination according to 
the result. If the condition is true, the destination is set to all 1s, 
otherwise it's set to all 0s.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PFCMPEQ} tests whether dst == src;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PFCMPGE} tests whether dst >= src;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PFCMPGT} tests whether dst > src.
\par\pard\sb120
\page
#{\footnote section_b_4_215}
${\footnote B.4.215. PFMAX: Packed Single-Precision FP Maximum}
+{\footnote browse:00435}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFMAX}
\keepn\f2\b\fs30\sb60\sa60
B.4.215. {\f1 PFMAX}: Packed Single-Precision FP Maximum
\par\pard\plain\sb120
\keep\f1\sb120
PFMAX mm1,mm2/m64             ; 0F 0F /r A4          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFMAX} returns the higher of each pair of single-precision FP values. 
If the higher value is zero, it is returned as positive zero.
\par\sb120
\page
#{\footnote section_b_4_216}
${\footnote B.4.216. PFMIN: Packed Single-Precision FP Minimum}
+{\footnote browse:00436}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFMIN}
\keepn\f2\b\fs30\sb60\sa60
B.4.216. {\f1 PFMIN}: Packed Single-Precision FP Minimum
\par\pard\plain\sb120
\keep\f1\sb120
PFMIN mm1,mm2/m64             ; 0F 0F /r 94          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFMIN} returns the lower of each pair of single-precision FP values. 
If the lower value is zero, it is returned as positive zero.
\par\sb120
\page
#{\footnote section_b_4_217}
${\footnote B.4.217. PFMUL: Packed Single-Precision FP Multiply}
+{\footnote browse:00437}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFMUL}
\keepn\f2\b\fs30\sb60\sa60
B.4.217. {\f1 PFMUL}: Packed Single-Precision FP Multiply
\par\pard\plain\sb120
\keep\f1\sb120
PFMUL mm1,mm2/m64             ; 0F 0F /r B4          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFMUL} returns the product of each pair of single-precision FP values.
\par\sb120
\keep\f1\sb120
   dst[0-31]  := dst[0-31]  * src[0-31], \par\sb0
   dst[32-63] := dst[32-63] * src[32-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_218}
${\footnote B.4.218. PFNACC: Packed Single-Precision FP Negative Accumulate}
+{\footnote browse:00438}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFNACC}
\keepn\f2\b\fs30\sb60\sa60
B.4.218. {\f1 PFNACC}: Packed Single-Precision FP Negative Accumulate
\par\pard\plain\sb120
\keep\f1\sb120
PFNACC mm1,mm2/m64            ; 0F 0F /r 8A          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFNACC} performs a negative accumulate of the two single-precision FP 
values in the source and destination registers. The result of the 
accumulate from the destination register is stored in the low doubleword of 
the destination, and the result of the source accumulate is stored in the 
high doubleword of the destination register.
\par\sb120
The operation is:
\par\sb120
\keep\f1\sb120
   dst[0-31]  := dst[0-31] - dst[32-63], \par\sb0
   dst[32-63] := src[0-31] - src[32-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_219}
${\footnote B.4.219. PFPNACC: Packed Single-Precision FP Mixed Accumulate}
+{\footnote browse:00439}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFPNACC}
\keepn\f2\b\fs30\sb60\sa60
B.4.219. {\f1 PFPNACC}: Packed Single-Precision FP Mixed Accumulate
\par\pard\plain\sb120
\keep\f1\sb120
PFPNACC mm1,mm2/m64           ; 0F 0F /r 8E          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFPNACC} performs a positive accumulate of the two single-precision FP 
values in the source register and a negative accumulate of the destination 
register. The result of the accumulate from the destination register is 
stored in the low doubleword of the destination, and the result of the 
source accumulate is stored in the high doubleword of the destination 
register.
\par\sb120
The operation is:
\par\sb120
\keep\f1\sb120
   dst[0-31]  := dst[0-31] - dst[32-63], \par\sb0
   dst[32-63] := src[0-31] + src[32-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_220}
${\footnote B.4.220. PFRCP: Packed Single-Precision FP Reciprocal Approximation}
+{\footnote browse:00440}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFRCP}
\keepn\f2\b\fs30\sb60\sa60
B.4.220. {\f1 PFRCP}: Packed Single-Precision FP Reciprocal Approximation
\par\pard\plain\sb120
\keep\f1\sb120
PFRCP mm1,mm2/m64             ; 0F 0F /r 96          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFRCP} performs a low precision estimate of the reciprocal of the 
low-order single-precision FP value in the source operand, storing the 
result in both halves of the destination register. The result is accurate 
to 14 bits.
\par\sb120
For higher precision reciprocals, this instruction should be followed by 
two more instructions: {\f1 PFRCPIT1} ({\uldb section 
B.4.221}{\v section_b_4_221}) and {\f1 PFRCPIT2} ({\uldb section 
B.4.221}{\v section_b_4_221}). This will result in a 24-bit accuracy. For 
more details, see the AMD 3DNow! technology manual.
\par\sb120
\page
#{\footnote section_b_4_221}
${\footnote B.4.221. PFRCPIT1: Packed Single-Precision FP Reciprocal, First Iteration Step}
+{\footnote browse:00441}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFRCPIT1}
\keepn\f2\b\fs30\sb60\sa60
B.4.221. {\f1 PFRCPIT1}: Packed Single-Precision FP Reciprocal, First Iteration Step
\par\pard\plain\sb120
\keep\f1\sb120
PFRCPIT1 mm1,mm2/m64          ; 0F 0F /r A6          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFRCPIT1} performs the first intermediate step in the calculation of 
the reciprocal of a single-precision FP value. The first source value 
({\f1 mm1} is the original value, and the second source value 
({\f1 mm2/m64} is the result of a {\f1 PFRCP} instruction.
\par\sb120
For the final step in a reciprocal, returning the full 24-bit accuracy of a 
single-precision FP value, see {\f1 PFRCPIT2} ({\uldb section 
B.4.222}{\v section_b_4_222}). For more details, see the AMD 3DNow! 
technology manual.
\par\sb120
\page
#{\footnote section_b_4_222}
${\footnote B.4.222. PFRCPIT2: Packed Single-Precision FP Reciprocal/ Reciprocal Square Root, Second Iteration Step}
+{\footnote browse:00442}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFRCPIT2}
\keepn\f2\b\fs30\sb60\sa60
B.4.222. {\f1 PFRCPIT2}: Packed Single-Precision FP Reciprocal/ Reciprocal Square Root, Second Iteration Step
\par\pard\plain\sb120
\keep\f1\sb120
PFRCPIT2 mm1,mm2/m64          ; 0F 0F /r B6          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFRCPIT2} performs the second and final intermediate step in the 
calculation of a reciprocal or reciprocal square root, refining the values 
returned by the {\f1 PFRCP} and {\f1 PFRSQRT} instructions, respectively.
\par\sb120
The first source value ({\f1 mm1}) is the output of either a {\f1 PFRCPIT1} 
or a {\f1 PFRSQIT1} instruction, and the second source is the output of 
either the {\f1 PFRCP} or the {\f1 PFRSQRT} instruction. For more details, 
see the AMD 3DNow! technology manual.
\par\sb120
\page
#{\footnote section_b_4_223}
${\footnote B.4.223. PFRSQIT1: Packed Single-Precision FP Reciprocal Square Root, First Iteration Step}
+{\footnote browse:00443}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFRSQIT1}
\keepn\f2\b\fs30\sb60\sa60
B.4.223. {\f1 PFRSQIT1}: Packed Single-Precision FP Reciprocal Square Root, First Iteration Step
\par\pard\plain\sb120
\keep\f1\sb120
PFRSQIT1 mm1,mm2/m64          ; 0F 0F /r A7          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFRSQIT1} performs the first intermediate step in the calculation of 
the reciprocal square root of a single-precision FP value. The first source 
value ({\f1 mm1} is the square of the result of a {\f1 PFRSQRT} 
instruction, and the second source value ({\f1 mm2/m64} is the original 
value.
\par\sb120
For the final step in a calculation, returning the full 24-bit accuracy of 
a single-precision FP value, see {\f1 PFRCPIT2} ({\uldb section 
B.4.222}{\v section_b_4_222}). For more details, see the AMD 3DNow! 
technology manual.
\par\sb120
\page
#{\footnote section_b_4_224}
${\footnote B.4.224. PFRSQRT: Packed Single-Precision FP Reciprocal Square Root Approximation}
+{\footnote browse:00444}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFRSQRT}
\keepn\f2\b\fs30\sb60\sa60
B.4.224. {\f1 PFRSQRT}: Packed Single-Precision FP Reciprocal Square Root Approximation
\par\pard\plain\sb120
\keep\f1\sb120
PFRSQRT mm1,mm2/m64           ; 0F 0F /r 97          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFRSQRT} performs a low precision estimate of the reciprocal square 
root of the low-order single-precision FP value in the source operand, 
storing the result in both halves of the destination register. The result 
is accurate to 15 bits.
\par\sb120
For higher precision reciprocals, this instruction should be followed by 
two more instructions: {\f1 PFRSQIT1} ({\uldb section 
B.4.223}{\v section_b_4_223}) and {\f1 PFRCPIT2} ({\uldb section 
B.4.221}{\v section_b_4_221}). This will result in a 24-bit accuracy. For 
more details, see the AMD 3DNow! technology manual.
\par\sb120
\page
#{\footnote section_b_4_225}
${\footnote B.4.225. PFSUB: Packed Single-Precision FP Subtract}
+{\footnote browse:00445}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFSUB}
\keepn\f2\b\fs30\sb60\sa60
B.4.225. {\f1 PFSUB}: Packed Single-Precision FP Subtract
\par\pard\plain\sb120
\keep\f1\sb120
PFSUB mm1,mm2/m64             ; 0F 0F /r 9A          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFSUB} subtracts the single-precision FP values in the source from 
those in the destination, and stores the result in the destination operand.
\par\sb120
\keep\f1\sb120
   dst[0-31]  := dst[0-31]  - src[0-31], \par\sb0
   dst[32-63] := dst[32-63] - src[32-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_226}
${\footnote B.4.226. PFSUBR: Packed Single-Precision FP Reverse Subtract}
+{\footnote browse:00446}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PFSUBR}
\keepn\f2\b\fs30\sb60\sa60
B.4.226. {\f1 PFSUBR}: Packed Single-Precision FP Reverse Subtract
\par\pard\plain\sb120
\keep\f1\sb120
PFSUBR mm1,mm2/m64            ; 0F 0F /r AA          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PFSUBR} subtracts the single-precision FP values in the destination 
from those in the source, and stores the result in the destination operand.
\par\sb120
\keep\f1\sb120
   dst[0-31]  := src[0-31]  - dst[0-31], \par\sb0
   dst[32-63] := src[32-63] - dst[32-63].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_227}
${\footnote B.4.227. PI2FD: Packed Doubleword Integer to Single-Precision FP Convert}
+{\footnote browse:00447}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PI2FD}
\keepn\f2\b\fs30\sb60\sa60
B.4.227. {\f1 PI2FD}: Packed Doubleword Integer to Single-Precision FP Convert
\par\pard\plain\sb120
\keep\f1\sb120
PI2FD mm1,mm2/m64             ; 0F 0F /r 0D          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PF2ID} converts two signed 32-bit integers in the source operand to 
single-precision FP values, using truncation of significant digits, and 
stores them in the destination operand.
\par\sb120
\page
#{\footnote section_b_4_228}
${\footnote B.4.228. PF2IW: Packed Word Integer to Single-Precision FP Convert}
+{\footnote browse:00448}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PF2IW}
\keepn\f2\b\fs30\sb60\sa60
B.4.228. {\f1 PF2IW}: Packed Word Integer to Single-Precision FP Convert
\par\pard\plain\sb120
\keep\f1\sb120
PI2FW mm1,mm2/m64             ; 0F 0F /r 0C          [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PF2IW} converts two signed 16-bit integers in the source operand to 
single-precision FP values, and stores them in the destination operand. The 
input values are in the low word of each doubleword.
\par\sb120
\page
#{\footnote section_b_4_229}
${\footnote B.4.229. PINSRW: Insert Word}
+{\footnote browse:00449}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PINSRW}
\keepn\f2\b\fs30\sb60\sa60
B.4.229. {\f1 PINSRW}: Insert Word
\par\pard\plain\sb120
\keep\f1\sb120
PINSRW mm,r16/r32/m16,imm8    ;0F C4 /r ib      [KATMAI,MMX] \par\sb0
PINSRW xmm,r16/r32/m16,imm8   ;66 0F C4 /r ib   [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PINSRW} loads a word from a 16-bit register (or the low half of a 
32-bit register), or from memory, and loads it to the word position in the 
destination register, pointed at by the count operand (third operand). If 
the destination is an {\f1 MMX} register, the low two bits of the count 
byte are used, if it is an {\f1 XMM} register the low 3 bits are used. The 
insertion is done in such a way that the other words from the destination 
register are left untouched.
\par\sb120
\page
#{\footnote section_b_4_230}
${\footnote B.4.230. PMACHRIW: Packed Multiply and Accumulate with Rounding}
+{\footnote browse:00450}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMACHRIW}
\keepn\f2\b\fs30\sb60\sa60
B.4.230. {\f1 PMACHRIW}: Packed Multiply and Accumulate with Rounding
\par\pard\plain\sb120
\keep\f1\sb120
PMACHRIW mm,m64               ; 0F 5E /r             [CYRIX,MMX]\par\sb0
\pard\f0\sb120
{\f1 PMACHRIW} takes two packed 16-bit integer inputs, multiplies the 
values in the inputs, rounds on bit 15 of each result, then adds bits 15-30 
of each result to the corresponding position of the {\i implied} 
destination register.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dstI[0-15]  := dstI[0-15]  + (mm[0-15] *m64[0-15] \par\sb0
                                          + 0x00004000)[15-30], \par\sb0
   dstI[16-31] := dstI[16-31] + (mm[16-31]*m64[16-31] \par\sb0
                                          + 0x00004000)[15-30], \par\sb0
   dstI[32-47] := dstI[32-47] + (mm[32-47]*m64[32-47] \par\sb0
                                          + 0x00004000)[15-30], \par\sb0
   dstI[48-63] := dstI[48-63] + (mm[48-63]*m64[48-63] \par\sb0
                                          + 0x00004000)[15-30].\par\sb0
\pard\f0\sb120
Note that {\f1 PMACHRIW} cannot take a register as its second source 
operand.
\par\sb120
\page
#{\footnote section_b_4_231}
${\footnote B.4.231. PMADDWD: MMX Packed Multiply and Add}
+{\footnote browse:00451}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMADDWD}
\keepn\f2\b\fs30\sb60\sa60
B.4.231. {\f1 PMADDWD}: MMX Packed Multiply and Add
\par\pard\plain\sb120
\keep\f1\sb120
PMADDWD mm1,mm2/m64           ; 0F F5 /r             [PENT,MMX] \par\sb0
PMADDWD xmm1,xmm2/m128        ; 66 0F F5 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMADDWD} treats its two inputs as vectors of signed words. It 
multiplies corresponding elements of the two operands, giving doubleword 
results. These are then added together in pairs and stored in the 
destination operand.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[0-31]   := (dst[0-15] * src[0-15]) \par\sb0
                               + (dst[16-31] * src[16-31]); \par\sb0
   dst[32-63]  := (dst[32-47] * src[32-47]) \par\sb0
                               + (dst[48-63] * src[48-63]);\par\sb0
\pard\f0\sb120
The following apply to the {\f1 SSE} version of the instruction:
\par\sb120
\keep\f1\sb120
   dst[64-95]  := (dst[64-79] * src[64-79]) \par\sb0
                               + (dst[80-95] * src[80-95]); \par\sb0
   dst[96-127] := (dst[96-111] * src[96-111]) \par\sb0
                               + (dst[112-127] * src[112-127]).\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_232}
${\footnote B.4.232. PMAGW: MMX Packed Magnitude}
+{\footnote browse:00452}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMAGW}
\keepn\f2\b\fs30\sb60\sa60
B.4.232. {\f1 PMAGW}: MMX Packed Magnitude
\par\pard\plain\sb120
\keep\f1\sb120
PMAGW mm1,mm2/m64             ; 0F 52 /r             [CYRIX,MMX]\par\sb0
\pard\f0\sb120
{\f1 PMAGW}, specific to the Cyrix MMX extensions, treats both its operands 
as vectors of four signed words. It compares the absolute values of the 
words in corresponding positions, and sets each word of the destination 
(first) operand to whichever of the two words in that position had the 
larger absolute value.
\par\sb120
\page
#{\footnote section_b_4_233}
${\footnote B.4.233. PMAXSW: Packed Signed Integer Word Maximum}
+{\footnote browse:00453}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMAXSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.233. {\f1 PMAXSW}: Packed Signed Integer Word Maximum
\par\pard\plain\sb120
\keep\f1\sb120
PMAXSW mm1,mm2/m64            ; 0F EE /r        [KATMAI,MMX] \par\sb0
PMAXSW xmm1,xmm2/m128         ; 66 0F EE /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMAXSW} compares each pair of words in the two source operands, and 
for each pair it stores the maximum value in the destination register.
\par\sb120
\page
#{\footnote section_b_4_234}
${\footnote B.4.234. PMAXUB: Packed Unsigned Integer Byte Maximum}
+{\footnote browse:00454}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMAXUB}
\keepn\f2\b\fs30\sb60\sa60
B.4.234. {\f1 PMAXUB}: Packed Unsigned Integer Byte Maximum
\par\pard\plain\sb120
\keep\f1\sb120
PMAXUB mm1,mm2/m64            ; 0F DE /r        [KATMAI,MMX] \par\sb0
PMAXUB xmm1,xmm2/m128         ; 66 0F DE /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMAXUB} compares each pair of bytes in the two source operands, and 
for each pair it stores the maximum value in the destination register.
\par\sb120
\page
#{\footnote section_b_4_235}
${\footnote B.4.235. PMINSW: Packed Signed Integer Word Minimum}
+{\footnote browse:00455}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMINSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.235. {\f1 PMINSW}: Packed Signed Integer Word Minimum
\par\pard\plain\sb120
\keep\f1\sb120
PMINSW mm1,mm2/m64            ; 0F EA /r        [KATMAI,MMX] \par\sb0
PMINSW xmm1,xmm2/m128         ; 66 0F EA /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMINSW} compares each pair of words in the two source operands, and 
for each pair it stores the minimum value in the destination register.
\par\sb120
\page
#{\footnote section_b_4_236}
${\footnote B.4.236. PMINUB: Packed Unsigned Integer Byte Minimum}
+{\footnote browse:00456}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMINUB}
\keepn\f2\b\fs30\sb60\sa60
B.4.236. {\f1 PMINUB}: Packed Unsigned Integer Byte Minimum
\par\pard\plain\sb120
\keep\f1\sb120
PMINUB mm1,mm2/m64            ; 0F DA /r        [KATMAI,MMX] \par\sb0
PMINUB xmm1,xmm2/m128         ; 66 0F DA /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMINUB} compares each pair of bytes in the two source operands, and 
for each pair it stores the minimum value in the destination register.
\par\sb120
\page
#{\footnote section_b_4_237}
${\footnote B.4.237. PMOVMSKB: Move Byte Mask To Integer}
+{\footnote browse:00457}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMOVMSKB}
\keepn\f2\b\fs30\sb60\sa60
B.4.237. {\f1 PMOVMSKB}: Move Byte Mask To Integer
\par\pard\plain\sb120
\keep\f1\sb120
PMOVMSKB reg32,mm             ; 0F D7 /r        [KATMAI,MMX] \par\sb0
PMOVMSKB reg32,xmm            ; 66 0F D7 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMOVMSKB} returns an 8-bit or 16-bit mask formed of the most 
significant bits of each byte of source operand (8-bits for an {\f1 MMX} 
register, 16-bits for an {\f1 XMM} register).
\par\sb120
\page
#{\footnote section_b_4_238}
${\footnote B.4.238. PMULHRWC, PMULHRIW: Multiply Packed 16-bit Integers With Rounding, and Store High Word}
+{\footnote browse:00458}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMULHRIW;
PMULHRWC}
\keepn\f2\b\fs30\sb60\sa60
B.4.238. {\f1 PMULHRWC}, {\f1 PMULHRIW}: Multiply Packed 16-bit Integers With Rounding, and Store High Word
\par\pard\plain\sb120
\keep\f1\sb120
PMULHRWC mm1,mm2/m64         ; 0F 59 /r              [CYRIX,MMX] \par\sb0
PMULHRIW mm1,mm2/m64         ; 0F 5D /r              [CYRIX,MMX]\par\sb0
\pard\f0\sb120
These instructions take two packed 16-bit integer inputs, multiply the 
values in the inputs, round on bit 15 of each result, then store bits 15-30 
of each result to the corresponding position of the destination register.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 PMULHRWC}, the destination is the first source operand.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
For {\f1 PMULHRIW}, the destination is an implied register (worked out as 
described for {\f1 PADDSIW} ({\uldb section B.4.200}{\v section_b_4_200})).
\par\pard\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[0-15]  := (src1[0-15] *src2[0-15]  + 0x00004000)[15-30] \par\sb0
   dst[16-31] := (src1[16-31]*src2[16-31] + 0x00004000)[15-30] \par\sb0
   dst[32-47] := (src1[32-47]*src2[32-47] + 0x00004000)[15-30] \par\sb0
   dst[48-63] := (src1[48-63]*src2[48-63] + 0x00004000)[15-30]\par\sb0
\pard\f0\sb120
See also {\f1 PMULHRWA} ({\uldb section B.4.239}{\v section_b_4_239}) for a 
3DNow! version of this instruction.
\par\sb120
\page
#{\footnote section_b_4_239}
${\footnote B.4.239. PMULHRWA: Multiply Packed 16-bit Integers With Rounding, and Store High Word}
+{\footnote browse:00459}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMULHRWA}
\keepn\f2\b\fs30\sb60\sa60
B.4.239. {\f1 PMULHRWA}: Multiply Packed 16-bit Integers With Rounding, and Store High Word
\par\pard\plain\sb120
\keep\f1\sb120
PMULHRWA mm1,mm2/m64          ; 0F 0F /r B7     [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PMULHRWA} takes two packed 16-bit integer inputs, multiplies the 
values in the inputs, rounds on bit 16 of each result, then stores bits 
16-31 of each result to the corresponding position of the destination 
register.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[0-15]  := (src1[0-15] *src2[0-15]  + 0x00008000)[16-31]; \par\sb0
   dst[16-31] := (src1[16-31]*src2[16-31] + 0x00008000)[16-31]; \par\sb0
   dst[32-47] := (src1[32-47]*src2[32-47] + 0x00008000)[16-31]; \par\sb0
   dst[48-63] := (src1[48-63]*src2[48-63] + 0x00008000)[16-31].\par\sb0
\pard\f0\sb120
See also {\f1 PMULHRWC} ({\uldb section B.4.238}{\v section_b_4_238}) for a 
Cyrix version of this instruction.
\par\sb120
\page
#{\footnote section_b_4_240}
${\footnote B.4.240. PMULHUW: Multiply Packed 16-bit Integers, and Store High Word}
+{\footnote browse:00460}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMULHUW}
\keepn\f2\b\fs30\sb60\sa60
B.4.240. {\f1 PMULHUW}: Multiply Packed 16-bit Integers, and Store High Word
\par\pard\plain\sb120
\keep\f1\sb120
PMULHUW mm1,mm2/m64           ; 0F E4 /r        [KATMAI,MMX] \par\sb0
PMULHUW xmm1,xmm2/m128        ; 66 0F E4 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMULHUW} takes two packed unsigned 16-bit integer inputs, multiplies 
the values in the inputs, then stores bits 16-31 of each result to the 
corresponding position of the destination register.
\par\sb120
\page
#{\footnote section_b_4_241}
${\footnote B.4.241. PMULHW, PMULLW: Multiply Packed 16-bit Integers, and Store}
+{\footnote browse:00461}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMULHW;
PMULLW}
\keepn\f2\b\fs30\sb60\sa60
B.4.241. {\f1 PMULHW}, {\f1 PMULLW}: Multiply Packed 16-bit Integers, and Store
\par\pard\plain\sb120
\keep\f1\sb120
PMULHW mm1,mm2/m64            ; 0F E5 /r             [PENT,MMX] \par\sb0
PMULLW mm1,mm2/m64            ; 0F D5 /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PMULHW xmm1,xmm2/m128         ; 66 0F E5 /r     [WILLAMETTE,SSE2] \par\sb0
PMULLW xmm1,xmm2/m128         ; 66 0F D5 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMULxW} takes two packed unsigned 16-bit integer inputs, and 
multiplies the values in the inputs, forming doubleword results.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PMULHW} then stores the top 16 bits of each doubleword in the 
destination (first) operand;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PMULLW} stores the bottom 16 bits of each doubleword in the 
destination operand.
\par\pard\sb120
\page
#{\footnote section_b_4_242}
${\footnote B.4.242. PMULUDQ: Multiply Packed Unsigned 32-bit Integers, and Store.}
+{\footnote browse:00462}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMULUDQ}
\keepn\f2\b\fs30\sb60\sa60
B.4.242. {\f1 PMULUDQ}: Multiply Packed Unsigned 32-bit Integers, and Store.
\par\pard\plain\sb120
\keep\f1\sb120
PMULUDQ mm1,mm2/m64           ; 0F F4 /r        [WILLAMETTE,SSE2] \par\sb0
PMULUDQ xmm1,xmm2/m128        ; 66 0F F4 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PMULUDQ} takes two packed unsigned 32-bit integer inputs, and 
multiplies the values in the inputs, forming quadword results. The source 
is either an unsigned doubleword in the low doubleword of a 64-bit operand, 
or it's two unsigned doublewords in the first and third doublewords of a 
128-bit operand. This produces either one or two 64-bit results, which are 
stored in the respective quadword locations of the destination register.
\par\sb120
The operation is:
\par\sb120
\keep\f1\sb120
   dst[0-63]   := dst[0-31]  * src[0-31]; \par\sb0
   dst[64-127] := dst[64-95] * src[64-95].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_243}
${\footnote B.4.243. PMVccZB: MMX Packed Conditional Move}
+{\footnote browse:00463}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PMVccZB}
\keepn\f2\b\fs30\sb60\sa60
B.4.243. {\f1 PMVccZB}: MMX Packed Conditional Move
\par\pard\plain\sb120
\keep\f1\sb120
PMVZB mmxreg,mem64            ; 0F 58 /r             [CYRIX,MMX] \par\sb0
PMVNZB mmxreg,mem64           ; 0F 5A /r             [CYRIX,MMX] \par\sb0
PMVLZB mmxreg,mem64           ; 0F 5B /r             [CYRIX,MMX] \par\sb0
PMVGEZB mmxreg,mem64          ; 0F 5C /r             [CYRIX,MMX]\par\sb0
\pard\f0\sb120
These instructions, specific to the Cyrix MMX extensions, perform parallel 
conditional moves. The two input operands are treated as vectors of eight 
bytes. Each byte of the destination (first) operand is either written from 
the corresponding byte of the source (second) operand, or left alone, 
depending on the value of the byte in the {\i implied} operand (specified 
in the same way as {\f1 PADDSIW}, in {\uldb section 
B.4.200}{\v section_b_4_200}).
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PMVZB} performs each move if the corresponding byte in the implied 
operand is zero;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PMVNZB} moves if the byte is non-zero;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PMVLZB} moves if the byte is less than zero;
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PMVGEZB} moves if the byte is greater than or equal to zero.
\par\pard\sb120
Note that these instructions cannot take a register as their second source 
operand.
\par\sb120
\page
#{\footnote section_b_4_244}
${\footnote B.4.244. POP: Pop Data from Stack}
+{\footnote browse:00464}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
o16;
o32;
POP}
\keepn\f2\b\fs30\sb60\sa60
B.4.244. {\f1 POP}: Pop Data from Stack
\par\pard\plain\sb120
\keep\f1\sb120
POP reg16                     ; o16 58+r             [8086] \par\sb0
POP reg32                     ; o32 58+r             [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
POP r/m16                     ; o16 8F /0            [8086] \par\sb0
POP r/m32                     ; o32 8F /0            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
POP CS                        ; 0F                   [8086,UNDOC] \par\sb0
POP DS                        ; 1F                   [8086] \par\sb0
POP ES                        ; 07                   [8086] \par\sb0
POP SS                        ; 17                   [8086] \par\sb0
POP FS                        ; 0F A1                [386] \par\sb0
POP GS                        ; 0F A9                [386]\par\sb0
\pard\f0\sb120
{\f1 POP} loads a value from the stack (from {\f1 [SS:SP]} or 
{\f1 [SS:ESP]}) and then increments the stack pointer.
\par\sb120
The address-size attribute of the instruction determines whether {\f1 SP} 
or {\f1 ESP} is used as the stack pointer: to deliberately override the 
default given by the {\f1 BITS} setting, you can use an {\f1 a16} or 
{\f1 a32} prefix.
\par\sb120
The operand-size attribute of the instruction determines whether the stack 
pointer is incremented by 2 or 4: this means that segment register pops in 
{\f1 BITS\'A032} mode will pop 4 bytes off the stack and discard the upper 
two of them. If you need to override that, you can use an {\f1 o16} or 
{\f1 o32} prefix.
\par\sb120
The above opcode listings give two forms for general-purpose register pop 
instructions: for example, {\f1 POP\'A0BX} has the two forms {\f1 5B} and 
{\f1 8F\'A0C3}. NASM will always generate the shorter form when given 
{\f1 POP\'A0BX}. NDISASM will disassemble both.
\par\sb120
{\f1 POP\'A0CS} is not a documented instruction, and is not supported on 
any processor above the 8086 (since they use {\f1 0Fh} as an opcode prefix 
for instruction set extensions). However, at least some 8086 processors do 
support it, and so NASM generates it for completeness.
\par\sb120
\page
#{\footnote section_b_4_245}
${\footnote B.4.245. POPAx: Pop All General-Purpose Registers}
+{\footnote browse:00465}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote POPAx}
\keepn\f2\b\fs30\sb60\sa60
B.4.245. {\f1 POPAx}: Pop All General-Purpose Registers
\par\pard\plain\sb120
\keep\f1\sb120
POPA                          ; 61                   [186] \par\sb0
POPAW                         ; o16 61               [186] \par\sb0
POPAD                         ; o32 61               [386]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 POPAW} pops a word from the stack into each of, successively, 
{\f1 DI}, {\f1 SI}, {\f1 BP}, nothing (it discards a word from the stack 
which was a placeholder for {\f1 SP}), {\f1 BX}, {\f1 DX}, {\f1 CX} and 
{\f1 AX}. It is intended to reverse the operation of {\f1 PUSHAW} (see 
{\uldb section B.4.264}{\v section_b_4_264}), but it ignores the value for 
{\f1 SP} that was pushed on the stack by {\f1 PUSHAW}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 POPAD} pops twice as much data, and places the results in {\f1 EDI}, 
{\f1 ESI}, {\f1 EBP}, nothing (placeholder for {\f1 ESP}), {\f1 EBX}, 
{\f1 EDX}, {\f1 ECX} and {\f1 EAX}. It reverses the operation of 
{\f1 PUSHAD}.
\par\pard\sb120
{\f1 POPA} is an alias mnemonic for either {\f1 POPAW} or {\f1 POPAD}, 
depending on the current {\f1 BITS} setting.
\par\sb120
Note that the registers are popped in reverse order of their numeric values 
in opcodes (see {\uldb section B.2.1}{\v section_b_2_1}).
\par\sb120
\page
#{\footnote section_b_4_246}
${\footnote B.4.246. POPFx: Pop Flags Register}
+{\footnote browse:00466}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote POPFx}
\keepn\f2\b\fs30\sb60\sa60
B.4.246. {\f1 POPFx}: Pop Flags Register
\par\pard\plain\sb120
\keep\f1\sb120
POPF                          ; 9D                   [8086] \par\sb0
POPFW                         ; o16 9D               [8086] \par\sb0
POPFD                         ; o32 9D               [386]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 POPFW} pops a word from the stack and stores it in the bottom 16 bits 
of the flags register (or the whole flags register, on processors below a 
386).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 POPFD} pops a doubleword and stores it in the entire flags register.
\par\pard\sb120
{\f1 POPF} is an alias mnemonic for either {\f1 POPFW} or {\f1 POPFD}, 
depending on the current {\f1 BITS} setting.
\par\sb120
See also {\f1 PUSHF} ({\uldb section B.4.265}{\v section_b_4_265}).
\par\sb120
\page
#{\footnote section_b_4_247}
${\footnote B.4.247. POR: MMX Bitwise OR}
+{\footnote browse:00467}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote POR}
\keepn\f2\b\fs30\sb60\sa60
B.4.247. {\f1 POR}: MMX Bitwise OR
\par\pard\plain\sb120
\keep\f1\sb120
POR mm1,mm2/m64               ; 0F EB /r             [PENT,MMX] \par\sb0
POR xmm1,xmm2/m128            ; 66 0F EB /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 POR} performs a bitwise OR operation between its two operands (i.e. 
each bit of the result is 1 if and only if at least one of the 
corresponding bits of the two inputs was 1), and stores the result in the 
destination (first) operand.
\par\sb120
\page
#{\footnote section_b_4_248}
${\footnote B.4.248. PREFETCH: Prefetch Data Into Caches}
+{\footnote browse:00468}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PREFETCH}
\keepn\f2\b\fs30\sb60\sa60
B.4.248. {\f1 PREFETCH}: Prefetch Data Into Caches
\par\pard\plain\sb120
\keep\f1\sb120
PREFETCH mem8                 ; 0F 0D /0             [PENT,3DNOW] \par\sb0
PREFETCHW mem8                ; 0F 0D /1             [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PREFETCH} and {\f1 PREFETCHW} fetch the line of data from memory that 
contains the specified byte. {\f1 PREFETCHW} performs differently on the 
Athlon to earlier processors.
\par\sb120
For more details, see the 3DNow! Technology Manual.
\par\sb120
\page
#{\footnote section_b_4_249}
${\footnote B.4.249. PREFETCHh: Prefetch Data Into Caches    }
+{\footnote browse:00469}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PREFETCHh;
PREFETCHNTA;
PREFETCHT0;
PREFETCHT1;
PREFETCHT2}
\keepn\f2\b\fs30\sb60\sa60
B.4.249. {\f1 PREFETCHh}: Prefetch Data Into Caches    
\par\pard\plain\sb120
\keep\f1\sb120
PREFETCHNTA m8                ; 0F 18 /0        [KATMAI] \par\sb0
PREFETCHT0 m8                 ; 0F 18 /1        [KATMAI] \par\sb0
PREFETCHT1 m8                 ; 0F 18 /2        [KATMAI] \par\sb0
PREFETCHT2 m8                 ; 0F 18 /3        [KATMAI]\par\sb0
\pard\f0\sb120
The {\f1 PREFETCHh} instructions fetch the line of data from memory that 
contains the specified byte. It is placed in the cache according to rules 
specified by locality hints {\f1 h}:
\par\sb120
The hints are:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 T0} (temporal data) \'96 prefetch data into all levels of the cache 
hierarchy.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 T1} (temporal data with respect to first level cache) \'96 prefetch 
data into level 2 cache and higher.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 T2} (temporal data with respect to second level cache) \'96 prefetch 
data into level 2 cache and higher.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 NTA} (non-temporal data with respect to all cache levels) \'96 
prefetch data into non-temporal cache structure and into a location close 
to the processor, minimizing cache pollution.
\par\pard\sb120
Note that this group of instructions doesn't provide a guarantee that the 
data will be in the cache when it is needed. For more details, see the 
Intel IA32 Software Developer Manual, Volume 2.
\par\sb120
\page
#{\footnote section_b_4_250}
${\footnote B.4.250. PSADBW: Packed Sum of Absolute Differences}
+{\footnote browse:00470}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSADBW}
\keepn\f2\b\fs30\sb60\sa60
B.4.250. {\f1 PSADBW}: Packed Sum of Absolute Differences
\par\pard\plain\sb120
\keep\f1\sb120
PSADBW mm1,mm2/m64            ; 0F F6 /r        [KATMAI,MMX] \par\sb0
PSADBW xmm1,xmm2/m128         ; 66 0F F6 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSADBW} The PSADBW instruction computes the absolute value of the 
difference of the packed unsigned bytes in the two source operands. These 
differences are then summed to produce a word result in the lower 16-bit 
field of the destination register; the rest of the register is cleared. The 
destination operand is an {\f1 MMX} or an {\f1 XMM} register. The source 
operand can either be a register or a memory operand.
\par\sb120
\page
#{\footnote section_b_4_251}
${\footnote B.4.251. PSHUFD: Shuffle Packed Doublewords}
+{\footnote browse:00471}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSHUFD}
\keepn\f2\b\fs30\sb60\sa60
B.4.251. {\f1 PSHUFD}: Shuffle Packed Doublewords
\par\pard\plain\sb120
\keep\f1\sb120
PSHUFD xmm1,xmm2/m128,imm8    ; 66 0F 70 /r ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSHUFD} shuffles the doublewords in the source (second) operand 
according to the encoding specified by imm8, and stores the result in the 
destination (first) operand.
\par\sb120
Bits 0 and 1 of imm8 encode the source position of the doubleword to be 
copied to position 0 in the destination operand. Bits 2 and 3 encode for 
position 1, bits 4 and 5 encode for position 2, and bits 6 and 7 encode for 
position 3. For example, an encoding of 10 in bits 0 and 1 of imm8 
indicates that the doubleword at bits 64-95 of the source operand will be 
copied to bits 0-31 of the destination.
\par\sb120
\page
#{\footnote section_b_4_252}
${\footnote B.4.252. PSHUFHW: Shuffle Packed High Words}
+{\footnote browse:00472}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSHUFHW}
\keepn\f2\b\fs30\sb60\sa60
B.4.252. {\f1 PSHUFHW}: Shuffle Packed High Words
\par\pard\plain\sb120
\keep\f1\sb120
PSHUFHW xmm1,xmm2/m128,imm8   ; F3 0F 70 /r ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSHUFW} shuffles the words in the high quadword of the source (second) 
operand according to the encoding specified by imm8, and stores the result 
in the high quadword of the destination (first) operand.
\par\sb120
The operation of this instruction is similar to the {\f1 PSHUFW} 
instruction, except that the source and destination are the top quadword of 
a 128-bit operand, instead of being 64-bit operands. The low quadword is 
copied from the source to the destination without any changes.
\par\sb120
\page
#{\footnote section_b_4_253}
${\footnote B.4.253. PSHUFLW: Shuffle Packed Low Words}
+{\footnote browse:00473}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSHUFLW}
\keepn\f2\b\fs30\sb60\sa60
B.4.253. {\f1 PSHUFLW}: Shuffle Packed Low Words
\par\pard\plain\sb120
\keep\f1\sb120
PSHUFLW xmm1,xmm2/m128,imm8   ; F2 0F 70 /r ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSHUFLW} shuffles the words in the low quadword of the source (second) 
operand according to the encoding specified by imm8, and stores the result 
in the low quadword of the destination (first) operand.
\par\sb120
The operation of this instruction is similar to the {\f1 PSHUFW} 
instruction, except that the source and destination are the low quadword of 
a 128-bit operand, instead of being 64-bit operands. The high quadword is 
copied from the source to the destination without any changes.
\par\sb120
\page
#{\footnote section_b_4_254}
${\footnote B.4.254. PSHUFW: Shuffle Packed Words}
+{\footnote browse:00474}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSHUFW}
\keepn\f2\b\fs30\sb60\sa60
B.4.254. {\f1 PSHUFW}: Shuffle Packed Words
\par\pard\plain\sb120
\keep\f1\sb120
PSHUFW mm1,mm2/m64,imm8       ; 0F 70 /r ib     [KATMAI,MMX]\par\sb0
\pard\f0\sb120
{\f1 PSHUFW} shuffles the words in the source (second) operand according to 
the encoding specified by imm8, and stores the result in the destination 
(first) operand.
\par\sb120
Bits 0 and 1 of imm8 encode the source position of the word to be copied to 
position 0 in the destination operand. Bits 2 and 3 encode for position 1, 
bits 4 and 5 encode for position 2, and bits 6 and 7 encode for position 3. 
For example, an encoding of 10 in bits 0 and 1 of imm8 indicates that the 
word at bits 32-47 of the source operand will be copied to bits 0-15 of the 
destination.
\par\sb120
\page
#{\footnote section_b_4_255}
${\footnote B.4.255. PSLLx: Packed Data Bit Shift Left Logical}
+{\footnote browse:00475}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSLLx}
\keepn\f2\b\fs30\sb60\sa60
B.4.255. {\f1 PSLLx}: Packed Data Bit Shift Left Logical
\par\pard\plain\sb120
\keep\f1\sb120
PSLLW mm1,mm2/m64             ; 0F F1 /r             [PENT,MMX] \par\sb0
PSLLW mm,imm8                 ; 0F 71 /6 ib          [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSLLW xmm1,xmm2/m128          ; 66 0F F1 /r     [WILLAMETTE,SSE2] \par\sb0
PSLLW xmm,imm8                ; 66 0F 71 /6 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSLLD mm1,mm2/m64             ; 0F F2 /r             [PENT,MMX] \par\sb0
PSLLD mm,imm8                 ; 0F 72 /6 ib          [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSLLD xmm1,xmm2/m128          ; 66 0F F2 /r     [WILLAMETTE,SSE2] \par\sb0
PSLLD xmm,imm8                ; 66 0F 72 /6 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSLLQ mm1,mm2/m64             ; 0F F3 /r             [PENT,MMX] \par\sb0
PSLLQ mm,imm8                 ; 0F 73 /6 ib          [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSLLQ xmm1,xmm2/m128          ; 66 0F F3 /r     [WILLAMETTE,SSE2] \par\sb0
PSLLQ xmm,imm8                ; 66 0F 73 /6 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSLLDQ xmm1,imm8              ; 66 0F 73 /7 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSLLx} performs logical left shifts of the data elements in the 
destination (first) operand, moving each bit in the separate elements left 
by the number of bits specified in the source (second) operand, clearing 
the low-order bits as they are vacated. {\f1 PSLLDQ} shifts bytes, not 
bits.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSLLW} shifts word sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSLLD} shifts doubleword sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSLLQ} shifts quadword sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSLLDQ} shifts double quadword sized elements.
\par\pard\sb120
\page
#{\footnote section_b_4_256}
${\footnote B.4.256. PSRAx: Packed Data Bit Shift Right Arithmetic}
+{\footnote browse:00476}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSRAx}
\keepn\f2\b\fs30\sb60\sa60
B.4.256. {\f1 PSRAx}: Packed Data Bit Shift Right Arithmetic
\par\pard\plain\sb120
\keep\f1\sb120
PSRAW mm1,mm2/m64             ; 0F E1 /r             [PENT,MMX] \par\sb0
PSRAW mm,imm8                 ; 0F 71 /4 ib          [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRAW xmm1,xmm2/m128          ; 66 0F E1 /r     [WILLAMETTE,SSE2] \par\sb0
PSRAW xmm,imm8                ; 66 0F 71 /4 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRAD mm1,mm2/m64             ; 0F E2 /r             [PENT,MMX] \par\sb0
PSRAD mm,imm8                 ; 0F 72 /4 ib          [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRAD xmm1,xmm2/m128          ; 66 0F E2 /r     [WILLAMETTE,SSE2] \par\sb0
PSRAD xmm,imm8                ; 66 0F 72 /4 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSRAx} performs arithmetic right shifts of the data elements in the 
destination (first) operand, moving each bit in the separate elements right 
by the number of bits specified in the source (second) operand, setting the 
high-order bits to the value of the original sign bit.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSRAW} shifts word sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSRAD} shifts doubleword sized elements.
\par\pard\sb120
\page
#{\footnote section_b_4_257}
${\footnote B.4.257. PSRLx: Packed Data Bit Shift Right Logical}
+{\footnote browse:00477}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSRLx}
\keepn\f2\b\fs30\sb60\sa60
B.4.257. {\f1 PSRLx}: Packed Data Bit Shift Right Logical
\par\pard\plain\sb120
\keep\f1\sb120
PSRLW mm1,mm2/m64             ; 0F D1 /r             [PENT,MMX] \par\sb0
PSRLW mm,imm8                 ; 0F 71 /2 ib          [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRLW xmm1,xmm2/m128          ; 66 0F D1 /r     [WILLAMETTE,SSE2] \par\sb0
PSRLW xmm,imm8                ; 66 0F 71 /2 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRLD mm1,mm2/m64             ; 0F D2 /r             [PENT,MMX] \par\sb0
PSRLD mm,imm8                 ; 0F 72 /2 ib          [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRLD xmm1,xmm2/m128          ; 66 0F D2 /r     [WILLAMETTE,SSE2] \par\sb0
PSRLD xmm,imm8                ; 66 0F 72 /2 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRLQ mm1,mm2/m64             ; 0F D3 /r             [PENT,MMX] \par\sb0
PSRLQ mm,imm8                 ; 0F 73 /2 ib          [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRLQ xmm1,xmm2/m128          ; 66 0F D3 /r     [WILLAMETTE,SSE2] \par\sb0
PSRLQ xmm,imm8                ; 66 0F 73 /2 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSRLDQ xmm1,imm8              ; 66 0F 73 /3 ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSRLx} performs logical right shifts of the data elements in the 
destination (first) operand, moving each bit in the separate elements right 
by the number of bits specified in the source (second) operand, clearing 
the high-order bits as they are vacated. {\f1 PSRLDQ} shifts bytes, not 
bits.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSRLW} shifts word sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSRLD} shifts doubleword sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSRLQ} shifts quadword sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSRLDQ} shifts double quadword sized elements.
\par\pard\sb120
\page
#{\footnote section_b_4_258}
${\footnote B.4.258. PSUBx: Subtract Packed Integers}
+{\footnote browse:00478}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSUBx}
\keepn\f2\b\fs30\sb60\sa60
B.4.258. {\f1 PSUBx}: Subtract Packed Integers
\par\pard\plain\sb120
\keep\f1\sb120
PSUBB mm1,mm2/m64             ; 0F F8 /r             [PENT,MMX] \par\sb0
PSUBW mm1,mm2/m64             ; 0F F9 /r             [PENT,MMX] \par\sb0
PSUBD mm1,mm2/m64             ; 0F FA /r             [PENT,MMX] \par\sb0
PSUBQ mm1,mm2/m64             ; 0F FB /r        [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSUBB xmm1,xmm2/m128          ; 66 0F F8 /r     [WILLAMETTE,SSE2] \par\sb0
PSUBW xmm1,xmm2/m128          ; 66 0F F9 /r     [WILLAMETTE,SSE2] \par\sb0
PSUBD xmm1,xmm2/m128          ; 66 0F FA /r     [WILLAMETTE,SSE2] \par\sb0
PSUBQ xmm1,xmm2/m128          ; 66 0F FB /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSUBx} subtracts packed integers in the source operand from those in 
the destination operand. It doesn't differentiate between signed and 
unsigned integers, and doesn't set any of the flags.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSUBB} operates on byte sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSUBW} operates on word sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSUBD} operates on doubleword sized elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSUBQ} operates on quadword sized elements.
\par\pard\sb120
\page
#{\footnote section_b_4_259}
${\footnote B.4.259. PSUBSxx, PSUBUSx: Subtract Packed Integers With Saturation}
+{\footnote browse:00479}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSUBSxx;
PSUBUSx}
\keepn\f2\b\fs30\sb60\sa60
B.4.259. {\f1 PSUBSxx}, {\f1 PSUBUSx}: Subtract Packed Integers With Saturation
\par\pard\plain\sb120
\keep\f1\sb120
PSUBSB mm1,mm2/m64            ; 0F E8 /r             [PENT,MMX] \par\sb0
PSUBSW mm1,mm2/m64            ; 0F E9 /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSUBSB xmm1,xmm2/m128         ; 66 0F E8 /r     [WILLAMETTE,SSE2] \par\sb0
PSUBSW xmm1,xmm2/m128         ; 66 0F E9 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSUBUSB mm1,mm2/m64           ; 0F D8 /r             [PENT,MMX] \par\sb0
PSUBUSW mm1,mm2/m64           ; 0F D9 /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PSUBUSB xmm1,xmm2/m128        ; 66 0F D8 /r     [WILLAMETTE,SSE2] \par\sb0
PSUBUSW xmm1,xmm2/m128        ; 66 0F D9 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PSUBSx} and {\f1 PSUBUSx} subtracts packed integers in the source 
operand from those in the destination operand, and use saturation for 
results that are outside the range supported by the destination operand.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSUBSB} operates on signed bytes, and uses signed saturation on the 
results.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSUBSW} operates on signed words, and uses signed saturation on the 
results.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSUBUSB} operates on unsigned bytes, and uses signed saturation on the 
results.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PSUBUSW} operates on unsigned words, and uses signed saturation on the 
results.
\par\pard\sb120
\page
#{\footnote section_b_4_260}
${\footnote B.4.260. PSUBSIW: MMX Packed Subtract with Saturation to Implied Destination}
+{\footnote browse:00480}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSUBSIW}
\keepn\f2\b\fs30\sb60\sa60
B.4.260. {\f1 PSUBSIW}: MMX Packed Subtract with Saturation to Implied Destination
\par\pard\plain\sb120
\keep\f1\sb120
PSUBSIW mm1,mm2/m64           ; 0F 55 /r             [CYRIX,MMX]\par\sb0
\pard\f0\sb120
{\f1 PSUBSIW}, specific to the Cyrix extensions to the MMX instruction set, 
performs the same function as {\f1 PSUBSW}, except that the result is not 
placed in the register specified by the first operand, but instead in the 
implied destination register, specified as for {\f1 PADDSIW} 
({\uldb section B.4.200}{\v section_b_4_200}).
\par\sb120
\page
#{\footnote section_b_4_261}
${\footnote B.4.261. PSWAPD: Swap Packed Data }
+{\footnote browse:00481}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PSWAPD;
PSWAPW}
\keepn\f2\b\fs30\sb60\sa60
B.4.261. {\f1 PSWAPD}: Swap Packed Data 
\par\pard\plain\sb120
\keep\f1\sb120
PSWAPD mm1,mm2/m64            ; 0F 0F /r BB     [PENT,3DNOW]\par\sb0
\pard\f0\sb120
{\f1 PSWAPD} swaps the packed doublewords in the source operand, and stores 
the result in the destination operand.
\par\sb120
In the {\f1 K6\'AD2} and {\f1 K6\'ADIII} processors, this opcode uses the 
mnemonic {\f1 PSWAPW}, and it swaps the order of words when copying from 
the source to the destination.
\par\sb120
The operation in the {\f1 K6\'AD2} and {\f1 K6\'ADIII} processors is
\par\sb120
\keep\f1\sb120
   dst[0-15]  = src[48-63]; \par\sb0
   dst[16-31] = src[32-47]; \par\sb0
   dst[32-47] = src[16-31]; \par\sb0
   dst[48-63] = src[0-15].\par\sb0
\pard\f0\sb120
The operation in the {\f1 K6\'ADx+}, {\f1 ATHLON} and later processors is:
\par\sb120
\keep\f1\sb120
   dst[0-31]  = src[32-63]; \par\sb0
   dst[32-63] = src[0-31].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_262}
${\footnote B.4.262. PUNPCKxxx: Unpack and Interleave Data}
+{\footnote browse:00482}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PUNPCKxxx}
\keepn\f2\b\fs30\sb60\sa60
B.4.262. {\f1 PUNPCKxxx}: Unpack and Interleave Data
\par\pard\plain\sb120
\keep\f1\sb120
PUNPCKHBW mm1,mm2/m64         ; 0F 68 /r             [PENT,MMX] \par\sb0
PUNPCKHWD mm1,mm2/m64         ; 0F 69 /r             [PENT,MMX] \par\sb0
PUNPCKHDQ mm1,mm2/m64         ; 0F 6A /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PUNPCKHBW xmm1,xmm2/m128      ; 66 0F 68 /r     [WILLAMETTE,SSE2] \par\sb0
PUNPCKHWD xmm1,xmm2/m128      ; 66 0F 69 /r     [WILLAMETTE,SSE2] \par\sb0
PUNPCKHDQ xmm1,xmm2/m128      ; 66 0F 6A /r     [WILLAMETTE,SSE2] \par\sb0
PUNPCKHQDQ xmm1,xmm2/m128     ; 66 0F 6D /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PUNPCKLBW mm1,mm2/m32         ; 0F 60 /r             [PENT,MMX] \par\sb0
PUNPCKLWD mm1,mm2/m32         ; 0F 61 /r             [PENT,MMX] \par\sb0
PUNPCKLDQ mm1,mm2/m32         ; 0F 62 /r             [PENT,MMX]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PUNPCKLBW xmm1,xmm2/m128      ; 66 0F 60 /r     [WILLAMETTE,SSE2] \par\sb0
PUNPCKLWD xmm1,xmm2/m128      ; 66 0F 61 /r     [WILLAMETTE,SSE2] \par\sb0
PUNPCKLDQ xmm1,xmm2/m128      ; 66 0F 62 /r     [WILLAMETTE,SSE2] \par\sb0
PUNPCKLQDQ xmm1,xmm2/m128     ; 66 0F 6C /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PUNPCKxx} all treat their operands as vectors, and produce a new 
vector generated by interleaving elements from the two inputs. The 
{\f1 PUNPCKHxx} instructions start by throwing away the bottom half of each 
input operand, and the {\f1 PUNPCKLxx} instructions throw away the top 
half.
\par\sb120
The remaining elements, are then interleaved into the destination, 
alternating elements from the second (source) operand and the first 
(destination) operand: so the leftmost part of each element in the result 
always comes from the second operand, and the rightmost from the 
destination.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKxBW} works a byte at a time, producing word sized output 
elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKxWD} works a word at a time, producing doubleword sized output 
elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKxDQ} works a doubleword at a time, producing quadword sized 
output elements.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKxQDQ} works a quadword at a time, producing double quadword 
sized output elements.
\par\pard\sb120
So, for example, for {\f1 MMX} operands, if the first operand held 
{\f1 0x7A6A5A4A3A2A1A0A} and the second held {\f1 0x7B6B5B4B3B2B1B0B}, 
then:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKHBW} would return {\f1 0x7B7A6B6A5B5A4B4A}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKHWD} would return {\f1 0x7B6B7A6A5B4B5A4A}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKHDQ} would return {\f1 0x7B6B5B4B7A6A5A4A}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKLBW} would return {\f1 0x3B3A2B2A1B1A0B0A}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKLWD} would return {\f1 0x3B2B3A2A1B0B1A0A}.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUNPCKLDQ} would return {\f1 0x3B2B1B0B3A2A1A0A}.
\par\pard\sb120
\page
#{\footnote section_b_4_263}
${\footnote B.4.263. PUSH: Push Data on Stack}
+{\footnote browse:00483}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
o16;
o32;
PUSH;
register push}
\keepn\f2\b\fs30\sb60\sa60
B.4.263. {\f1 PUSH}: Push Data on Stack
\par\pard\plain\sb120
\keep\f1\sb120
PUSH reg16                    ; o16 50+r             [8086] \par\sb0
PUSH reg32                    ; o32 50+r             [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PUSH r/m16                    ; o16 FF /6            [8086] \par\sb0
PUSH r/m32                    ; o32 FF /6            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PUSH CS                       ; 0E                   [8086] \par\sb0
PUSH DS                       ; 1E                   [8086] \par\sb0
PUSH ES                       ; 06                   [8086] \par\sb0
PUSH SS                       ; 16                   [8086] \par\sb0
PUSH FS                       ; 0F A0                [386] \par\sb0
PUSH GS                       ; 0F A8                [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
PUSH imm8                     ; 6A ib                [186] \par\sb0
PUSH imm16                    ; o16 68 iw            [186] \par\sb0
PUSH imm32                    ; o32 68 id            [386]\par\sb0
\pard\f0\sb120
{\f1 PUSH} decrements the stack pointer ({\f1 SP} or {\f1 ESP}) by 2 or 4, 
and then stores the given value at {\f1 [SS:SP]} or {\f1 [SS:ESP]}.
\par\sb120
The address-size attribute of the instruction determines whether {\f1 SP} 
or {\f1 ESP} is used as the stack pointer: to deliberately override the 
default given by the {\f1 BITS} setting, you can use an {\f1 a16} or 
{\f1 a32} prefix.
\par\sb120
The operand-size attribute of the instruction determines whether the stack 
pointer is decremented by 2 or 4: this means that segment register pushes 
in {\f1 BITS\'A032} mode will push 4 bytes on the stack, of which the upper 
two are undefined. If you need to override that, you can use an {\f1 o16} 
or {\f1 o32} prefix.
\par\sb120
The above opcode listings give two forms for general-purpose register push 
instructions: for example, {\f1 PUSH\'A0BX} has the two forms {\f1 53} and 
{\f1 FF\'A0F3}. NASM will always generate the shorter form when given 
{\f1 PUSH\'A0BX}. NDISASM will disassemble both.
\par\sb120
Unlike the undocumented and barely supported {\f1 POP\'A0CS}, 
{\f1 PUSH\'A0CS} is a perfectly valid and sensible instruction, supported 
on all processors.
\par\sb120
The instruction {\f1 PUSH\'A0SP} may be used to distinguish an 8086 from 
later processors: on an 8086, the value of {\f1 SP} stored is the value it 
has {\i after} the push instruction, whereas on later processors it is the 
value {\i before} the push instruction.
\par\sb120
\page
#{\footnote section_b_4_264}
${\footnote B.4.264. PUSHAx: Push All General-Purpose Registers}
+{\footnote browse:00484}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PUSHAx}
\keepn\f2\b\fs30\sb60\sa60
B.4.264. {\f1 PUSHAx}: Push All General-Purpose Registers
\par\pard\plain\sb120
\keep\f1\sb120
PUSHA                         ; 60                   [186] \par\sb0
PUSHAD                        ; o32 60               [386] \par\sb0
PUSHAW                        ; o16 60               [186]\par\sb0
\pard\f0\sb120
{\f1 PUSHAW} pushes, in succession, {\f1 AX}, {\f1 CX}, {\f1 DX}, {\f1 BX}, 
{\f1 SP}, {\f1 BP}, {\f1 SI} and {\f1 DI} on the stack, decrementing the 
stack pointer by a total of 16.
\par\sb120
{\f1 PUSHAD} pushes, in succession, {\f1 EAX}, {\f1 ECX}, {\f1 EDX}, 
{\f1 EBX}, {\f1 ESP}, {\f1 EBP}, {\f1 ESI} and {\f1 EDI} on the stack, 
decrementing the stack pointer by a total of 32.
\par\sb120
In both cases, the value of {\f1 SP} or {\f1 ESP} pushed is its 
{\i original} value, as it had before the instruction was executed.
\par\sb120
{\f1 PUSHA} is an alias mnemonic for either {\f1 PUSHAW} or {\f1 PUSHAD}, 
depending on the current {\f1 BITS} setting.
\par\sb120
Note that the registers are pushed in order of their numeric values in 
opcodes (see {\uldb section B.2.1}{\v section_b_2_1}).
\par\sb120
See also {\f1 POPA} ({\uldb section B.4.245}{\v section_b_4_245}).
\par\sb120
\page
#{\footnote section_b_4_265}
${\footnote B.4.265. PUSHFx: Push Flags Register}
+{\footnote browse:00485}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PUSHFx}
\keepn\f2\b\fs30\sb60\sa60
B.4.265. {\f1 PUSHFx}: Push Flags Register
\par\pard\plain\sb120
\keep\f1\sb120
PUSHF                         ; 9C                   [8086] \par\sb0
PUSHFD                        ; o32 9C               [386] \par\sb0
PUSHFW                        ; o16 9C               [8086]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUSHFW} pops a word from the stack and stores it in the bottom 16 bits 
of the flags register (or the whole flags register, on processors below a 
386).
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 PUSHFD} pops a doubleword and stores it in the entire flags register.
\par\pard\sb120
{\f1 PUSHF} is an alias mnemonic for either {\f1 PUSHFW} or {\f1 PUSHFD}, 
depending on the current {\f1 BITS} setting.
\par\sb120
See also {\f1 POPF} ({\uldb section B.4.246}{\v section_b_4_246}).
\par\sb120
\page
#{\footnote section_b_4_266}
${\footnote B.4.266. PXOR: MMX Bitwise XOR}
+{\footnote browse:00486}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote PXOR}
\keepn\f2\b\fs30\sb60\sa60
B.4.266. {\f1 PXOR}: MMX Bitwise XOR
\par\pard\plain\sb120
\keep\f1\sb120
PXOR mm1,mm2/m64              ; 0F EF /r             [PENT,MMX] \par\sb0
PXOR xmm1,xmm2/m128           ; 66 0F EF /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 PXOR} performs a bitwise XOR operation between its two operands (i.e. 
each bit of the result is 1 if and only if exactly one of the corresponding 
bits of the two inputs was 1), and stores the result in the destination 
(first) operand.
\par\sb120
\page
#{\footnote section_b_4_267}
${\footnote B.4.267. RCL, RCR: Bitwise Rotate through Carry Bit}
+{\footnote browse:00487}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RCL;
RCR}
\keepn\f2\b\fs30\sb60\sa60
B.4.267. {\f1 RCL}, {\f1 RCR}: Bitwise Rotate through Carry Bit
\par\pard\plain\sb120
\keep\f1\sb120
RCL r/m8,1                    ; D0 /2                [8086] \par\sb0
RCL r/m8,CL                   ; D2 /2                [8086] \par\sb0
RCL r/m8,imm8                 ; C0 /2 ib             [186] \par\sb0
RCL r/m16,1                   ; o16 D1 /2            [8086] \par\sb0
RCL r/m16,CL                  ; o16 D3 /2            [8086] \par\sb0
RCL r/m16,imm8                ; o16 C1 /2 ib         [186] \par\sb0
RCL r/m32,1                   ; o32 D1 /2            [386] \par\sb0
RCL r/m32,CL                  ; o32 D3 /2            [386] \par\sb0
RCL r/m32,imm8                ; o32 C1 /2 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
RCR r/m8,1                    ; D0 /3                [8086] \par\sb0
RCR r/m8,CL                   ; D2 /3                [8086] \par\sb0
RCR r/m8,imm8                 ; C0 /3 ib             [186] \par\sb0
RCR r/m16,1                   ; o16 D1 /3            [8086] \par\sb0
RCR r/m16,CL                  ; o16 D3 /3            [8086] \par\sb0
RCR r/m16,imm8                ; o16 C1 /3 ib         [186] \par\sb0
RCR r/m32,1                   ; o32 D1 /3            [386] \par\sb0
RCR r/m32,CL                  ; o32 D3 /3            [386] \par\sb0
RCR r/m32,imm8                ; o32 C1 /3 ib         [386]\par\sb0
\pard\f0\sb120
{\f1 RCL} and {\f1 RCR} perform a 9-bit, 17-bit or 33-bit bitwise rotation 
operation, involving the given source/destination (first) operand and the 
carry bit. Thus, for example, in the operation {\f1 RCL\'A0AL,1}, a 9-bit 
rotation is performed in which {\f1 AL} is shifted left by 1, the top bit 
of {\f1 AL} moves into the carry flag, and the original value of the carry 
flag is placed in the low bit of {\f1 AL}.
\par\sb120
The number of bits to rotate by is given by the second operand. Only the 
bottom five bits of the rotation count are considered by processors above 
the 8086.
\par\sb120
You can force the longer (286 and upwards, beginning with a {\f1 C1} byte) 
form of {\f1 RCL\'A0foo,1} by using a {\f1 BYTE} prefix: 
{\f1 RCL\'A0foo,BYTE\'A01}. Similarly with {\f1 RCR}.
\par\sb120
\page
#{\footnote section_b_4_268}
${\footnote B.4.268. RCPPS: Packed Single-Precision FP Reciprocal}
+{\footnote browse:00488}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RCPPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.268. {\f1 RCPPS}: Packed Single-Precision FP Reciprocal
\par\pard\plain\sb120
\keep\f1\sb120
RCPPS xmm1,xmm2/m128          ; 0F 53 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 RCPPS} returns an approximation of the reciprocal of the packed 
single-precision FP values from xmm2/m128. The maximum error for this 
approximation is: |Error| <= 1.5 x 2^-12
\par\sb120
\page
#{\footnote section_b_4_269}
${\footnote B.4.269. RCPSS: Scalar Single-Precision FP Reciprocal}
+{\footnote browse:00489}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RCPSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.269. {\f1 RCPSS}: Scalar Single-Precision FP Reciprocal
\par\pard\plain\sb120
\keep\f1\sb120
RCPSS xmm1,xmm2/m128          ; F3 0F 53 /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 RCPSS} returns an approximation of the reciprocal of the lower 
single-precision FP value from xmm2/m32; the upper three fields are passed 
through from xmm1. The maximum error for this approximation is: |Error| <= 
1.5 x 2^-12
\par\sb120
\page
#{\footnote section_b_4_270}
${\footnote B.4.270. RDMSR: Read Model-Specific Registers}
+{\footnote browse:00490}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RDMSR}
\keepn\f2\b\fs30\sb60\sa60
B.4.270. {\f1 RDMSR}: Read Model-Specific Registers
\par\pard\plain\sb120
\keep\f1\sb120
RDMSR                         ; 0F 32                [PENT,PRIV]\par\sb0
\pard\f0\sb120
{\f1 RDMSR} reads the processor Model-Specific Register (MSR) whose index 
is stored in {\f1 ECX}, and stores the result in {\f1 EDX:EAX}. See also 
{\f1 WRMSR} ({\uldb section B.4.329}{\v section_b_4_329}).
\par\sb120
\page
#{\footnote section_b_4_271}
${\footnote B.4.271. RDPMC: Read Performance-Monitoring Counters}
+{\footnote browse:00491}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RDPMC}
\keepn\f2\b\fs30\sb60\sa60
B.4.271. {\f1 RDPMC}: Read Performance-Monitoring Counters
\par\pard\plain\sb120
\keep\f1\sb120
RDPMC                         ; 0F 33                [P6]\par\sb0
\pard\f0\sb120
{\f1 RDPMC} reads the processor performance-monitoring counter whose index 
is stored in {\f1 ECX}, and stores the result in {\f1 EDX:EAX}.
\par\sb120
This instruction is available on P6 and later processors and on MMX class 
processors.
\par\sb120
\page
#{\footnote section_b_4_272}
${\footnote B.4.272. RDSHR: Read SMM Header Pointer Register}
+{\footnote browse:00492}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RDSHR}
\keepn\f2\b\fs30\sb60\sa60
B.4.272. {\f1 RDSHR}: Read SMM Header Pointer Register
\par\pard\plain\sb120
\keep\f1\sb120
RDSHR r/m32                   ; 0F 36 /0        [386,CYRIX,SMM]\par\sb0
\pard\f0\sb120
{\f1 RDSHR} reads the contents of the SMM header pointer register and saves 
it to the destination operand, which can be either a 32 bit memory location 
or a 32 bit register.
\par\sb120
See also {\f1 WRSHR} ({\uldb section B.4.330}{\v section_b_4_330}).
\par\sb120
\page
#{\footnote section_b_4_273}
${\footnote B.4.273. RDTSC: Read Time-Stamp Counter}
+{\footnote browse:00493}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RDTSC}
\keepn\f2\b\fs30\sb60\sa60
B.4.273. {\f1 RDTSC}: Read Time-Stamp Counter
\par\pard\plain\sb120
\keep\f1\sb120
RDTSC                         ; 0F 31                [PENT]\par\sb0
\pard\f0\sb120
{\f1 RDTSC} reads the processor's time-stamp counter into {\f1 EDX:EAX}.
\par\sb120
\page
#{\footnote section_b_4_274}
${\footnote B.4.274. RET, RETF, RETN: Return from Procedure Call}
+{\footnote browse:00494}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RET;
RETF;
RETN}
\keepn\f2\b\fs30\sb60\sa60
B.4.274. {\f1 RET}, {\f1 RETF}, {\f1 RETN}: Return from Procedure Call
\par\pard\plain\sb120
\keep\f1\sb120
RET                           ; C3                   [8086] \par\sb0
RET imm16                     ; C2 iw                [8086]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
RETF                          ; CB                   [8086] \par\sb0
RETF imm16                    ; CA iw                [8086]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
RETN                          ; C3                   [8086] \par\sb0
RETN imm16                    ; C2 iw                [8086]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 RET}, and its exact synonym {\f1 RETN}, pop {\f1 IP} or {\f1 EIP} from 
the stack and transfer control to the new address. Optionally, if a numeric 
second operand is provided, they increment the stack pointer by a further 
{\f1 imm16} bytes after popping the return address.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 RETF} executes a far return: after popping {\f1 IP}/{\f1 EIP}, it then 
pops {\f1 CS}, and {\i then} increments the stack pointer by the optional 
argument if present.
\par\pard\sb120
\page
#{\footnote section_b_4_275}
${\footnote B.4.275. ROL, ROR: Bitwise Rotate}
+{\footnote browse:00495}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote ROL;
ROR}
\keepn\f2\b\fs30\sb60\sa60
B.4.275. {\f1 ROL}, {\f1 ROR}: Bitwise Rotate
\par\pard\plain\sb120
\keep\f1\sb120
ROL r/m8,1                    ; D0 /0                [8086] \par\sb0
ROL r/m8,CL                   ; D2 /0                [8086] \par\sb0
ROL r/m8,imm8                 ; C0 /0 ib             [186] \par\sb0
ROL r/m16,1                   ; o16 D1 /0            [8086] \par\sb0
ROL r/m16,CL                  ; o16 D3 /0            [8086] \par\sb0
ROL r/m16,imm8                ; o16 C1 /0 ib         [186] \par\sb0
ROL r/m32,1                   ; o32 D1 /0            [386] \par\sb0
ROL r/m32,CL                  ; o32 D3 /0            [386] \par\sb0
ROL r/m32,imm8                ; o32 C1 /0 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
ROR r/m8,1                    ; D0 /1                [8086] \par\sb0
ROR r/m8,CL                   ; D2 /1                [8086] \par\sb0
ROR r/m8,imm8                 ; C0 /1 ib             [186] \par\sb0
ROR r/m16,1                   ; o16 D1 /1            [8086] \par\sb0
ROR r/m16,CL                  ; o16 D3 /1            [8086] \par\sb0
ROR r/m16,imm8                ; o16 C1 /1 ib         [186] \par\sb0
ROR r/m32,1                   ; o32 D1 /1            [386] \par\sb0
ROR r/m32,CL                  ; o32 D3 /1            [386] \par\sb0
ROR r/m32,imm8                ; o32 C1 /1 ib         [386]\par\sb0
\pard\f0\sb120
{\f1 ROL} and {\f1 ROR} perform a bitwise rotation operation on the given 
source/destination (first) operand. Thus, for example, in the operation 
{\f1 ROL\'A0AL,1}, an 8-bit rotation is performed in which {\f1 AL} is 
shifted left by 1 and the original top bit of {\f1 AL} moves round into the 
low bit.
\par\sb120
The number of bits to rotate by is given by the second operand. Only the 
bottom five bits of the rotation count are considered by processors above 
the 8086.
\par\sb120
You can force the longer (286 and upwards, beginning with a {\f1 C1} byte) 
form of {\f1 ROL\'A0foo,1} by using a {\f1 BYTE} prefix: 
{\f1 ROL\'A0foo,BYTE\'A01}. Similarly with {\f1 ROR}.
\par\sb120
\page
#{\footnote section_b_4_276}
${\footnote B.4.276. RSDC: Restore Segment Register and Descriptor}
+{\footnote browse:00496}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RSDC}
\keepn\f2\b\fs30\sb60\sa60
B.4.276. {\f1 RSDC}: Restore Segment Register and Descriptor
\par\pard\plain\sb120
\keep\f1\sb120
RSDC segreg,m80               ; 0F 79 /r        [486,CYRIX,SMM]\par\sb0
\pard\f0\sb120
{\f1 RSDC} restores a segment register (DS, ES, FS, GS, or SS) from mem80, 
and sets up its descriptor.
\par\sb120
\page
#{\footnote section_b_4_277}
${\footnote B.4.277. RSLDT: Restore Segment Register and Descriptor}
+{\footnote browse:00497}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RSLDT}
\keepn\f2\b\fs30\sb60\sa60
B.4.277. {\f1 RSLDT}: Restore Segment Register and Descriptor
\par\pard\plain\sb120
\keep\f1\sb120
RSLDT m80                     ; 0F 7B /0        [486,CYRIX,SMM]\par\sb0
\pard\f0\sb120
{\f1 RSLDT} restores the Local Descriptor Table (LDTR) from mem80.
\par\sb120
\page
#{\footnote section_b_4_278}
${\footnote B.4.278. RSM: Resume from System-Management Mode}
+{\footnote browse:00498}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RSM}
\keepn\f2\b\fs30\sb60\sa60
B.4.278. {\f1 RSM}: Resume from System-Management Mode
\par\pard\plain\sb120
\keep\f1\sb120
RSM                           ; 0F AA                [PENT]\par\sb0
\pard\f0\sb120
{\f1 RSM} returns the processor to its normal operating mode when it was in 
System-Management Mode.
\par\sb120
\page
#{\footnote section_b_4_279}
${\footnote B.4.279. RSQRTPS: Packed Single-Precision FP Square Root Reciprocal}
+{\footnote browse:00499}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RSQRTPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.279. {\f1 RSQRTPS}: Packed Single-Precision FP Square Root Reciprocal
\par\pard\plain\sb120
\keep\f1\sb120
RSQRTPS xmm1,xmm2/m128        ; 0F 52 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 RSQRTPS} computes the approximate reciprocals of the square roots of 
the packed single-precision floating-point values in the source and stores 
the results in xmm1. The maximum error for this approximation is: |Error| 
<= 1.5 x 2^-12
\par\sb120
\page
#{\footnote section_b_4_280}
${\footnote B.4.280. RSQRTSS: Scalar Single-Precision FP Square Root Reciprocal}
+{\footnote browse:00500}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RSQRTSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.280. {\f1 RSQRTSS}: Scalar Single-Precision FP Square Root Reciprocal
\par\pard\plain\sb120
\keep\f1\sb120
RSQRTSS xmm1,xmm2/m128        ; F3 0F 52 /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 RSQRTSS} returns an approximation of the reciprocal of the square root 
of the lowest order single-precision FP value from the source, and stores 
it in the low doubleword of the destination register. The upper three 
fields of xmm1 are preserved. The maximum error for this approximation is: 
|Error| <= 1.5 x 2^-12
\par\sb120
\page
#{\footnote section_b_4_281}
${\footnote B.4.281. RSTS: Restore TSR and Descriptor}
+{\footnote browse:00501}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote RSTS}
\keepn\f2\b\fs30\sb60\sa60
B.4.281. {\f1 RSTS}: Restore TSR and Descriptor
\par\pard\plain\sb120
\keep\f1\sb120
RSTS m80                      ; 0F 7D /0        [486,CYRIX,SMM]\par\sb0
\pard\f0\sb120
{\f1 RSTS} restores Task State Register (TSR) from mem80.
\par\sb120
\page
#{\footnote section_b_4_282}
${\footnote B.4.282. SAHF: Store AH to Flags}
+{\footnote browse:00502}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SAHF}
\keepn\f2\b\fs30\sb60\sa60
B.4.282. {\f1 SAHF}: Store AH to Flags
\par\pard\plain\sb120
\keep\f1\sb120
SAHF                          ; 9E                   [8086]\par\sb0
\pard\f0\sb120
{\f1 SAHF} sets the low byte of the flags word according to the contents of 
the {\f1 AH} register.
\par\sb120
The operation of {\f1 SAHF} is:
\par\sb120
\keep\f1\sb120
 AH --> SF:ZF:0:AF:0:PF:1:CF\par\sb0
\pard\f0\sb120
See also {\f1 LAHF} ({\uldb section B.4.131}{\v section_b_4_131}).
\par\sb120
\page
#{\footnote section_b_4_283}
${\footnote B.4.283. SAL, SAR: Bitwise Arithmetic Shifts}
+{\footnote browse:00503}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SAL;
SAR}
\keepn\f2\b\fs30\sb60\sa60
B.4.283. {\f1 SAL}, {\f1 SAR}: Bitwise Arithmetic Shifts
\par\pard\plain\sb120
\keep\f1\sb120
SAL r/m8,1                    ; D0 /4                [8086] \par\sb0
SAL r/m8,CL                   ; D2 /4                [8086] \par\sb0
SAL r/m8,imm8                 ; C0 /4 ib             [186] \par\sb0
SAL r/m16,1                   ; o16 D1 /4            [8086] \par\sb0
SAL r/m16,CL                  ; o16 D3 /4            [8086] \par\sb0
SAL r/m16,imm8                ; o16 C1 /4 ib         [186] \par\sb0
SAL r/m32,1                   ; o32 D1 /4            [386] \par\sb0
SAL r/m32,CL                  ; o32 D3 /4            [386] \par\sb0
SAL r/m32,imm8                ; o32 C1 /4 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SAR r/m8,1                    ; D0 /7                [8086] \par\sb0
SAR r/m8,CL                   ; D2 /7                [8086] \par\sb0
SAR r/m8,imm8                 ; C0 /7 ib             [186] \par\sb0
SAR r/m16,1                   ; o16 D1 /7            [8086] \par\sb0
SAR r/m16,CL                  ; o16 D3 /7            [8086] \par\sb0
SAR r/m16,imm8                ; o16 C1 /7 ib         [186] \par\sb0
SAR r/m32,1                   ; o32 D1 /7            [386] \par\sb0
SAR r/m32,CL                  ; o32 D3 /7            [386] \par\sb0
SAR r/m32,imm8                ; o32 C1 /7 ib         [386]\par\sb0
\pard\f0\sb120
{\f1 SAL} and {\f1 SAR} perform an arithmetic shift operation on the given 
source/destination (first) operand. The vacated bits are filled with zero 
for {\f1 SAL}, and with copies of the original high bit of the source 
operand for {\f1 SAR}.
\par\sb120
{\f1 SAL} is a synonym for {\f1 SHL} (see {\uldb section 
B.4.290}{\v section_b_4_290}). NASM will assemble either one to the same 
code, but NDISASM will always disassemble that code as {\f1 SHL}.
\par\sb120
The number of bits to shift by is given by the second operand. Only the 
bottom five bits of the shift count are considered by processors above the 
8086.
\par\sb120
You can force the longer (286 and upwards, beginning with a {\f1 C1} byte) 
form of {\f1 SAL\'A0foo,1} by using a {\f1 BYTE} prefix: 
{\f1 SAL\'A0foo,BYTE\'A01}. Similarly with {\f1 SAR}.
\par\sb120
\page
#{\footnote section_b_4_284}
${\footnote B.4.284. SALC: Set AL from Carry Flag}
+{\footnote browse:00504}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SALC}
\keepn\f2\b\fs30\sb60\sa60
B.4.284. {\f1 SALC}: Set AL from Carry Flag
\par\pard\plain\sb120
\keep\f1\sb120
SALC                          ; D6                  [8086,UNDOC]\par\sb0
\pard\f0\sb120
{\f1 SALC} is an early undocumented instruction similar in concept to 
{\f1 SETcc} ({\uldb section B.4.287}{\v section_b_4_287}). Its function is 
to set {\f1 AL} to zero if the carry flag is clear, or to {\f1 0xFF} if it 
is set.
\par\sb120
\page
#{\footnote section_b_4_285}
${\footnote B.4.285. SBB: Subtract with Borrow}
+{\footnote browse:00505}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SBB}
\keepn\f2\b\fs30\sb60\sa60
B.4.285. {\f1 SBB}: Subtract with Borrow
\par\pard\plain\sb120
\keep\f1\sb120
SBB r/m8,reg8                 ; 18 /r                [8086] \par\sb0
SBB r/m16,reg16               ; o16 19 /r            [8086] \par\sb0
SBB r/m32,reg32               ; o32 19 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SBB reg8,r/m8                 ; 1A /r                [8086] \par\sb0
SBB reg16,r/m16               ; o16 1B /r            [8086] \par\sb0
SBB reg32,r/m32               ; o32 1B /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SBB r/m8,imm8                 ; 80 /3 ib             [8086] \par\sb0
SBB r/m16,imm16               ; o16 81 /3 iw         [8086] \par\sb0
SBB r/m32,imm32               ; o32 81 /3 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SBB r/m16,imm8                ; o16 83 /3 ib         [8086] \par\sb0
SBB r/m32,imm8                ; o32 83 /3 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SBB AL,imm8                   ; 1C ib                [8086] \par\sb0
SBB AX,imm16                  ; o16 1D iw            [8086] \par\sb0
SBB EAX,imm32                 ; o32 1D id            [386]\par\sb0
\pard\f0\sb120
{\f1 SBB} performs integer subtraction: it subtracts its second operand, 
plus the value of the carry flag, from its first, and leaves the result in 
its destination (first) operand. The flags are set according to the result 
of the operation: in particular, the carry flag is affected and can be used 
by a subsequent {\f1 SBB} instruction.
\par\sb120
In the forms with an 8-bit immediate second operand and a longer first 
operand, the second operand is considered to be signed, and is 
sign-extended to the length of the first operand. In these cases, the 
{\f1 BYTE} qualifier is necessary to force NASM to generate this form of 
the instruction.
\par\sb120
To subtract one number from another without also subtracting the contents 
of the carry flag, use {\f1 SUB} ({\uldb section 
B.4.305}{\v section_b_4_305}).
\par\sb120
\page
#{\footnote section_b_4_286}
${\footnote B.4.286. SCASB, SCASW, SCASD: Scan String}
+{\footnote browse:00506}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
SCASB;
SCASD;
SCASW}
\keepn\f2\b\fs30\sb60\sa60
B.4.286. {\f1 SCASB}, {\f1 SCASW}, {\f1 SCASD}: Scan String
\par\pard\plain\sb120
\keep\f1\sb120
SCASB                         ; AE                   [8086] \par\sb0
SCASW                         ; o16 AF               [8086] \par\sb0
SCASD                         ; o32 AF               [386]\par\sb0
\pard\f0\sb120
{\f1 SCASB} compares the byte in {\f1 AL} with the byte at {\f1 [ES:DI]} or 
{\f1 [ES:EDI]}, and sets the flags accordingly. It then increments or 
decrements (depending on the direction flag: increments if the flag is 
clear, decrements if it is set) {\f1 DI} (or {\f1 EDI}).
\par\sb120
The register used is {\f1 DI} if the address size is 16 bits, and {\f1 EDI} 
if it is 32 bits. If you need to use an address size not equal to the 
current {\f1 BITS} setting, you can use an explicit {\f1 a16} or {\f1 a32} 
prefix.
\par\sb120
Segment override prefixes have no effect for this instruction: the use of 
{\f1 ES} for the load from {\f1 [DI]} or {\f1 [EDI]} cannot be overridden.
\par\sb120
{\f1 SCASW} and {\f1 SCASD} work in the same way, but they compare a word 
to {\f1 AX} or a doubleword to {\f1 EAX} instead of a byte to {\f1 AL}, and 
increment or decrement the addressing registers by 2 or 4 instead of 1.
\par\sb120
The {\f1 REPE} and {\f1 REPNE} prefixes (equivalently, {\f1 REPZ} and 
{\f1 REPNZ}) may be used to repeat the instruction up to {\f1 CX} (or 
{\f1 ECX} \'96 again, the address size chooses which) times until the first 
unequal or equal byte is found.
\par\sb120
\page
#{\footnote section_b_4_287}
${\footnote B.4.287. SETcc: Set Register from Condition}
+{\footnote browse:00507}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SETcc}
\keepn\f2\b\fs30\sb60\sa60
B.4.287. {\f1 SETcc}: Set Register from Condition
\par\pard\plain\sb120
\keep\f1\sb120
SETcc r/m8                    ; 0F 90+cc /2          [386]\par\sb0
\pard\f0\sb120
{\f1 SETcc} sets the given 8-bit operand to zero if its condition is not 
satisfied, and to 1 if it is.
\par\sb120
\page
#{\footnote section_b_4_288}
${\footnote B.4.288. SFENCE: Store Fence}
+{\footnote browse:00508}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SFENCE}
\keepn\f2\b\fs30\sb60\sa60
B.4.288. {\f1 SFENCE}: Store Fence
\par\pard\plain\sb120
\keep\f1\sb120
SFENCE                 ; 0F AE /7               [KATMAI]\par\sb0
\pard\f0\sb120
{\f1 SFENCE} performs a serialising operation on all writes to memory that 
were issued before the {\f1 SFENCE} instruction. This guarantees that all 
memory writes before the {\f1 SFENCE} instruction are visible before any 
writes after the {\f1 SFENCE} instruction.
\par\sb120
{\f1 SFENCE} is ordered respective to other {\f1 SFENCE} instruction, 
{\f1 MFENCE}, any memory write and any other serialising instruction (such 
as {\f1 CPUID}).
\par\sb120
Weakly ordered memory types can be used to achieve higher processor 
performance through such techniques as out-of-order issue, write-combining, 
and write-collapsing. The degree to which a consumer of data recognizes or 
knows that the data is weakly ordered varies among applications and may be 
unknown to the producer of this data. The {\f1 SFENCE} instruction provides 
a performance-efficient way of insuring store ordering between routines 
that produce weakly-ordered results and routines that consume this data.
\par\sb120
{\f1 SFENCE} uses the following ModRM encoding:
\par\sb120
\keep\f1\sb120
          Mod (7:6)        = 11B \par\sb0
          Reg/Opcode (5:3) = 111B \par\sb0
          R/M (2:0)        = 000B\par\sb0
\pard\f0\sb120
All other ModRM encodings are defined to be reserved, and use of these 
encodings risks incompatibility with future processors.
\par\sb120
See also {\f1 LFENCE} ({\uldb section B.4.137}{\v section_b_4_137}) and 
{\f1 MFENCE} ({\uldb section B.4.151}{\v section_b_4_151}).
\par\sb120
\page
#{\footnote section_b_4_289}
${\footnote B.4.289. SGDT, SIDT, SLDT: Store Descriptor Table Pointers}
+{\footnote browse:00509}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SGDT;
SIDT;
SLDT}
\keepn\f2\b\fs30\sb60\sa60
B.4.289. {\f1 SGDT}, {\f1 SIDT}, {\f1 SLDT}: Store Descriptor Table Pointers
\par\pard\plain\sb120
\keep\f1\sb120
SGDT mem                      ; 0F 01 /0             [286,PRIV] \par\sb0
SIDT mem                      ; 0F 01 /1             [286,PRIV] \par\sb0
SLDT r/m16                    ; 0F 00 /0             [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 SGDT} and {\f1 SIDT} both take a 6-byte memory area as an operand: 
they store the contents of the GDTR (global descriptor table register) or 
IDTR (interrupt descriptor table register) into that area as a 32-bit 
linear address and a 16-bit size limit from that area (in that order). 
These are the only instructions which directly use {\i linear} addresses, 
rather than segment/offset pairs.
\par\sb120
{\f1 SLDT} stores the segment selector corresponding to the LDT (local 
descriptor table) into the given operand.
\par\sb120
See also {\f1 LGDT}, {\f1 LIDT} and {\f1 LLDT} ({\uldb section 
B.4.138}{\v section_b_4_138}).
\par\sb120
\page
#{\footnote section_b_4_290}
${\footnote B.4.290. SHL, SHR: Bitwise Logical Shifts}
+{\footnote browse:00510}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SHL;
SHR}
\keepn\f2\b\fs30\sb60\sa60
B.4.290. {\f1 SHL}, {\f1 SHR}: Bitwise Logical Shifts
\par\pard\plain\sb120
\keep\f1\sb120
SHL r/m8,1                    ; D0 /4                [8086] \par\sb0
SHL r/m8,CL                   ; D2 /4                [8086] \par\sb0
SHL r/m8,imm8                 ; C0 /4 ib             [186] \par\sb0
SHL r/m16,1                   ; o16 D1 /4            [8086] \par\sb0
SHL r/m16,CL                  ; o16 D3 /4            [8086] \par\sb0
SHL r/m16,imm8                ; o16 C1 /4 ib         [186] \par\sb0
SHL r/m32,1                   ; o32 D1 /4            [386] \par\sb0
SHL r/m32,CL                  ; o32 D3 /4            [386] \par\sb0
SHL r/m32,imm8                ; o32 C1 /4 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SHR r/m8,1                    ; D0 /5                [8086] \par\sb0
SHR r/m8,CL                   ; D2 /5                [8086] \par\sb0
SHR r/m8,imm8                 ; C0 /5 ib             [186] \par\sb0
SHR r/m16,1                   ; o16 D1 /5            [8086] \par\sb0
SHR r/m16,CL                  ; o16 D3 /5            [8086] \par\sb0
SHR r/m16,imm8                ; o16 C1 /5 ib         [186] \par\sb0
SHR r/m32,1                   ; o32 D1 /5            [386] \par\sb0
SHR r/m32,CL                  ; o32 D3 /5            [386] \par\sb0
SHR r/m32,imm8                ; o32 C1 /5 ib         [386]\par\sb0
\pard\f0\sb120
{\f1 SHL} and {\f1 SHR} perform a logical shift operation on the given 
source/destination (first) operand. The vacated bits are filled with zero.
\par\sb120
A synonym for {\f1 SHL} is {\f1 SAL} (see {\uldb section 
B.4.283}{\v section_b_4_283}). NASM will assemble either one to the same 
code, but NDISASM will always disassemble that code as {\f1 SHL}.
\par\sb120
The number of bits to shift by is given by the second operand. Only the 
bottom five bits of the shift count are considered by processors above the 
8086.
\par\sb120
You can force the longer (286 and upwards, beginning with a {\f1 C1} byte) 
form of {\f1 SHL\'A0foo,1} by using a {\f1 BYTE} prefix: 
{\f1 SHL\'A0foo,BYTE\'A01}. Similarly with {\f1 SHR}.
\par\sb120
\page
#{\footnote section_b_4_291}
${\footnote B.4.291. SHLD, SHRD: Bitwise Double-Precision Shifts}
+{\footnote browse:00511}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SHLD;
SHRD}
\keepn\f2\b\fs30\sb60\sa60
B.4.291. {\f1 SHLD}, {\f1 SHRD}: Bitwise Double-Precision Shifts
\par\pard\plain\sb120
\keep\f1\sb120
SHLD r/m16,reg16,imm8         ; o16 0F A4 /r ib      [386] \par\sb0
SHLD r/m16,reg32,imm8         ; o32 0F A4 /r ib      [386] \par\sb0
SHLD r/m16,reg16,CL           ; o16 0F A5 /r         [386] \par\sb0
SHLD r/m16,reg32,CL           ; o32 0F A5 /r         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SHRD r/m16,reg16,imm8         ; o16 0F AC /r ib      [386] \par\sb0
SHRD r/m32,reg32,imm8         ; o32 0F AC /r ib      [386] \par\sb0
SHRD r/m16,reg16,CL           ; o16 0F AD /r         [386] \par\sb0
SHRD r/m32,reg32,CL           ; o32 0F AD /r         [386]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 SHLD} performs a double-precision left shift. It notionally places its 
second operand to the right of its first, then shifts the entire bit string 
thus generated to the left by a number of bits specified in the third 
operand. It then updates only the {\i first} operand according to the 
result of this. The second operand is not modified.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 SHRD} performs the corresponding right shift: it notionally places the 
second operand to the {\i left} of the first, shifts the whole bit string 
right, and updates only the first operand.
\par\pard\sb120
For example, if {\f1 EAX} holds {\f1 0x01234567} and {\f1 EBX} holds 
{\f1 0x89ABCDEF}, then the instruction {\f1 SHLD\'A0EAX,EBX,4} would update 
{\f1 EAX} to hold {\f1 0x12345678}. Under the same conditions, 
{\f1 SHRD\'A0EAX,EBX,4} would update {\f1 EAX} to hold {\f1 0xF0123456}.
\par\sb120
The number of bits to shift by is given by the third operand. Only the 
bottom five bits of the shift count are considered.
\par\sb120
\page
#{\footnote section_b_4_292}
${\footnote B.4.292. SHUFPD: Shuffle Packed Double-Precision FP Values}
+{\footnote browse:00512}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SHUFPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.292. {\f1 SHUFPD}: Shuffle Packed Double-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
SHUFPD xmm1,xmm2/m128,imm8    ; 66 0F C6 /r ib  [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 SHUFPD} moves one of the packed double-precision FP values from the 
destination operand into the low quadword of the destination operand; the 
upper quadword is generated by moving one of the double-precision FP values 
from the source operand into the destination. The select (third) operand 
selects which of the values are moved to the destination register.
\par\sb120
The select operand is an 8-bit immediate: bit 0 selects which value is 
moved from the destination operand to the result (where 0 selects the low 
quadword and 1 selects the high quadword) and bit 1 selects which value is 
moved from the source operand to the result. Bits 2 through 7 of the 
shuffle operand are reserved.
\par\sb120
\page
#{\footnote section_b_4_293}
${\footnote B.4.293. SHUFPS: Shuffle Packed Single-Precision FP Values}
+{\footnote browse:00513}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SHUFPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.293. {\f1 SHUFPS}: Shuffle Packed Single-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
SHUFPS xmm1,xmm2/m128,imm8    ; 0F C6 /r ib     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 SHUFPS} moves two of the packed single-precision FP values from the 
destination operand into the low quadword of the destination operand; the 
upper quadword is generated by moving two of the single-precision FP values 
from the source operand into the destination. The select (third) operand 
selects which of the values are moved to the destination register.
\par\sb120
The select operand is an 8-bit immediate: bits 0 and 1 select the value to 
be moved from the destination operand the low doubleword of the result, 
bits 2 and 3 select the value to be moved from the destination operand the 
second doubleword of the result, bits 4 and 5 select the value to be moved 
from the source operand the third doubleword of the result, and bits 6 and 
7 select the value to be moved from the source operand to the high 
doubleword of the result.
\par\sb120
\page
#{\footnote section_b_4_294}
${\footnote B.4.294. SMI: System Management Interrupt}
+{\footnote browse:00514}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SMI}
\keepn\f2\b\fs30\sb60\sa60
B.4.294. {\f1 SMI}: System Management Interrupt
\par\pard\plain\sb120
\keep\f1\sb120
SMI                           ; F1                   [386,UNDOC]\par\sb0
\pard\f0\sb120
{\f1 SMI} puts some AMD processors into SMM mode. It is available on some 
386 and 486 processors, and is only available when DR7 bit 12 is set, 
otherwise it generates an Int 1.
\par\sb120
\page
#{\footnote section_b_4_295}
${\footnote B.4.295. SMINT, SMINTOLD: Software SMM Entry (CYRIX)}
+{\footnote browse:00515}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SMINT;
SMINTOLD}
\keepn\f2\b\fs30\sb60\sa60
B.4.295. {\f1 SMINT}, {\f1 SMINTOLD}: Software SMM Entry (CYRIX)
\par\pard\plain\sb120
\keep\f1\sb120
SMINT                         ; 0F 38                [PENT,CYRIX] \par\sb0
SMINTOLD                      ; 0F 7E                [486,CYRIX]\par\sb0
\pard\f0\sb120
{\f1 SMINT} puts the processor into SMM mode. The CPU state information is 
saved in the SMM memory header, and then execution begins at the SMM base 
address.
\par\sb120
{\f1 SMINTOLD} is the same as {\f1 SMINT}, but was the opcode used on the 
486.
\par\sb120
This pair of opcodes are specific to the Cyrix and compatible range of 
processors (Cyrix, IBM, Via).
\par\sb120
\page
#{\footnote section_b_4_296}
${\footnote B.4.296. SMSW: Store Machine Status Word}
+{\footnote browse:00516}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SMSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.296. {\f1 SMSW}: Store Machine Status Word
\par\pard\plain\sb120
\keep\f1\sb120
SMSW r/m16                    ; 0F 01 /4             [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 SMSW} stores the bottom half of the {\f1 CR0} control register (or the 
Machine Status Word, on 286 processors) into the destination operand. See 
also {\f1 LMSW} ({\uldb section B.4.139}{\v section_b_4_139}).
\par\sb120
For 32-bit code, this would use the low 16-bits of the specified register 
(or a 16bit memory location), without needing an operand size override 
byte.
\par\sb120
\page
#{\footnote section_b_4_297}
${\footnote B.4.297. SQRTPD: Packed Double-Precision FP Square Root}
+{\footnote browse:00517}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SQRTPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.297. {\f1 SQRTPD}: Packed Double-Precision FP Square Root
\par\pard\plain\sb120
\keep\f1\sb120
SQRTPD xmm1,xmm2/m128         ; 66 0F 51 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 SQRTPD} calculates the square root of the packed double-precision FP 
value from the source operand, and stores the double-precision results in 
the destination register.
\par\sb120
\page
#{\footnote section_b_4_298}
${\footnote B.4.298. SQRTPS: Packed Single-Precision FP Square Root}
+{\footnote browse:00518}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SQRTPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.298. {\f1 SQRTPS}: Packed Single-Precision FP Square Root
\par\pard\plain\sb120
\keep\f1\sb120
SQRTPS xmm1,xmm2/m128         ; 0F 51 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 SQRTPS} calculates the square root of the packed single-precision FP 
value from the source operand, and stores the single-precision results in 
the destination register.
\par\sb120
\page
#{\footnote section_b_4_299}
${\footnote B.4.299. SQRTSD: Scalar Double-Precision FP Square Root}
+{\footnote browse:00519}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SQRTSD}
\keepn\f2\b\fs30\sb60\sa60
B.4.299. {\f1 SQRTSD}: Scalar Double-Precision FP Square Root
\par\pard\plain\sb120
\keep\f1\sb120
SQRTSD xmm1,xmm2/m128         ; F2 0F 51 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 SQRTSD} calculates the square root of the low-order double-precision 
FP value from the source operand, and stores the double-precision result in 
the destination register. The high-quadword remains unchanged.
\par\sb120
\page
#{\footnote section_b_4_300}
${\footnote B.4.300. SQRTSS: Scalar Single-Precision FP Square Root}
+{\footnote browse:00520}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SQRTSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.300. {\f1 SQRTSS}: Scalar Single-Precision FP Square Root
\par\pard\plain\sb120
\keep\f1\sb120
SQRTSS xmm1,xmm2/m128         ; F3 0F 51 /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 SQRTSS} calculates the square root of the low-order single-precision 
FP value from the source operand, and stores the single-precision result in 
the destination register. The three high doublewords remain unchanged.
\par\sb120
\page
#{\footnote section_b_4_301}
${\footnote B.4.301. STC, STD, STI: Set Flags}
+{\footnote browse:00521}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote STC;
STD;
STI}
\keepn\f2\b\fs30\sb60\sa60
B.4.301. {\f1 STC}, {\f1 STD}, {\f1 STI}: Set Flags
\par\pard\plain\sb120
\keep\f1\sb120
STC                           ; F9                   [8086] \par\sb0
STD                           ; FD                   [8086] \par\sb0
STI                           ; FB                   [8086]\par\sb0
\pard\f0\sb120
These instructions set various flags. {\f1 STC} sets the carry flag; 
{\f1 STD} sets the direction flag; and {\f1 STI} sets the interrupt flag 
(thus enabling interrupts).
\par\sb120
To clear the carry, direction, or interrupt flags, use the {\f1 CLC}, 
{\f1 CLD} and {\f1 CLI} instructions ({\uldb section 
B.4.20}{\v section_b_4_20}). To invert the carry flag, use {\f1 CMC} 
({\uldb section B.4.22}{\v section_b_4_22}).
\par\sb120
\page
#{\footnote section_b_4_302}
${\footnote B.4.302. STMXCSR: Store Streaming SIMD Extension Control/Status}
+{\footnote browse:00522}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote STMXCSR}
\keepn\f2\b\fs30\sb60\sa60
B.4.302. {\f1 STMXCSR}: Store Streaming SIMD Extension Control/Status
\par\pard\plain\sb120
\keep\f1\sb120
STMXCSR m32                   ; 0F AE /3        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 STMXCSR} stores the contents of the {\f1 MXCSR} control/status 
register to the specified memory location. {\f1 MXCSR} is used to enable 
masked/unmasked exception handling, to set rounding modes, to set 
flush-to-zero mode, and to view exception status flags. The reserved bits 
in the {\f1 MXCSR} register are stored as 0s.
\par\sb120
For details of the {\f1 MXCSR} register, see the Intel processor docs.
\par\sb120
See also {\f1 LDMXCSR} ({\uldb section B.4.133}{\v section_b_4_133}).
\par\sb120
\page
#{\footnote section_b_4_303}
${\footnote B.4.303. STOSB, STOSW, STOSD: Store Byte to String}
+{\footnote browse:00523}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
STOSB;
STOSD;
STOSW}
\keepn\f2\b\fs30\sb60\sa60
B.4.303. {\f1 STOSB}, {\f1 STOSW}, {\f1 STOSD}: Store Byte to String
\par\pard\plain\sb120
\keep\f1\sb120
STOSB                         ; AA                   [8086] \par\sb0
STOSW                         ; o16 AB               [8086] \par\sb0
STOSD                         ; o32 AB               [386]\par\sb0
\pard\f0\sb120
{\f1 STOSB} stores the byte in {\f1 AL} at {\f1 [ES:DI]} or {\f1 [ES:EDI]}, 
and sets the flags accordingly. It then increments or decrements (depending 
on the direction flag: increments if the flag is clear, decrements if it is 
set) {\f1 DI} (or {\f1 EDI}).
\par\sb120
The register used is {\f1 DI} if the address size is 16 bits, and {\f1 EDI} 
if it is 32 bits. If you need to use an address size not equal to the 
current {\f1 BITS} setting, you can use an explicit {\f1 a16} or {\f1 a32} 
prefix.
\par\sb120
Segment override prefixes have no effect for this instruction: the use of 
{\f1 ES} for the store to {\f1 [DI]} or {\f1 [EDI]} cannot be overridden.
\par\sb120
{\f1 STOSW} and {\f1 STOSD} work in the same way, but they store the word 
in {\f1 AX} or the doubleword in {\f1 EAX} instead of the byte in {\f1 AL}, 
and increment or decrement the addressing registers by 2 or 4 instead of 1.
\par\sb120
The {\f1 REP} prefix may be used to repeat the instruction {\f1 CX} (or 
{\f1 ECX} \'96 again, the address size chooses which) times.
\par\sb120
\page
#{\footnote section_b_4_304}
${\footnote B.4.304. STR: Store Task Register}
+{\footnote browse:00524}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote STR}
\keepn\f2\b\fs30\sb60\sa60
B.4.304. {\f1 STR}: Store Task Register
\par\pard\plain\sb120
\keep\f1\sb120
STR r/m16                     ; 0F 00 /1             [286,PRIV]\par\sb0
\pard\f0\sb120
{\f1 STR} stores the segment selector corresponding to the contents of the 
Task Register into its operand. When the operand size is a 16-bit register, 
the upper 16-bits are cleared to 0s. When the destination operand is a 
memory location, 16 bits are written regardless of the operand size.
\par\sb120
\page
#{\footnote section_b_4_305}
${\footnote B.4.305. SUB: Subtract Integers}
+{\footnote browse:00525}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SUB}
\keepn\f2\b\fs30\sb60\sa60
B.4.305. {\f1 SUB}: Subtract Integers
\par\pard\plain\sb120
\keep\f1\sb120
SUB r/m8,reg8                 ; 28 /r                [8086] \par\sb0
SUB r/m16,reg16               ; o16 29 /r            [8086] \par\sb0
SUB r/m32,reg32               ; o32 29 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SUB reg8,r/m8                 ; 2A /r                [8086] \par\sb0
SUB reg16,r/m16               ; o16 2B /r            [8086] \par\sb0
SUB reg32,r/m32               ; o32 2B /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SUB r/m8,imm8                 ; 80 /5 ib             [8086] \par\sb0
SUB r/m16,imm16               ; o16 81 /5 iw         [8086] \par\sb0
SUB r/m32,imm32               ; o32 81 /5 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SUB r/m16,imm8                ; o16 83 /5 ib         [8086] \par\sb0
SUB r/m32,imm8                ; o32 83 /5 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
SUB AL,imm8                   ; 2C ib                [8086] \par\sb0
SUB AX,imm16                  ; o16 2D iw            [8086] \par\sb0
SUB EAX,imm32                 ; o32 2D id            [386]\par\sb0
\pard\f0\sb120
{\f1 SUB} performs integer subtraction: it subtracts its second operand 
from its first, and leaves the result in its destination (first) operand. 
The flags are set according to the result of the operation: in particular, 
the carry flag is affected and can be used by a subsequent {\f1 SBB} 
instruction ({\uldb section B.4.285}{\v section_b_4_285}).
\par\sb120
In the forms with an 8-bit immediate second operand and a longer first 
operand, the second operand is considered to be signed, and is 
sign-extended to the length of the first operand. In these cases, the 
{\f1 BYTE} qualifier is necessary to force NASM to generate this form of 
the instruction.
\par\sb120
\page
#{\footnote section_b_4_306}
${\footnote B.4.306. SUBPD: Packed Double-Precision FP Subtract}
+{\footnote browse:00526}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SUBPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.306. {\f1 SUBPD}: Packed Double-Precision FP Subtract
\par\pard\plain\sb120
\keep\f1\sb120
SUBPD xmm1,xmm2/m128          ; 66 0F 5C /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 SUBPD} subtracts the packed double-precision FP values of the source 
operand from those of the destination operand, and stores the result in the 
destination operation.
\par\sb120
\page
#{\footnote section_b_4_307}
${\footnote B.4.307. SUBPS: Packed Single-Precision FP Subtract}
+{\footnote browse:00527}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SUBPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.307. {\f1 SUBPS}: Packed Single-Precision FP Subtract
\par\pard\plain\sb120
\keep\f1\sb120
SUBPS xmm1,xmm2/m128          ; 0F 5C /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 SUBPS} subtracts the packed single-precision FP values of the source 
operand from those of the destination operand, and stores the result in the 
destination operation.
\par\sb120
\page
#{\footnote section_b_4_308}
${\footnote B.4.308. SUBSD: Scalar Single-FP Subtract}
+{\footnote browse:00528}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SUBSD}
\keepn\f2\b\fs30\sb60\sa60
B.4.308. {\f1 SUBSD}: Scalar Single-FP Subtract
\par\pard\plain\sb120
\keep\f1\sb120
SUBSD xmm1,xmm2/m128          ; F2 0F 5C /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 SUBSD} subtracts the low-order double-precision FP value of the source 
operand from that of the destination operand, and stores the result in the 
destination operation. The high quadword is unchanged.
\par\sb120
\page
#{\footnote section_b_4_309}
${\footnote B.4.309. SUBSS: Scalar Single-FP Subtract}
+{\footnote browse:00529}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SUBSS}
\keepn\f2\b\fs30\sb60\sa60
B.4.309. {\f1 SUBSS}: Scalar Single-FP Subtract
\par\pard\plain\sb120
\keep\f1\sb120
SUBSS xmm1,xmm2/m128          ; F3 0F 5C /r     [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 SUBSS} subtracts the low-order single-precision FP value of the source 
operand from that of the destination operand, and stores the result in the 
destination operation. The three high doublewords are unchanged.
\par\sb120
\page
#{\footnote section_b_4_310}
${\footnote B.4.310. SVDC: Save Segment Register and Descriptor}
+{\footnote browse:00530}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SVDC}
\keepn\f2\b\fs30\sb60\sa60
B.4.310. {\f1 SVDC}: Save Segment Register and Descriptor
\par\pard\plain\sb120
\keep\f1\sb120
SVDC m80,segreg               ; 0F 78 /r        [486,CYRIX,SMM]\par\sb0
\pard\f0\sb120
{\f1 SVDC} saves a segment register (DS, ES, FS, GS, or SS) and its 
descriptor to mem80.
\par\sb120
\page
#{\footnote section_b_4_311}
${\footnote B.4.311. SVLDT: Save LDTR and Descriptor}
+{\footnote browse:00531}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SVLDT}
\keepn\f2\b\fs30\sb60\sa60
B.4.311. {\f1 SVLDT}: Save LDTR and Descriptor
\par\pard\plain\sb120
\keep\f1\sb120
SVLDT m80                     ; 0F 7A /0        [486,CYRIX,SMM]\par\sb0
\pard\f0\sb120
{\f1 SVLDT} saves the Local Descriptor Table (LDTR) to mem80.
\par\sb120
\page
#{\footnote section_b_4_312}
${\footnote B.4.312. SVTS: Save TSR and Descriptor}
+{\footnote browse:00532}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SVTS}
\keepn\f2\b\fs30\sb60\sa60
B.4.312. {\f1 SVTS}: Save TSR and Descriptor
\par\pard\plain\sb120
\keep\f1\sb120
SVTS m80                      ; 0F 7C /0        [486,CYRIX,SMM]\par\sb0
\pard\f0\sb120
{\f1 SVTS} saves the Task State Register (TSR) to mem80.
\par\sb120
\page
#{\footnote section_b_4_313}
${\footnote B.4.313. SYSCALL: Call Operating System}
+{\footnote browse:00533}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SYSCALL}
\keepn\f2\b\fs30\sb60\sa60
B.4.313. {\f1 SYSCALL}: Call Operating System
\par\pard\plain\sb120
\keep\f1\sb120
SYSCALL                       ; 0F 05                [P6,AMD]\par\sb0
\pard\f0\sb120
{\f1 SYSCALL} provides a fast method of transferring control to a fixed 
entry point in an operating system.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 EIP} register is copied into the {\f1 ECX} register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Bits [31-0] of the 64-bit SYSCALL/SYSRET Target Address Register 
({\f1 STAR}) are copied into the {\f1 EIP} register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Bits [47-32] of the {\f1 STAR} register specify the selector that is copied 
into the {\f1 CS} register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Bits [47-32]+1000b of the {\f1 STAR} register specify the selector that is 
copied into the SS register.
\par\pard\sb120
The {\f1 CS} and {\f1 SS} registers should not be modified by the operating 
system between the execution of the {\f1 SYSCALL} instruction and its 
corresponding {\f1 SYSRET} instruction.
\par\sb120
For more information, see the 
{\f1 SYSCALL\'A0and\'A0SYSRET\'A0Instruction\'A0Specification} (AMD 
document number 21086.pdf).
\par\sb120
\page
#{\footnote section_b_4_314}
${\footnote B.4.314. SYSENTER: Fast System Call}
+{\footnote browse:00534}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SYSENTER}
\keepn\f2\b\fs30\sb60\sa60
B.4.314. {\f1 SYSENTER}: Fast System Call
\par\pard\plain\sb120
\keep\f1\sb120
SYSENTER                      ; 0F 34                [P6]\par\sb0
\pard\f0\sb120
{\f1 SYSENTER} executes a fast call to a level 0 system procedure or 
routine. Before using this instruction, various MSRs need to be set up:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 SYSENTER_CS_MSR} contains the 32-bit segment selector for the 
privilege level 0 code segment. (This value is also used to compute the 
segment selector of the privilege level 0 stack segment.)
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 SYSENTER_EIP_MSR} contains the 32-bit offset into the privilege level 
0 code segment to the first instruction of the selected operating procedure 
or routine.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 SYSENTER_ESP_MSR} contains the 32-bit stack pointer for the privilege 
level 0 stack.
\par\pard\sb120
{\f1 SYSENTER} performs the following sequence of operations:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Loads the segment selector from the {\f1 SYSENTER_CS_MSR} into the {\f1 CS} 
register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Loads the instruction pointer from the {\f1 SYSENTER_EIP_MSR} into the 
{\f1 EIP} register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Adds 8 to the value in {\f1 SYSENTER_CS_MSR} and loads it into the {\f1 SS} 
register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Loads the stack pointer from the {\f1 SYSENTER_ESP_MSR} into the {\f1 ESP} 
register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Switches to privilege level 0.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Clears the {\f1 VM} flag in the {\f1 EFLAGS} register, if the flag is set.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Begins executing the selected system procedure.
\par\pard\sb120
In particular, note that this instruction des not save the values of 
{\f1 CS} or {\f1 (E)IP}. If you need to return to the calling code, you 
need to write your code to cater for this.
\par\sb120
For more information, see the Intel Architecture Software Developer's 
Manual, Volume 2.
\par\sb120
\page
#{\footnote section_b_4_315}
${\footnote B.4.315. SYSEXIT: Fast Return From System Call}
+{\footnote browse:00535}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SYSEXIT}
\keepn\f2\b\fs30\sb60\sa60
B.4.315. {\f1 SYSEXIT}: Fast Return From System Call
\par\pard\plain\sb120
\keep\f1\sb120
SYSEXIT                       ; 0F 35                [P6,PRIV]\par\sb0
\pard\f0\sb120
{\f1 SYSEXIT} executes a fast return to privilege level 3 user code. This 
instruction is a companion instruction to the {\f1 SYSENTER} instruction, 
and can only be executed by privilege level 0 code. Various registers need 
to be set up before calling this instruction:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 SYSENTER_CS_MSR} contains the 32-bit segment selector for the 
privilege level 0 code segment in which the processor is currently 
executing. (This value is used to compute the segment selectors for the 
privilege level 3 code and stack segments.)
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 EDX} contains the 32-bit offset into the privilege level 3 code 
segment to the first instruction to be executed in the user code.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 ECX} contains the 32-bit stack pointer for the privilege level 3 
stack.
\par\pard\sb120
{\f1 SYSEXIT} performs the following sequence of operations:
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Adds 16 to the value in {\f1 SYSENTER_CS_MSR} and loads the sum into the 
{\f1 CS} selector register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Loads the instruction pointer from the {\f1 EDX} register into the 
{\f1 EIP} register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Adds 24 to the value in {\f1 SYSENTER_CS_MSR} and loads the sum into the 
{\f1 SS} selector register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Loads the stack pointer from the {\f1 ECX} register into the {\f1 ESP} 
register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Switches to privilege level 3.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Begins executing the user code at the {\f1 EIP} address.
\par\pard\sb120
For more information on the use of the {\f1 SYSENTER} and {\f1 SYSEXIT} 
instructions, see the Intel Architecture Software Developer's Manual, 
Volume 2.
\par\sb120
\page
#{\footnote section_b_4_316}
${\footnote B.4.316. SYSRET: Return From Operating System}
+{\footnote browse:00536}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote SYSRET}
\keepn\f2\b\fs30\sb60\sa60
B.4.316. {\f1 SYSRET}: Return From Operating System
\par\pard\plain\sb120
\keep\f1\sb120
SYSRET                        ; 0F 07                [P6,AMD,PRIV]\par\sb0
\pard\f0\sb120
{\f1 SYSRET} is the return instruction used in conjunction with the 
{\f1 SYSCALL} instruction to provide fast entry/exit to an operating 
system.
\par\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
The {\f1 ECX} register, which points to the next sequential instruction 
after the corresponding {\f1 SYSCALL} instruction, is copied into the 
{\f1 EIP} register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Bits [63-48] of the {\f1 STAR} register specify the selector that is copied 
into the {\f1 CS} register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Bits [63-48]+1000b of the {\f1 STAR} register specify the selector that is 
copied into the {\f1 SS} register.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
Bits [1-0] of the {\f1 SS} register are set to 11b (RPL of 3) regardless of 
the value of bits [49-48] of the {\f1 STAR} register.
\par\pard\sb120
The {\f1 CS} and {\f1 SS} registers should not be modified by the operating 
system between the execution of the {\f1 SYSCALL} instruction and its 
corresponding {\f1 SYSRET} instruction.
\par\sb120
For more information, see the 
{\f1 SYSCALL\'A0and\'A0SYSRET\'A0Instruction\'A0Specification} (AMD 
document number 21086.pdf).
\par\sb120
\page
#{\footnote section_b_4_317}
${\footnote B.4.317. TEST: Test Bits (notional bitwise AND)}
+{\footnote browse:00537}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote TEST}
\keepn\f2\b\fs30\sb60\sa60
B.4.317. {\f1 TEST}: Test Bits (notional bitwise AND)
\par\pard\plain\sb120
\keep\f1\sb120
TEST r/m8,reg8                ; 84 /r                [8086] \par\sb0
TEST r/m16,reg16              ; o16 85 /r            [8086] \par\sb0
TEST r/m32,reg32              ; o32 85 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
TEST r/m8,imm8                ; F6 /0 ib             [8086] \par\sb0
TEST r/m16,imm16              ; o16 F7 /0 iw         [8086] \par\sb0
TEST r/m32,imm32              ; o32 F7 /0 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
TEST AL,imm8                  ; A8 ib                [8086] \par\sb0
TEST AX,imm16                 ; o16 A9 iw            [8086] \par\sb0
TEST EAX,imm32                ; o32 A9 id            [386]\par\sb0
\pard\f0\sb120
{\f1 TEST} performs a `mental' bitwise AND of its two operands, and affects 
the flags as if the operation had taken place, but does not store the 
result of the operation anywhere.
\par\sb120
\page
#{\footnote section_b_4_318}
${\footnote B.4.318. UCOMISD: Unordered Scalar Double-Precision FP compare and set EFLAGS}
+{\footnote browse:00538}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote UCOMISD}
\keepn\f2\b\fs30\sb60\sa60
B.4.318. {\f1 UCOMISD}: Unordered Scalar Double-Precision FP compare and set EFLAGS
\par\pard\plain\sb120
\keep\f1\sb120
UCOMISD xmm1,xmm2/m128        ; 66 0F 2E /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 UCOMISD} compares the low-order double-precision FP numbers in the two 
operands, and sets the {\f1 ZF}, {\f1 PF} and {\f1 CF} bits in the 
{\f1 EFLAGS} register. In addition, the {\f1 OF}, {\f1 SF} and {\f1 AF} 
bits in the {\f1 EFLAGS} register are zeroed out. The unordered predicate 
({\f1 ZF}, {\f1 PF} and {\f1 CF} all set) is returned if either source 
operand is a {\f1 NaN} ({\f1 qNaN} or {\f1 sNaN}).
\par\sb120
\page
#{\footnote section_b_4_319}
${\footnote B.4.319. UCOMISS: Unordered Scalar Single-Precision FP compare and set EFLAGS}
+{\footnote browse:00539}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote UCOMISS}
\keepn\f2\b\fs30\sb60\sa60
B.4.319. {\f1 UCOMISS}: Unordered Scalar Single-Precision FP compare and set EFLAGS
\par\pard\plain\sb120
\keep\f1\sb120
UCOMISS xmm1,xmm2/m128        ; 0F 2E /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 UCOMISS} compares the low-order single-precision FP numbers in the two 
operands, and sets the {\f1 ZF}, {\f1 PF} and {\f1 CF} bits in the 
{\f1 EFLAGS} register. In addition, the {\f1 OF}, {\f1 SF} and {\f1 AF} 
bits in the {\f1 EFLAGS} register are zeroed out. The unordered predicate 
({\f1 ZF}, {\f1 PF} and {\f1 CF} all set) is returned if either source 
operand is a {\f1 NaN} ({\f1 qNaN} or {\f1 sNaN}).
\par\sb120
\page
#{\footnote section_b_4_320}
${\footnote B.4.320. UD0, UD1, UD2: Undefined Instruction}
+{\footnote browse:00540}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote UD0;
UD1;
UD2}
\keepn\f2\b\fs30\sb60\sa60
B.4.320. {\f1 UD0}, {\f1 UD1}, {\f1 UD2}: Undefined Instruction
\par\pard\plain\sb120
\keep\f1\sb120
UD0                           ; 0F FF                [186,UNDOC] \par\sb0
UD1                           ; 0F B9                [186,UNDOC] \par\sb0
UD2                           ; 0F 0B                [186]\par\sb0
\pard\f0\sb120
{\f1 UDx} can be used to generate an invalid opcode exception, for testing 
purposes.
\par\sb120
{\f1 UD0} is specifically documented by AMD as being reserved for this 
purpose.
\par\sb120
{\f1 UD1} is documented by Intel as being available for this purpose.
\par\sb120
{\f1 UD2} is specifically documented by Intel as being reserved for this 
purpose. Intel document this as the preferred method of generating an 
invalid opcode exception.
\par\sb120
All these opcodes can be used to generate invalid opcode exceptions on all 
currently available processors.
\par\sb120
\page
#{\footnote section_b_4_321}
${\footnote B.4.321. UMOV: User Move Data}
+{\footnote browse:00541}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote UMOV}
\keepn\f2\b\fs30\sb60\sa60
B.4.321. {\f1 UMOV}: User Move Data
\par\pard\plain\sb120
\keep\f1\sb120
UMOV r/m8,reg8                ; 0F 10 /r             [386,UNDOC] \par\sb0
UMOV r/m16,reg16              ; o16 0F 11 /r         [386,UNDOC] \par\sb0
UMOV r/m32,reg32              ; o32 0F 11 /r         [386,UNDOC]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
UMOV reg8,r/m8                ; 0F 12 /r             [386,UNDOC] \par\sb0
UMOV reg16,r/m16              ; o16 0F 13 /r         [386,UNDOC] \par\sb0
UMOV reg32,r/m32              ; o32 0F 13 /r         [386,UNDOC]\par\sb0
\pard\f0\sb120
This undocumented instruction is used by in-circuit emulators to access 
user memory (as opposed to host memory). It is used just like an ordinary 
memory/register or register/register {\f1 MOV} instruction, but accesses 
user space.
\par\sb120
This instruction is only available on some AMD and IBM 386 and 486 
processors.
\par\sb120
\page
#{\footnote section_b_4_322}
${\footnote B.4.322. UNPCKHPD: Unpack and Interleave High Packed Double-Precision FP Values}
+{\footnote browse:00542}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote UNPCKHPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.322. {\f1 UNPCKHPD}: Unpack and Interleave High Packed Double-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
UNPCKHPD xmm1,xmm2/m128       ; 66 0F 15 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 UNPCKHPD} performs an interleaved unpack of the high-order data 
elements of the source and destination operands, saving the result in 
{\f1 xmm1}. It ignores the lower half of the sources.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[63-0]   := dst[127-64]; \par\sb0
   dst[127-64] := src[127-64].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_323}
${\footnote B.4.323. UNPCKHPS: Unpack and Interleave High Packed Single-Precision FP Values}
+{\footnote browse:00543}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote UNPCKHPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.323. {\f1 UNPCKHPS}: Unpack and Interleave High Packed Single-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
UNPCKHPS xmm1,xmm2/m128       ; 0F 15 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 UNPCKHPS} performs an interleaved unpack of the high-order data 
elements of the source and destination operands, saving the result in 
{\f1 xmm1}. It ignores the lower half of the sources.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[31-0]   := dst[95-64]; \par\sb0
   dst[63-32]  := src[95-64]; \par\sb0
   dst[95-64]  := dst[127-96]; \par\sb0
   dst[127-96] := src[127-96].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_324}
${\footnote B.4.324. UNPCKLPD: Unpack and Interleave Low Packed Double-Precision FP Data}
+{\footnote browse:00544}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote UNPCKLPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.324. {\f1 UNPCKLPD}: Unpack and Interleave Low Packed Double-Precision FP Data
\par\pard\plain\sb120
\keep\f1\sb120
UNPCKLPD xmm1,xmm2/m128       ; 66 0F 14 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 UNPCKLPD} performs an interleaved unpack of the low-order data 
elements of the source and destination operands, saving the result in 
{\f1 xmm1}. It ignores the lower half of the sources.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[63-0]   := dst[63-0]; \par\sb0
   dst[127-64] := src[63-0].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_325}
${\footnote B.4.325. UNPCKLPS: Unpack and Interleave Low Packed Single-Precision FP Data}
+{\footnote browse:00545}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote UNPCKLPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.325. {\f1 UNPCKLPS}: Unpack and Interleave Low Packed Single-Precision FP Data
\par\pard\plain\sb120
\keep\f1\sb120
UNPCKLPS xmm1,xmm2/m128       ; 0F 14 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 UNPCKLPS} performs an interleaved unpack of the low-order data 
elements of the source and destination operands, saving the result in 
{\f1 xmm1}. It ignores the lower half of the sources.
\par\sb120
The operation of this instruction is:
\par\sb120
\keep\f1\sb120
   dst[31-0]   := dst[31-0]; \par\sb0
   dst[63-32]  := src[31-0]; \par\sb0
   dst[95-64]  := dst[63-32]; \par\sb0
   dst[127-96] := src[63-32].\par\sb0
\pard\f0\sb120
\page
#{\footnote section_b_4_326}
${\footnote B.4.326. VERR, VERW: Verify Segment Readability/Writability}
+{\footnote browse:00546}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote VERR;
VERW}
\keepn\f2\b\fs30\sb60\sa60
B.4.326. {\f1 VERR}, {\f1 VERW}: Verify Segment Readability/Writability
\par\pard\plain\sb120
\keep\f1\sb120
VERR r/m16                    ; 0F 00 /4             [286,PRIV]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
VERW r/m16                    ; 0F 00 /5             [286,PRIV]\par\sb0
\pard\f0\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 VERR} sets the zero flag if the segment specified by the selector in 
its operand can be read from at the current privilege level. Otherwise it 
is cleared.
\par\pard\sb120
\tx360\li360\fi-360{\f3\'9F}\tab
{\f1 VERW} sets the zero flag if the segment can be written.
\par\pard\sb120
\page
#{\footnote section_b_4_327}
${\footnote B.4.327. WAIT: Wait for Floating-Point Processor}
+{\footnote browse:00547}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote WAIT}
\keepn\f2\b\fs30\sb60\sa60
B.4.327. {\f1 WAIT}: Wait for Floating-Point Processor
\par\pard\plain\sb120
\keep\f1\sb120
WAIT                          ; 9B                   [8086] \par\sb0
FWAIT                         ; 9B                   [8086]\par\sb0
\pard\f0\sb120
{\f1 WAIT}, on 8086 systems with a separate 8087 FPU, waits for the FPU to 
have finished any operation it is engaged in before continuing main 
processor operations, so that (for example) an FPU store to main memory can 
be guaranteed to have completed before the CPU tries to read the result 
back out.
\par\sb120
On higher processors, {\f1 WAIT} is unnecessary for this purpose, and it 
has the alternative purpose of ensuring that any pending unmasked FPU 
exceptions have happened before execution continues.
\par\sb120
\page
#{\footnote section_b_4_328}
${\footnote B.4.328. WBINVD: Write Back and Invalidate Cache}
+{\footnote browse:00548}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote WBINVD}
\keepn\f2\b\fs30\sb60\sa60
B.4.328. {\f1 WBINVD}: Write Back and Invalidate Cache
\par\pard\plain\sb120
\keep\f1\sb120
WBINVD                        ; 0F 09                [486]\par\sb0
\pard\f0\sb120
{\f1 WBINVD} invalidates and empties the processor's internal caches, and 
causes the processor to instruct external caches to do the same. It writes 
the contents of the caches back to memory first, so no data is lost. To 
flush the caches quickly without bothering to write the data back first, 
use {\f1 INVD} ({\uldb section B.4.125}{\v section_b_4_125}).
\par\sb120
\page
#{\footnote section_b_4_329}
${\footnote B.4.329. WRMSR: Write Model-Specific Registers}
+{\footnote browse:00549}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote WRMSR}
\keepn\f2\b\fs30\sb60\sa60
B.4.329. {\f1 WRMSR}: Write Model-Specific Registers
\par\pard\plain\sb120
\keep\f1\sb120
WRMSR                         ; 0F 30                [PENT]\par\sb0
\pard\f0\sb120
{\f1 WRMSR} writes the value in {\f1 EDX:EAX} to the processor 
Model-Specific Register (MSR) whose index is stored in {\f1 ECX}. See also 
{\f1 RDMSR} ({\uldb section B.4.270}{\v section_b_4_270}).
\par\sb120
\page
#{\footnote section_b_4_330}
${\footnote B.4.330. WRSHR: Write SMM Header Pointer Register}
+{\footnote browse:00550}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote WRSHR}
\keepn\f2\b\fs30\sb60\sa60
B.4.330. {\f1 WRSHR}: Write SMM Header Pointer Register
\par\pard\plain\sb120
\keep\f1\sb120
WRSHR r/m32                   ; 0F 37 /0        [386,CYRIX,SMM]\par\sb0
\pard\f0\sb120
{\f1 WRSHR} loads the contents of either a 32-bit memory location or a 
32-bit register into the SMM header pointer register.
\par\sb120
See also {\f1 RDSHR} ({\uldb section B.4.272}{\v section_b_4_272}).
\par\sb120
\page
#{\footnote section_b_4_331}
${\footnote B.4.331. XADD: Exchange and Add}
+{\footnote browse:00551}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote XADD}
\keepn\f2\b\fs30\sb60\sa60
B.4.331. {\f1 XADD}: Exchange and Add
\par\pard\plain\sb120
\keep\f1\sb120
XADD r/m8,reg8                ; 0F C0 /r             [486] \par\sb0
XADD r/m16,reg16              ; o16 0F C1 /r         [486] \par\sb0
XADD r/m32,reg32              ; o32 0F C1 /r         [486]\par\sb0
\pard\f0\sb120
{\f1 XADD} exchanges the values in its two operands, and then adds them 
together and writes the result into the destination (first) operand. This 
instruction can be used with a {\f1 LOCK} prefix for multi-processor 
synchronisation purposes.
\par\sb120
\page
#{\footnote section_b_4_332}
${\footnote B.4.332. XBTS: Extract Bit String}
+{\footnote browse:00552}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote XBTS}
\keepn\f2\b\fs30\sb60\sa60
B.4.332. {\f1 XBTS}: Extract Bit String
\par\pard\plain\sb120
\keep\f1\sb120
XBTS reg16,r/m16              ; o16 0F A6 /r         [386,UNDOC] \par\sb0
XBTS reg32,r/m32              ; o32 0F A6 /r         [386,UNDOC]\par\sb0
\pard\f0\sb120
The implied operation of this instruction is:
\par\sb120
\keep\f1\sb120
XBTS r/m16,reg16,AX,CL \par\sb0
XBTS r/m32,reg32,EAX,CL\par\sb0
\pard\f0\sb120
Writes a bit string from the source operand to the destination. {\f1 CL} 
indicates the number of bits to be copied, and {\f1 (E)AX} indicates the 
low order bit offset in the source. The bits are written to the low order 
bits of the destination register. For example, if {\f1 CL} is set to 4 and 
{\f1 AX} (for 16-bit code) is set to 5, bits 5-8 of {\f1 src} will be 
copied to bits 0-3 of {\f1 dst}. This instruction is very poorly 
documented, and I have been unable to find any official source of 
documentation on it.
\par\sb120
{\f1 XBTS} is supported only on the early Intel 386s, and conflicts with 
the opcodes for {\f1 CMPXCHG486} (on early Intel 486s). NASM supports it 
only for completeness. Its counterpart is {\f1 IBTS} (see {\uldb section 
B.4.116}{\v section_b_4_116}).
\par\sb120
\page
#{\footnote section_b_4_333}
${\footnote B.4.333. XCHG: Exchange}
+{\footnote browse:00553}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote XCHG}
\keepn\f2\b\fs30\sb60\sa60
B.4.333. {\f1 XCHG}: Exchange
\par\pard\plain\sb120
\keep\f1\sb120
XCHG reg8,r/m8                ; 86 /r                [8086] \par\sb0
XCHG reg16,r/m8               ; o16 87 /r            [8086] \par\sb0
XCHG reg32,r/m32              ; o32 87 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
XCHG r/m8,reg8                ; 86 /r                [8086] \par\sb0
XCHG r/m16,reg16              ; o16 87 /r            [8086] \par\sb0
XCHG r/m32,reg32              ; o32 87 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
XCHG AX,reg16                 ; o16 90+r             [8086] \par\sb0
XCHG EAX,reg32                ; o32 90+r             [386] \par\sb0
XCHG reg16,AX                 ; o16 90+r             [8086] \par\sb0
XCHG reg32,EAX                ; o32 90+r             [386]\par\sb0
\pard\f0\sb120
{\f1 XCHG} exchanges the values in its two operands. It can be used with a 
{\f1 LOCK} prefix for purposes of multi-processor synchronisation.
\par\sb120
{\f1 XCHG\'A0AX,AX} or {\f1 XCHG\'A0EAX,EAX} (depending on the {\f1 BITS} 
setting) generates the opcode {\f1 90h}, and so is a synonym for {\f1 NOP} 
({\uldb section B.4.190}{\v section_b_4_190}).
\par\sb120
\page
#{\footnote section_b_4_334}
${\footnote B.4.334. XLATB: Translate Byte in Lookup Table}
+{\footnote browse:00554}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote a16;
a32;
XLATB}
\keepn\f2\b\fs30\sb60\sa60
B.4.334. {\f1 XLATB}: Translate Byte in Lookup Table
\par\pard\plain\sb120
\keep\f1\sb120
XLAT                          ; D7                   [8086] \par\sb0
XLATB                         ; D7                   [8086]\par\sb0
\pard\f0\sb120
{\f1 XLATB} adds the value in {\f1 AL}, treated as an unsigned byte, to 
{\f1 BX} or {\f1 EBX}, and loads the byte from the resulting address (in 
the segment specified by {\f1 DS}) back into {\f1 AL}.
\par\sb120
The base register used is {\f1 BX} if the address size is 16 bits, and 
{\f1 EBX} if it is 32 bits. If you need to use an address size not equal to 
the current {\f1 BITS} setting, you can use an explicit {\f1 a16} or 
{\f1 a32} prefix.
\par\sb120
The segment register used to load from {\f1 [BX+AL]} or {\f1 [EBX+AL]} can 
be overridden by using a segment register name as a prefix (for example, 
{\f1 es\'A0xlatb}).
\par\sb120
\page
#{\footnote section_b_4_335}
${\footnote B.4.335. XOR: Bitwise Exclusive OR}
+{\footnote browse:00555}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote XOR}
\keepn\f2\b\fs30\sb60\sa60
B.4.335. {\f1 XOR}: Bitwise Exclusive OR
\par\pard\plain\sb120
\keep\f1\sb120
XOR r/m8,reg8                 ; 30 /r                [8086] \par\sb0
XOR r/m16,reg16               ; o16 31 /r            [8086] \par\sb0
XOR r/m32,reg32               ; o32 31 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
XOR reg8,r/m8                 ; 32 /r                [8086] \par\sb0
XOR reg16,r/m16               ; o16 33 /r            [8086] \par\sb0
XOR reg32,r/m32               ; o32 33 /r            [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
XOR r/m8,imm8                 ; 80 /6 ib             [8086] \par\sb0
XOR r/m16,imm16               ; o16 81 /6 iw         [8086] \par\sb0
XOR r/m32,imm32               ; o32 81 /6 id         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
XOR r/m16,imm8                ; o16 83 /6 ib         [8086] \par\sb0
XOR r/m32,imm8                ; o32 83 /6 ib         [386]\par\sb0
\pard\f0\sb120
\keep\f1\sb120
XOR AL,imm8                   ; 34 ib                [8086] \par\sb0
XOR AX,imm16                  ; o16 35 iw            [8086] \par\sb0
XOR EAX,imm32                 ; o32 35 id            [386]\par\sb0
\pard\f0\sb120
{\f1 XOR} performs a bitwise XOR operation between its two operands (i.e. 
each bit of the result is 1 if and only if exactly one of the corresponding 
bits of the two inputs was 1), and stores the result in the destination 
(first) operand.
\par\sb120
In the forms with an 8-bit immediate second operand and a longer first 
operand, the second operand is considered to be signed, and is 
sign-extended to the length of the first operand. In these cases, the 
{\f1 BYTE} qualifier is necessary to force NASM to generate this form of 
the instruction.
\par\sb120
The {\f1 MMX} instruction {\f1 PXOR} (see {\uldb section 
B.4.266}{\v section_b_4_266}) performs the same operation on the 64-bit 
{\f1 MMX} registers.
\par\sb120
\page
#{\footnote section_b_4_336}
${\footnote B.4.336. XORPD: Bitwise Logical XOR of Double-Precision FP Values}
+{\footnote browse:00556}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote XORPD}
\keepn\f2\b\fs30\sb60\sa60
B.4.336. {\f1 XORPD}: Bitwise Logical XOR of Double-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
XORPD xmm1,xmm2/m128          ; 66 0F 57 /r     [WILLAMETTE,SSE2]\par\sb0
\pard\f0\sb120
{\f1 XORPD} returns a bit-wise logical XOR between the source and 
destination operands, storing the result in the destination operand.
\par\sb120
\page
#{\footnote section_b_4_337}
${\footnote B.4.337. XORPS: Bitwise Logical XOR of Single-Precision FP Values}
+{\footnote browse:00557}
!{\footnote ChangeButtonBinding("btn_up","JumpId(`nasmdoc.hlp',`section_b_4')");
EnableButton("btn_up")}
K{\footnote XORPS}
\keepn\f2\b\fs30\sb60\sa60
B.4.337. {\f1 XORPS}: Bitwise Logical XOR of Single-Precision FP Values
\par\pard\plain\sb120
\keep\f1\sb120
XORPS xmm1,xmm2/m128          ; 0F 57 /r        [KATMAI,SSE]\par\sb0
\pard\f0\sb120
{\f1 XORPS} returns a bit-wise logical XOR between the source and 
destination operands, storing the result in the destination operand.
\page}