GNU Info

(as.info)MIPS Opts

---

Next: MIPS Object Up: MIPS-Dependent

---

Enter node , (file) or (file)node

Assembler options
-----------------

   The MIPS configurations of GNU `as' support these special options:

`-G NUM'
     This option sets the largest size of an object that can be
     referenced implicitly with the `gp' register.  It is only accepted
     for targets that use ECOFF format.  The default value is 8.

`-EB'
`-EL'
     Any MIPS configuration of `as' can select big-endian or
     little-endian output at run time (unlike the other GNU development
     tools, which must be configured for one or the other).  Use `-EB'
     to select big-endian output, and `-EL' for little-endian.

`-mips1'
`-mips2'
`-mips3'
`-mips4'
`-mips5'
`-mips32'
`-mips64'
     Generate code for a particular MIPS Instruction Set Architecture
     level.  `-mips1' corresponds to the R2000 and R3000 processors,
     `-mips2' to the R6000 processor, `-mips3' to the R4000 processor,
     and `-mips4' to the R8000 and R10000 processors.  `-mips5',
     `-mips32', and `-mips64' correspond to generic MIPS V, MIPS32, and
     MIPS64 ISA processors, respectively.  You can also switch
     instruction sets during the assembly; see Note: Directives to
     override the ISA level.

`-mgp32'
`-mfp32'
     Some macros have different expansions for 32-bit and 64-bit
     registers.  The register sizes are normally inferred from the ISA
     and ABI, but these flags force a certain group of registers to be
     treated as 32 bits wide at all times.  `-mgp32' controls the size
     of general-purpose registers and `-mfp32' controls the size of
     floating-point registers.

     On some MIPS variants there is a 32-bit mode flag; when this flag
     is set, 64-bit instructions generate a trap.  Also, some 32-bit
     OSes only save the 32-bit registers on a context switch, so it is
     essential never to use the 64-bit registers.

`-mgp64'
     Assume that 64-bit general purpose registers are available.  This
     is provided in the interests of symmetry with -gp32.

`-mips16'
`-no-mips16'
     Generate code for the MIPS 16 processor.  This is equivalent to
     putting `.set mips16' at the start of the assembly file.
     `-no-mips16' turns off this option.

`-mfix7000'
`-no-mfix7000'
     Cause nops to be inserted if the read of the destination register
     of an mfhi or mflo instruction occurs in the following two
     instructions.

`-m4010'
`-no-m4010'
     Generate code for the LSI R4010 chip.  This tells the assembler to
     accept the R4010 specific instructions (`addciu', `ffc', etc.),
     and to not schedule `nop' instructions around accesses to the `HI'
     and `LO' registers.  `-no-m4010' turns off this option.

`-m4650'
`-no-m4650'
     Generate code for the MIPS R4650 chip.  This tells the assembler
     to accept the `mad' and `madu' instruction, and to not schedule
     `nop' instructions around accesses to the `HI' and `LO' registers.
     `-no-m4650' turns off this option.

`-m3900'
`-no-m3900'
`-m4100'
`-no-m4100'
     For each option `-mNNNN', generate code for the MIPS RNNNN chip.
     This tells the assembler to accept instructions specific to that
     chip, and to schedule for that chip's hazards.

`-march=CPU'
     Generate code for a particular MIPS cpu.  It is exactly equivalent
     to `-mCPU', except that there are more value of CPU understood.
     Valid CPU value are:

          2000, 3000, 3900, 4000, 4010, 4100, 4111, 4300, 4400, 4600,
          4650, 5000, rm5200, rm5230, rm5231, rm5261, rm5721, 6000,
          rm7000, 8000, 10000, 12000, mips32-4k, sb1

`-mtune=CPU'
     Schedule and tune for a particular MIPS cpu.  Valid CPU values are
     identical to `-march=CPU'.

`-mcpu=CPU'
     Generate code and schedule for a particular MIPS cpu.  This is
     exactly equivalent to `-march=CPU' and `-mtune=CPU'.  Valid CPU
     values are identical to `-march=CPU'.  Use of this option is
     discouraged.

`-nocpp'
     This option is ignored.  It is accepted for command-line
     compatibility with other assemblers, which use it to turn off C
     style preprocessing.  With GNU `as', there is no need for
     `-nocpp', because the GNU assembler itself never runs the C
     preprocessor.

`--construct-floats'
`--no-construct-floats'
     The `--no-construct-floats' option disables the construction of
     double width floating point constants by loading the two halves of
     the value into the two single width floating point registers that
     make up the double width register.  This feature is useful if the
     processor support the FR bit in its status  register, and this bit
     is known (by the programmer) to be set.  This bit prevents the
     aliasing of the double width register by the single width
     registers.

     By default `--construct-floats' is selected, allowing construction
     of these floating point constants.

`--trap'
`--no-break'
     `as' automatically macro expands certain division and
     multiplication instructions to check for overflow and division by
     zero.  This option causes `as' to generate code to take a trap
     exception rather than a break exception when an error is detected.
     The trap instructions are only supported at Instruction Set
     Architecture level 2 and higher.

`--break'
`--no-trap'
     Generate code to take a break exception rather than a trap
     exception when an error is detected.  This is the default.

`-n'
     When this option is used, `as' will issue a warning every time it
     generates a nop instruction from a macro.