GNU Info
(gcc-300.info)ARM Options
ARM Options
-----------
These `-m' options are defined for Advanced RISC Machines (ARM)
architectures:
`-mapcs-frame'
Generate a stack frame that is compliant with the ARM Procedure
Call Standard for all functions, even if this is not strictly
necessary for correct execution of the code. Specifying
`-fomit-frame-pointer' with this option will cause the stack
frames not to be generated for leaf functions. The default is
`-mno-apcs-frame'.
`-mapcs'
This is a synonym for `-mapcs-frame'.
`-mapcs-26'
Generate code for a processor running with a 26-bit program
counter, and conforming to the function calling standards for the
APCS 26-bit option. This option replaces the `-m2' and `-m3'
options of previous releases of the compiler.
`-mapcs-32'
Generate code for a processor running with a 32-bit program
counter, and conforming to the function calling standards for the
APCS 32-bit option. This option replaces the `-m6' option of
previous releases of the compiler.
`-mthumb-interwork'
Generate code which supports calling between the ARM and Thumb
instruction sets. Without this option the two instruction sets
cannot be reliably used inside one program. The default is
`-mno-thumb-interwork', since slightly larger code is generated
when `-mthumb-interwork' is specified.
`-mno-sched-prolog'
Prevent the reordering of instructions in the function prolog, or
the merging of those instruction with the instructions in the
function's body. This means that all functions will start with a
recognizable set of instructions (or in fact one of a choice from
a small set of different function prologues), and this information
can be used to locate the start if functions inside an executable
piece of code. The default is `-msched-prolog'.
`-mhard-float'
Generate output containing floating point instructions. This is
the default.
`-msoft-float'
Generate output containing library calls for floating point.
*Warning:* the requisite libraries are not available for all ARM
targets. Normally the facilities of the machine's usual C
compiler are used, but this cannot be done directly in
cross-compilation. You must make your own arrangements to provide
suitable library functions for cross-compilation.
`-msoft-float' changes the calling convention in the output file;
therefore, it is only useful if you compile _all_ of a program with
this option. In particular, you need to compile `libgcc.a', the
library that comes with GCC, with `-msoft-float' in order for this
to work.
`-mlittle-endian'
Generate code for a processor running in little-endian mode. This
is the default for all standard configurations.
`-mbig-endian'
Generate code for a processor running in big-endian mode; the
default is to compile code for a little-endian processor.
`-mwords-little-endian'
This option only applies when generating code for big-endian
processors. Generate code for a little-endian word order but a
big-endian byte order. That is, a byte order of the form
`32107654'. Note: this option should only be used if you require
compatibility with code for big-endian ARM processors generated by
versions of the compiler prior to 2.8.
`-malignment-traps'
Generate code that will not trap if the MMU has alignment traps
enabled. On ARM architectures prior to ARMv4, there were no
instructions to access half-word objects stored in memory.
However, when reading from memory a feature of the ARM
architecture allows a word load to be used, even if the address is
unaligned, and the processor core will rotate the data as it is
being loaded. This option tells the compiler that such misaligned
accesses will cause a MMU trap and that it should instead
synthesise the access as a series of byte accesses. The compiler
can still use word accesses to load half-word data if it knows
that the address is aligned to a word boundary.
This option is ignored when compiling for ARM architecture 4 or
later, since these processors have instructions to directly access
half-word objects in memory.
`-mno-alignment-traps'
Generate code that assumes that the MMU will not trap unaligned
accesses. This produces better code when the target instruction
set does not have half-word memory operations (i.e.
implementations prior to ARMv4).
Note that you cannot use this option to access unaligned word
objects, since the processor will only fetch one 32-bit aligned
object from memory.
The default setting for most targets is `-mno-alignment-traps',
since this produces better code when there are no half-word memory
instructions available.
`-mshort-load-bytes'
`-mno-short-load-words'
These are deprecated aliases for `-malignment-traps'.
`-mno-short-load-bytes'
`-mshort-load-words'
This are deprecated aliases for `-mno-alignment-traps'.
`-mbsd'
This option only applies to RISC iX. Emulate the native BSD-mode
compiler. This is the default if `-ansi' is not specified.
`-mxopen'
This option only applies to RISC iX. Emulate the native
X/Open-mode compiler.
`-mno-symrename'
This option only applies to RISC iX. Do not run the assembler
post-processor, `symrename', after code has been assembled.
Normally it is necessary to modify some of the standard symbols in
preparation for linking with the RISC iX C library; this option
suppresses this pass. The post-processor is never run when the
compiler is built for cross-compilation.
`-mcpu=NAME'
This specifies the name of the target ARM processor. GCC uses
this name to determine what kind of instructions it can emit when
generating assembly code. Permissible names are: `arm2', `arm250',
`arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7',
`arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700',
`arm700i', `arm710', `arm710c', `arm7100', `arm7500', `arm7500fe',
`arm7tdmi', `arm8', `strongarm', `strongarm110', `strongarm1100',
`arm8', `arm810', `arm9', `arm9e', `arm920', `arm920t', `arm940t',
`arm9tdmi', `arm10tdmi', `arm1020t', `xscale'.
`-mtune=NAME'
This option is very similar to the `-mcpu=' option, except that
instead of specifying the actual target processor type, and hence
restricting which instructions can be used, it specifies that GCC
should tune the performance of the code as if the target were of
the type specified in this option, but still choosing the
instructions that it will generate based on the cpu specified by a
`-mcpu=' option. For some ARM implementations better performance
can be obtained by using this option.
`-march=NAME'
This specifies the name of the target ARM architecture. GCC uses
this name to determine what kind of instructions it can emit when
generating assembly code. This option can be used in conjunction
with or instead of the `-mcpu=' option. Permissible names are:
`armv2', `armv2a', `armv3', `armv3m', `armv4', `armv4t', `armv5',
`armv5t', `armv5te'.
`-mfpe=NUMBER'
`-mfp=NUMBER'
This specifies the version of the floating point emulation
available on the target. Permissible values are 2 and 3. `-mfp='
is a synonym for `-mfpe=', for compatibility with older versions
of GCC.
`-mstructure-size-boundary=N'
The size of all structures and unions will be rounded up to a
multiple of the number of bits set by this option. Permissible
values are 8 and 32. The default value varies for different
toolchains. For the COFF targeted toolchain the default value is
8. Specifying the larger number can produce faster, more
efficient code, but can also increase the size of the program.
The two values are potentially incompatible. Code compiled with
one value cannot necessarily expect to work with code or libraries
compiled with the other value, if they exchange information using
structures or unions.
`-mabort-on-noreturn'
Generate a call to the function `abort' at the end of a `noreturn'
function. It will be executed if the function tries to return.
`-mlong-calls'
`-mno-long-calls'
Tells the compiler to perform function calls by first loading the
address of the function into a register and then performing a
subroutine call on this register. This switch is needed if the
target function will lie outside of the 64 megabyte addressing
range of the offset based version of subroutine call instruction.
Even if this switch is enabled, not all function calls will be
turned into long calls. The heuristic is that static functions,
functions which have the `short-call' attribute, functions that
are inside the scope of a `#pragma no_long_calls' directive and
functions whose definitions have already been compiled within the
current compilation unit, will not be turned into long calls. The
exception to this rule is that weak function definitions,
functions with the `long-call' attribute or the `section'
attribute, and functions that are within the scope of a `#pragma
long_calls' directive, will always be turned into long calls.
This feature is not enabled by default. Specifying
`-mno-long-calls' will restore the default behaviour, as will
placing the function calls within the scope of a `#pragma
long_calls_off' directive. Note these switches have no effect on
how the compiler generates code to handle function calls via
function pointers.
`-mnop-fun-dllimport'
Disable support for the `dllimport' attribute.
`-msingle-pic-base'
Treat the register used for PIC addressing as read-only, rather
than loading it in the prologue for each function. The run-time
system is responsible for initialising this register with an
appropriate value before execution begins.
`-mpic-register=REG'
Specify the register to be used for PIC addressing. The default
is R10 unless stack-checking is enabled, when R9 is used.
`-mpoke-function-name'
Write the name of each function into the text section, directly
preceding the function prologue. The generated code is similar to
this:
t0
.ascii "arm_poke_function_name", 0
.align
t1
.word 0xff000000 + (t1 - t0)
arm_poke_function_name
mov ip, sp
stmfd sp!, {fp, ip, lr, pc}
sub fp, ip, #4
When performing a stack backtrace, code can inspect the value of
`pc' stored at `fp + 0'. If the trace function then looks at
location `pc - 12' and the top 8 bits are set, then we know that
there is a function name embedded immediately preceding this
location and has length `((pc[-3]) & 0xff000000)'.
`-mthumb'
Generate code for the 16-bit Thumb instruction set. The default
is to use the 32-bit ARM instruction set.
`-mtpcs-frame'
Generate a stack frame that is compliant with the Thumb Procedure
Call Standard for all non-leaf functions. (A leaf function is one
that does not call any other functions.) The default is
`-mno-tpcs-frame'.
`-mtpcs-leaf-frame'
Generate a stack frame that is compliant with the Thumb Procedure
Call Standard for all leaf functions. (A leaf function is one
that does not call any other functions.) The default is
`-mno-apcs-leaf-frame'.
`-mcallee-super-interworking'
Gives all externally visible functions in the file being compiled
an ARM instruction set header which switches to Thumb mode before
executing the rest of the function. This allows these functions
to be called from non-interworking code.
`-mcaller-super-interworking'
Allows calls via function pointers (including virtual functions) to
execute correctly regardless of whether the target code has been
compiled for interworking or not. There is a small overhead in
the cost of executing a function pointer if this option is enabled.
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